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- 22 May, 2014 2 commits
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Martijn de Gouw authored
OCA4080 overview: - 1.466 GHz Freescale QorIQ P4080E Processor - 4Gbyte DDR3 on board - 8Mbyte Nor flash - Serial RapidIO 1.2 - 1 x 10/100/1000 BASE-T front ethernet - 1 x 1000 BASE-BX ethernet on AMC connector Signed-off-by:
Martijn de Gouw <martijn.de.gouw@prodrive.nl> [scottwood@freescale.com: minor conflict-related changes] Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Valentin Longchamp authored
This patch introduces the support for Keymile's kmcoge4 board which is the internal reference design for boards based on Freescale's P2040/P2041 SoCs. This internal reference design is named kmp204x. The peripherals used on this board are: - SPI NOR Flash as bootloader medium - NAND Flash with a ubi partition - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 4 Local Bus windows, with one dedicated to the QRIO reset/power mgmt CPLD - 2 I2C busses - last but not least, the mandatory serial port The patch also adds a defconfig file for this reference design that is necessary because of the lowmem option that must be set higher due to the number of PCIe devices with big ioremapped mem ranges on the boad. Signed-off-by:
Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 08 Jan, 2014 1 commit
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Xie Xiaobo authored
TWR-P1025 Overview ----------------- 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Signed-off-by:
Michael Johnston <michael.johnston@freescale.com> Signed-off-by:
Xie Xiaobo <X.Xie@freescale.com> [scottwood@freescale.com: use pr_info rather than KERN_INFO] Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 29 Oct, 2013 2 commits
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Kevin Hao authored
Currently all these boards use the same machine struct and also select the same kernel options, so it seems a bit of redundant to keep one separate kernel option for each board. Also update the defconfigs according to this change. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Kevin Hao authored
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds, p5020ds, p5040ds, t4240qds and b4qds are almost the same except the machine name. So this introduces a cornet_generic machine to support all these boards to avoid the code duplication. With these changes the file corenet_ds.h becomes useless. Just delete it. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 24 Aug, 2013 2 commits
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Mingkai Hu authored
C293PCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by:
Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by:
Po Liu <Po.Liu@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Chunhe Lan authored
P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by:
Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 10 Apr, 2013 1 commit
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Shaveta Leekha authored
- Add support for B4 board in board file b4_qds.c, It is common for B4860, B4420 and B4220QDS as they share same QDS board - Add B4QDS support in Kconfig and Makefile B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor, with following major features: - Four dual-threaded e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz - Two DDR3/3L controllers for high-speed memory interface each runs at up to 1866.67 MHz - CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN - Large internal cache memory with snooping and stashing capabilities - Sixteen 10-GHz SerDes lanes that serve: - Two SRIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes - Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less antenna connection - Two 10-Gbit Ethernet controllers (10GEC) - Six 1G/2.5-Gbit Ethernet controllers for network communications - PCI Express controller - Debug (Aurora) - Various system peripherals B4420 and B4220 have some differences in comparison to B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420: B4420 has: - Fewer e6500 cores: 1 cluster with 2 e6500 cores - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.6GHz - 2 X 4 lane serdes - 3 SGMII interfaces - no sRIO - no 10G Key differences between B4860 and B4220: B4220 has: - Fewer e6500 cores: 1 cluster with 1 e6500 core - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.33GHz - 2 X 2 lane serdes - 2 SGMII interfaces - no sRIO - no 10G Signed-off-by:
Shaveta Leekha <shaveta@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 20 Mar, 2013 1 commit
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Alexandre Courbot authored
ARCH_REQUIRE_GPIOLIB selects GENERIC_GPIO, so there is no need to select it explicitly. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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- 12 Mar, 2013 1 commit
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Kumar Gala authored
Some minor changes to the common corenet_ds.c code are needed to support the T4240QDS: * Add support for "fsl,qoriq-pcie-v3.0" controller * Bump max # of IRQs to 512 (T4240 supports more interrupts than previous SoCs). Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 15 Feb, 2013 1 commit
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Stef van Os authored
Initial board support for the Prodrive PPA8548 AMC module. Board is an MPC8548 AMC platform used in RapidIO systems. This module is also used to test/work on mainline linux RapidIO software. PPA8548 overview: - 1.3 GHz Freescale PowerQUICC III MPC8548 processor - 1 GB DDR2 @ 266 MHz - 8 MB NOR flash - Serial RapidIO 1.2 - 1 x 10/100/1000 BASE-T front ethernet - 1 x 1000 BASE-BX ethernet on AMC connector Signed-off-by:
Stef van Os <stef.van.os@prodrive.nl> Acked-by:
Timur Tabi <timur@tabi.org> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 29 Jan, 2013 1 commit
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Benjamin Collins authored
CTS-1000 is based on P4080. GPIO 27 is used to signal the FPGA to switch off power, and also associates IRQ 8 with front-panel button press (which we use to call orderly_poweroff()). The relevant device-tree looks like this: gpio0: gpio@130000 { compatible = "fsl,qoriq-gpio"; reg = <0x130000 0x1000>; interrupts = <55 2 0 0>; #gpio-cells = <2>; gpio-controller; /* Allows powering off the system via GPIO signal. */ gpio-halt@27 { compatible = "sgy,gpio-halt"; gpios = <&gpio0 27 0>; interrupts = <8 1 0 0>; }; }; Because the driver cannot match on sgy,gpio-halt (because the node is never processed through of_platform), it matches on fsl,qoriq-gpio and then checks child nodes for the matching sgy,gpio-halt. This also ensures that the GPIO controller is detected prior to sgy_cts1000's probe callback, since that node wont match via of_platform until the controller is registered. Also, because the GPIO handler for triggering system poweroff might sleep, the IRQ uses a workqueue to call orderly_poweroff(). As a final note, this driver may be expanded for other features specific to the CTS-1000. Signed-off-by:
Ben Collins <ben.c@servergy.com> Cc: Jack Smith <jack.s@servergy.com> Cc: Vihar Rai <vihar.r@servergy.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 21 Jan, 2013 1 commit
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Kees Cook authored
The CONFIG_EXPERIMENTAL config item has not carried much meaning for a while now and is almost always enabled by default. As agreed during the Linux kernel summit, remove it from any "depends on" lines in Kconfigs. CC: Kumar Gala <galak@kernel.crashing.org> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: Paul Mackerras <paulus@samba.org> Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 12 Sep, 2012 2 commits
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Timur Tabi authored
The Freescale / iVeia P1022RDK reference board is a small-factor board with a Freescale P1022 SOC. It includes: 1) 512 MB 64-bit DDR3-800 (max) memory 2) 8MB SPI serial flash memory for boot loader 3) Bootable 4-bit SD/MMC port 4) Two 10/100/1000 Ethernet connectors 5) One SATA port 6) Two USB ports 7) One PCIe x4 slot 8) DVI video connector 9) Audio input and output jacks, powered by a Wolfson WM8960 codec. Unlike the P1022DS, the P1022RDK does not have any localbus devices, presumably because of the localbus / DIU multiplexing restriction of the P1022 SOC. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which is similar to the P5020DS. Features of the P5040 are listed below, but not all of these features (e.g. DPAA networking) are currently supported. Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 11 Jul, 2012 1 commit
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Scott Wood authored
This gives the kernel a paravirtualized machine to target, without requiring both sides to pretend to be targeting a specific board that likely has little to do with the host in KVM scenarios. This avoids the need to add new boards to QEMU just to be able to run KVM on new CPUs. As this is the first platform that can run with either e500v2 or e500mc, CONFIG_PPC_E500MC is now a legitimately user configurable option, so add a help text. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 10 Jul, 2012 3 commits
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Prabhakar Kushwaha authored
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by:
Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by:
Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
This reverts commit 96cc017c. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Paul Gortmaker authored
This reference board dates back to 2004, and is largely a legacy EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is a more modern, better e500v2 target for people to use as a reference board with today's kernels, should they require one. Removing support for it will also allow us to remove some sbc8560 specific quirk handling in 8250 UART code, and some MTD mapping support. Cc: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 16 Mar, 2012 4 commits
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chenhui zhao authored
Enable RapidIO and add rapidio and rmu nodes to dts. Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
Remove the "select PHYS_64BIT" from the Kconfig entry for the P1022DS, so that large physical address support is a selectable option for non-CoreNet reference boards. The option is enabled in mpc85xx_[smp_]defconfig so that the default is unchanged. However, now it can be deselected. The P1022DS had this option defined because the default device tree for this board uses 36-bit addresses. This had the side-effect of forcing this option on for all boards that use mpc85xx_[smp_]defconfig. Some users may want to disable this feature to create an optimized configuration for boards with <= 2GB of RAM. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Claudiu Manoil authored
fsl_85xx_l2ctlr.o and fsl_85xx_cache_sram.o are built only if CONFIG_FSL_85XX_CACHE_SRAM is defined. The driver that qualifies and wants to make use of the CACHE SRAM's exported API (i.e. a freescale net driver) should (be able to) select this config option. Signed-off-by:
Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Martyn Welch authored
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020 processor. Signed-off-by:
Martyn Welch <martyn.welch@ge.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 15 Mar, 2012 1 commit
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Paul Gortmaker authored
The SERIAL_8250_EXTENDED option just enables access to other less regularly used options, like SERIAL_8250_SHARE_IRQ. Select it to get rid of this warning when selecting the child option living underneath it. warning: (FSL_SOC_BOOKE && SERIAL_8250_RM9K) selects SERIAL_8250_SHARE_IRQ which has unmet direct dependencies (HAS_IOMEM && SERIAL_8250_EXTENDED) Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 24 Nov, 2011 1 commit
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Paul Bolle authored
The driver for the Freescale P3060 QDS got added by commit 96cc017c ("[...] Add support for P3060QDS board"). Its Kconfig entry selects MPC8xxx_GPIO. But at the time that driver got added MPC8xxx_GPIO was already renamed to GPIO_MPC8XXX, by commit c68308dd ("gpio: move mpc8xxx/512x gpio driver to drivers/gpio"). So make this driver select GPIO_MPC8XXX. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Acked-by:
Wolfram Sang <w.sang@pengutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 03 Nov, 2011 1 commit
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Shengzhou Liu authored
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC. The P3060 Processor combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM Ethernet: - 4x1G + 4x1G/2.5G Ethernet controllers - 2xRGMII + 1xMII, three VSC8641 PHYs on board - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports up to four UARTs RapidIO: Supports two serial RapidIO ports Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 13 Oct, 2011 1 commit
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Paul Bolle authored
Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Acked-by:
Randy Dunlap <rdunlap@xenotime.net> Signed-off-by:
Jiri Kosina <jkosina@suse.cz>
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- 12 Oct, 2011 1 commit
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Anatolij Gustschin authored
Remove wrong CONFIG_ prefix in Kconfig file. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 07 Oct, 2011 1 commit
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Mingkai Hu authored
There's only p2041rdb board for official release, but the p2041 silicon on the board can be converted to p2040 silicon without XAUI and L2 cache function, then the board becomes p2040rdb board. so we use the file name p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also consistent with the board name under U-Boot. During the rename we make few other minor changes to the device tree: * Move USB phy setting into p2041si.dtsi as its SoC not board defined * Convert PCI clock-frequency to decimal to be more readable Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 22 Sep, 2011 1 commit
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Wolfram Sang authored
Move the driver to the place where it is expected to be nowadays. Also rename its CONFIG-name to match the rest and adapt the defconfigs. Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to the platforms, because this option is per-platform and not per-driver. Signed-off-by:
Wolfram Sang <w.sang@pengutronix.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
Anatolij Gustschin <agust@denx.de>
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- 08 Jul, 2011 1 commit
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Mingkai Hu authored
P2040RDB Specification: ----------------------- 2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) 128 Mbyte NOR flash single-chip memory 256 Kbit M24256 I2C EEPROM 16 Mbyte SPI memory SD connector to interface with the SD memory card dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) I2C1: Real time clock, Temperature sensor I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors UART: supports two UARTs up to 115200 bps for console USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces PCIe: - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 27 Jun, 2011 2 commits
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Prabhakar Kushwaha authored
P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory I2C Board 128x8 bit memory SD/MMC connector to interface with the SD memory card 2 SATA interface 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0 x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN Two DB-9 female connectors for Field bus interface UART DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
Add support for the ePAPR-compliant Freescale hypervisor (aka "Topaz") on the Freescale P3041DS, P4080DS, and P5020DS reference boards. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 23 Jun, 2011 1 commit
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Roy Zang authored
The P1023 processor is an e500v2 based SoC that utilizes the DPAA networking architecture. This adds basic board support for non-DPAA functionality (device tree, board file, etc). Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 14 Oct, 2010 3 commits
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Kumar Gala authored
The P5020DS is in the same family of boards as the P4080 DS and thus shares the corenet_ds code. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The P3041DS is in the same family of boards as the P4080DS and thus shares the corenet_ds code. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 04 Aug, 2010 1 commit
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Timur Tabi authored
Introduce basic support for the Freescale P1022DS reference board, based on the Freescale BSP for this board. This patch excludes the DIU, SSI, and MMC/SD drivers. Only a 36-bit DTS is provided. Update mpc86xx_smp_defconfig and mpc85xx_defconfig to support the P1022DS. This means enabling 64-bit physical address support, increasing the maximum zone order to 12 (to allow the DIU driver to allocate large chunks), and clean up the audio options to disable the deprecated OSS support. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 20 Apr, 2010 1 commit
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Anton Vorontsov authored
Currently some MPC85xx and MPC86xx boards fail to build without CONFIG_PCI: arch/powerpc/platforms/fsl_uli1575.c: In function 'quirk_final_uli5249': arch/powerpc/platforms/fsl_uli1575.c:234: error: implicit declaration of function 'pci_bus_for_each_resource' arch/powerpc/platforms/fsl_uli1575.c:234: error: expected ';' before '{' token cc1: warnings being treated as errors arch/powerpc/platforms/fsl_uli1575.c:223: warning: unused variable 'dummy' make[1]: *** [arch/powerpc/platforms/fsl_uli1575.o] Error 1 This patch fixes the issue by appending 'if PCI' condition when selecting FSL_ULI1575 Kconfig symbol. Signed-off-by:
Anton Vorontsov <avorontsov@mvista.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- 20 Nov, 2009 1 commit
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Kumar Gala authored
Add basic support for the P4080 DS reference board. None of the data path devices (ethernet, crypto, pme) are support at this time. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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