- 05 Jan, 2024 1 commit
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Arnd Bergmann authored
Merge tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v6.8 - Fix dtbs_check warnings for nand, usb, FPGA firmware, and pin-controller - Clean up of DTS for Agilex5 * tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: intel: minor whitespace cleanup around '=' arm64: dts: socfpga: agilex: drop redundant status arm64: dts: socfpga: agilex: add unit address to soc node arm64: dts: socfpga: agilex: move firmware out of soc node arm64: dts: socfpga: agilex: move FPGA region out of soc node arm64: dts: socfpga: agilex: align pin-controller name with bindings arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings arm64: dts: socfpga: stratix10: add unit address to soc node arm64: dts: socfpga: stratix10: move firmware out of soc node arm64: dts: socfpga: stratix10: move FPGA region out of soc node arm64: dts: socfpga: stratix10: align pincfg nodes with bindings arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size ARM: dts: socfpga: align NAND controller name with bindings ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size Link: https://lore.kernel.org/r/20240104001354.152410-1-dinguyen@kernel.orgSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 04 Jan, 2024 16 commits
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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Krzysztof Kozlowski authored
New device nodes are enabled by default. Signed-off-by:
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Krzysztof Kozlowski authored
The "soc" node has ranges with addresses, so it is should have unit address to fix dtc W=1 warnings like: socfpga_agilex.dtsi:152.6-674.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by:
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Krzysztof Kozlowski authored
The "soc" node is supposed to have only MMIO children, so move the firmware/svc node to top level to fix dtc W=1 warnings like: socfpga_agilex.dtsi:663.12-673.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property The node should still be instantiated by drivers/of/platform.c, just like in all other platforms. Signed-off-by:
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Krzysztof Kozlowski authored
The "soc" node is supposed to have only MMIO children, so move the FPGA region node to top level to fix dtc W=1 warnings like: socfpga_agilex.dtsi:141.20-146.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property Signed-off-by:
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Krzysztof Kozlowski authored
Use a generic node name for the pin controller node to fix: /socfpga_agilex_n6000.dtb: pinconf@ffd13100: $nodename:0: 'pinconf@ffd13100' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' Signed-off-by:
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Krzysztof Kozlowski authored
altr,dw-mshc-ciu-div and altr,dw-mshc-sdr-timing are neither documented nor used by Linux, so remove them to fix dtbs_check warnings like: socfpga_stratix10_swvp.dtb: mmc@ff808000: Unevaluated properties are not allowed ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect NAND child node name to match certain patterns: socfpga_agilex_socdk_nand.dtb: nand-controller@ffb90000: Unevaluated properties are not allowed ('flash@0' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The "soc" node has ranges with addresses, so it is should have unit address to fix dtc W=1 warnings like: socfpga_stratix10.dtsi:128.6-636.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by:
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Krzysztof Kozlowski authored
The "soc" node is supposed to have only MMIO children, so move the firmware/svc node to top level to fix dtc W=1 warnings like: socfpga_stratix10.dtsi:625.12-635.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property The node should still be instantiated by drivers/of/platform.c, just like in all other platforms. Signed-off-by:
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Krzysztof Kozlowski authored
The "soc" node is supposed to have only MMIO children, so move the FPGA region node to top level to fix dtc W=1 warnings like: socfpga_stratix10.dtsi:136.20-141.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property Signed-off-by:
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Krzysztof Kozlowski authored
pinctrl-single bindings require pin configuration node names to match certain patterns: socfpga_stratix10_socdk.dtb: pinctrl@ffd13000: 'i2c1-pmx-func', 'i2c1-pmx-func-gpio' do not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
The DWC2 USB bindings require clock-names property, to provide such to fix warnings like: socfpga_stratix10_swvp.dtb: usb@ffb40000: 'clock-names' is a required property Signed-off-by:
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Krzysztof Kozlowski authored
cdns,page-size and cdns,block-size are neither documented nor used by Linux, so remove them to fix dtbs_check warnings like: socfpga_n5x_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect NAND controller node name to match certain patterns: socfpga_arria10_socdk_nand.dtb: nand@ffb90000: $nodename:0: 'nand@ffb90000' does not match '^nand-controller(@.*)?' Signed-off-by:
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Krzysztof Kozlowski authored
cdns,page-size and cdns,block-size are neither documented nor used by Linux, so remove them to fix dtbs_check warnings like: socfpga_arria5_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected) Signed-off-by:
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- 02 Jan, 2024 6 commits
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Arnd Bergmann authored
Merge tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt RK3036 fix for emmc init issue and stdout-path for the console on rk3036 kylin. * tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Remove rockchip,default-sample-phase from rk3036.dtsi ARM: dts: rockchip: Add stdout-path for rk3036 kylin Link: https://lore.kernel.org/r/15502825.JCcGWNJJiE@diegoSigned-off-by:
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Arnd Bergmann authored
Merge tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt One new boards, the CoolPi CM5 SoM and 4B SBC. Basic node for the rk3588 display controller and a bunch of small improvements for different boards, * tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits) arm64: dts: rockchip: Fix led pinctrl of lubancat 1 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b arm64: dts: rockchip: support poweroff on the rock-5b arm64: dts: rockchip: Support poweroff on Orange Pi 5 arm64: dts: rockchip: nanopc-t6 sdmmc beautification arm64: dts: rockchip: Fix rk3588 USB power-domain clocks arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts arm64: dts: rockchip: Support poweroff on NanoPC-T6 arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB dt-bindings: arm: rockchip: Add Cool Pi CM5 arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B dt-bindings: arm: rockchip: Add Cool Pi 4B dt-bindings: vendor-prefixes: Add Cool Pi arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts arm64: dts: rockchip: Add vop on rk3588 ... Link: https://lore.kernel.org/r/3711719.VqM8IeB0Os@diegoSigned-off-by:
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Arnd Bergmann authored
Merge tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt A few more Qualcomm Arm64 DeviceTree updates for v6.8 This corrects the rate of the UTMI clock on IPQ6018 USB0. The SDHCI controller on SC7280 gains missing markings for being cache-coherent. For SC8180X a typo in assignment of PCIe refgen clocks is corrected, PCI controllers are marked cache-coherent, and the USB SS PHY interrupts are corrected to allow wakeup. Similarly USB HS PHY and SS PHY interrupts are corrected to allow wakeup on SDM670. On SM8550 the X3 cluster idle state is properly described, and the latency numbers are adjusted for all the idle states. The PM8550 regulator supplies on X1E are corrected to match the driver and binding, and the timer node is updated to avoid an unnecessary validation error. * tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: sc8180x: Fix up PCIe nodes arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550 arm64: dts: qcom: sm8550: Update idle state time requirements arm64: dts: qcom: sm8550: Separate out X3 idle state arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK arm64: dts: qcom: x1e80100: align mem timer size cells with bindings arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent arm64: dts: qcom: sc8180x: fix USB SS wakeup arm64: dts: qcom: sdm670: fix USB SS wakeup arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts Link: https://lore.kernel.org/r/20231231034108.3262678-1-andersson@kernel.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt A few more Qualcomm Arm32 DeviceTree updates fr v6.8 The recently introduced changes to the SDX55 USB controller interrupt flags prevents the USB controller from probing. These patches corrects the PDC's interrupt-cells, so that appropriate interrupt controller (which supports both-edge interrupts) can be used instead, which resolves the issue. The SDX55 PCIe PHY base address is also adjusted, from a mistake when the node recently was transitioned to the modernized DeviceTree binding. * tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY ARM: dts: qcom: sdx55: fix USB SS wakeup ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells' Link: https://lore.kernel.org/r/20231231033153.3262575-1-andersson@kernel.orgSigned-off-by:
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https://github.com/Broadcom/stblinuxArnd Bergmann authored
This pull request contains Broadcom ARM-based SoCs Device Tree changes for 6.8, please pull the following: - Rafal adds a Device Tree node for the BCM63138 high-speed UART used for Bluetooth devices * tag 'arm-soc/for-6.8/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: broadcom: Add BCM63138's high speed UART Link: https://lore.kernel.org/r/20231228085822.3656546-1-florian.fainelli@broadcom.comSigned-off-by:
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https://github.com/lyrazhang/linuxArnd Bergmann authored
ARM: sprd: DTS and bindings for v6.8-rc1 Unisoc ARM64 DTS and bindings changes are: - Fixed a few dtb_check warnings - Add bindings for a new SoC - UMS9620 - Fixed an issue on UMS512 * tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux: arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings arm64: dts: sprd: Add clock reference for pll2 on UMS512 arm64: dts: sprd: Removed unused clock references from etm nodes arm64: dts: sprd: Add support for Unisoc's UMS9620 dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 arm64: dts: sprd: fix the cpu node for UMS512 Link: https://lore.kernel.org/r/20231228084958.1439115-1-chunyan.zhang@unisoc.comSigned-off-by:
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- 29 Dec, 2023 6 commits
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Andy Yan authored
According to the schematics, the gpio control sys_led is GPIO0_C5. Fixes: 8d94da58 ("arm64: dts: rockchip: Add EmbedFire LubanCat 1") Reported-by:
Zhang Ning <zhangn1985@outlook.com> Closes: https://lore.kernel.org/linux-rockchip/OS0P286MB06412D049D8BF7B063D41350CD95A@OS0P286MB0641.JPNP286.PROD.OUTLOOK.COM/T/#uSigned-off-by:
Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20231225005055.3102743-1-andyshrk@163.comSigned-off-by:
Heiko Stuebner <heiko@sntech.de>
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John Clark authored
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by:
John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20231225223226.17690-1-inindev@gmail.comSigned-off-by:
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John Clark authored
Both rk806_dvs1_null and rk806_dvs2_null duplicate gpio_pwrctrl2 and gpio_pwrctrl1 is not set. This patch sets gpio_pwrctrl1. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20231225222859.17153-2-inindev@gmail.comSigned-off-by:
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John Clark authored
Allow the rock-5b to poweroff its pmic. When issuing a "shutdown -h now" on the rock-5b it reboots instead. Defining 'system-power-controller' allows the rk806 to power down. Commit c699fbfd ("arm64: dts: rockchip: Support poweroff on NanoPC-T6") similarly resolves this issue for the nanopc-t6. Signed-off-by:
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Jimmy Hon authored
The RK806 on the Orange Pi 5 can be used to power on/off the whole board. Mark it as the system power controller. Signed-off-by:
Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20231227203211.1047-1-honyuenkwun@gmail.comSigned-off-by:
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John Clark authored
drop max-frequency = <200000000> as it is already defined in rk3588s.dtsi order no-sdio & no-mmc properties while we are here Signed-off-by:
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- 28 Dec, 2023 6 commits
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Chunyan Zhang authored
Fix below dtbs_check warning: idle-states: 'core-pd' does not match any of the regexes: '^(cpu|cluster)-', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20231221092824.1169453-3-chunyan.zhang@unisoc.comSigned-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com>
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Chunyan Zhang authored
Fix below dtbs_check warning: 'clocks' is a dependency of 'clock-names' Link: https://lore.kernel.org/r/20231221092824.1169453-2-chunyan.zhang@unisoc.comSigned-off-by:
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Chunyan Zhang authored
Remove these unused clock references to fix dtbs_check warnings: etm@3f740000: clocks: [[11], [35, 34], [36, 8]] is too long etm@3f740000: clock-names:1: 'atclk' was expected etm@3f740000: clock-names: ['apb_pclk', 'clk_cs', 'cs_src'] is too long Link: https://lore.kernel.org/r/20231221092824.1169453-1-chunyan.zhang@unisoc.comSigned-off-by:
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Chunyan Zhang authored
Add basic support for Unisoc's UMS9620, with this patch, the board ums9620-2h10 can run into console. Link: https://lore.kernel.org/r/20231218100234.1102916-4-chunyan.zhang@unisoc.comSigned-off-by:
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Chunyan Zhang authored
Added bindings for Unisoc's UMS9620-2H10 board and UMS9620 SoC. Acked-by:
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Cixi Geng authored
The UMS512 Socs have 8 cores contains 6 a55 and 2 a75. modify the cpu nodes to correct information. Fixes: 2b488183 ("arm64: dts: sprd: Add support for Unisoc's UMS512") Cc: stable@vger.kernel.org Signed-off-by:
Cixi Geng <cixi.geng1@unisoc.com> Link: https://lore.kernel.org/r/20230711162346.5978-1-cixi.geng@linux.devSigned-off-by:
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- 24 Dec, 2023 5 commits
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Sam Edwards authored
The QoS blocks saved/restored when toggling the PD_USB power domain are clocked by ACLK_USB. Attempting to access these memory regions without that clock running will result in an indefinite CPU stall. The PD_USB node wasn't specifying this clock dependency, resulting in hangs when trying to toggle the power domain (either on or off), unless we get "lucky" and have ACLK_USB running for another reason at the time. This "luck" can result from the bootloader leaving USB powered/clocked, and if no built-in driver wants USB, Linux will disable the unused PD+CLK on boot when {pd,clk}_ignore_unused aren't given. This can also be unlucky because the two cleanup tasks run in parallel and race: if the CLK is disabled first, the PD deactivation stalls the boot. In any case, the PD cannot then be reenabled (if e.g. the driver loads later) once the clock has been stopped. Fix this by specifying a dependency on ACLK_USB, instead of only ACLK_USB_ROOT. The child-parent relationship means the former implies the latter anyway. Fixes: c9211fa2 ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Cc: stable@vger.kernel.org Signed-off-by:Sam Edwards <CFSworks@gmail.com> Link: https://lore.kernel.org/r/20231216021019.1543811-1-CFSworks@gmail.com [changed to only include the missing clock, not dropping the root-clocks] Signed-off-by:
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Tianling Shen authored
The default strength is not enough to provide stable connection under 3.3v LDO voltage. Fixes: 387b3bba ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS") Cc: stable@vger.kernel.org # 6.6+ Signed-off-by:
Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.comSigned-off-by:
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Hugh Cole-Baker authored
The RK806 on the NanoPC-T6 can be used to power on/off the whole board. Mark it as the system power controller. Signed-off-by:
Hugh Cole-Baker <sigmaris@gmail.com> Link: https://lore.kernel.org/r/20231216212134.23314-1-sigmaris@gmail.comSigned-off-by:
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Trevor Woerner authored
Perform the following cleanups on a previous patch: - indent lines after "gpio-line-names" - fix D0-D8 -> D0-D7 - sort phandle references Fixes: c45de75d ("arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s") Signed-off-by:
Trevor Woerner <twoerner@gmail.com> Link: https://lore.kernel.org/r/20231219173814.1569-1-twoerner@gmail.comSigned-off-by:
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Andy Yan authored
Cool Pi CM5 EVB works as a mother board connect with CM5. CM5 Specification: - Rockchip RK3588 - LPDDR4 2/4/8/16 GB - TF scard slot - eMMC 8/32/64/128 GB module - Gigabit ethernet x 1 with PHY YT8531 - Gigabit ethernet x 1 drived by PCIE with YT6801S CM5 EVB Specification: - HDMI Type A out x 2 - HDMI Type D in x 1 - USB 2.0 Host x 2 - USB 3.0 OTG x 1 - USB 3.0 Host x 1 - PCIE M.2 E Key for Wireless connection - PCIE M.2 M Key for NVME connection - 40 pin header Signed-off-by:
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