- 28 Jan, 2024 11 commits
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Luca Weiss authored
When the properties num-channels & qcom,num-ees are not specified, the driver tries to read the values from registers, but this read fails and resets the device if the interconnect from the qcom,qce node is not already active when that happens. Add the static properties to not touch any registers during probe, the rest of the time when the BAM is used by QCE then the interconnect will be active already. Fixes: d488f903 ("arm64: dts: qcom: sc7280: add QCrypto nodes") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231229-sc7280-cryptobam-fixup-v1-1-bd8f68589b80@fairphone.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Suraj Jaiswal authored
Add changes to support safety IRQ handling support for ethernet. Signed-off-by:
Suraj Jaiswal <quic_jsuraj@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240110111649.2256450-3-quic_jsuraj@quicinc.comSigned-off-by:
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Stephan Gerhold authored
Add "regulator" to the node names of the fixed regulators, and drop the "_rear" part of the camera node name since it is not part of the class of the device (which is simply "camera"). Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230922-apq8016-sbc-camera-dtso-v1-1-ce9451895ca1@gerhold.netSigned-off-by:
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Krzysztof Kozlowski authored
Other PCIe nodes in SM8250 and SM8350 have one interrupt name per line, so adjust PCIe0 to match the style. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Reviewed-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by:
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Konrad Dybcio authored
The serial ports did not have their interconnect paths specified when they were first introduced. Fix that. Fixes: 5188049c ("arm64: dts: qcom: Add base SM8450 DTSI") Fixes: f5837418 ("arm64: dts: qcom: sm8450: add uart20 node") Reported-by:
Georgi Djakov <djakov@kernel.org> Signed-off-by:
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- 27 Jan, 2024 23 commits
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Raymond Hackley authored
Document the new following device tree bindings used in their device trees: - samsung,fortuna3g - samsung,gprimeltecan - samsung,grandprimelte - samsung,rossa Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240120095715.13689-2-raymondhackley@protonmail.comSigned-off-by:
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Krzysztof Kozlowski authored
Due to lack of documentation the AMIC4 and AMIC5 analogue microphones were never actually working, so the audio routing for them was added hoping it is correct. It turned out not correct - their routing should point to SWR_INPUT0 (so audio mixer TX SMIC MUX0 = SWR_MIC0) and SWR_INPUT1 (so audio mixer TX SMIC MUX0 = SWR_MIC1), respectively. With proper mixer settings and fixed LPASS TX macr codec TX SMIC MUXn widgets, this makes all microphones working on HDK8450. Cc: stable@vger.kernel.org Fixes: f20cf2bc ("arm64: dts: qcom: sm8450-hdk: add other analogue microphones") Signed-off-by:
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Krzysztof Kozlowski authored
The PCIe nodes should get the ref clock, according to information from Qualcomm. Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, unify the naming scheme of the thermal zones across the tree while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Also, update the trip point label to be more telling, while at it. Signed-off-by:
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Konrad Dybcio authored
If the GPU ever reaches this temperature, the "critical" signal shuold definitely be propagated. Fix the wrong type. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
In order to allow for throttling the GPU, hook up the cooling device to the respective thermal zones. Signed-off-by:
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Konrad Dybcio authored
The RPMh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being committed. Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Previous Qualcomm SoCs over the past couple years have used the Arm DSU architecture, which basically unified the meaning of the "cluster" and "system". This is however clearly not the case on X1E, as can be seen by three separate cluster power domains. Add the lacking system-level power domain. For now it's going to be always-on, as no system-wide idle states are defined at the moment. Signed-off-by:
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Krishna Kurapati authored
For qcs404 and ipq5332, certain interrupts are missing in DT. Add them to ensure they are in accordance to bindings. The interrupts added enable remote wakeup functionality for these SoCs. Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Link: https://lore.kernel.org/r/20240125185921.5062-5-quic_kriskura@quicinc.comSigned-off-by:
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Krishna Kurapati authored
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Also modify order of interrupts in accordance to bindings update. Modifying the order of these interrupts is harmless as the driver tries to get these interrupts from DT by name and not by index. Signed-off-by:
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Krishna Kurapati authored
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Also modify order of interrupts in accordance to bindings update. Signed-off-by:
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Krishna Kurapati authored
On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq to qusb2_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. Add missing ss_phy_irq on some targets which allows for remote wakeup to work on a Super Speed link. Also modify order of interrupts in accordance to bindings update. Since driver looks up for interrupts by name and not by index, it is safe to modify order of these interrupts in the DT. Signed-off-by:
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Neil Armstrong authored
The SM8550-HDK is an embedded development platforms for the Snapdragon 8 Gen 2 SoC aka SM8550, with the following features: - Qualcomm SM8550 SoC - 16GiB On-board LPDDR5 - On-board WiFi 7 + Bluetooth 5.3/BLE - On-board UFS4.0 - M.2 Key B+M Gen3x2 PCIe Slot - HDMI Output - USB-C Connector with DP Almode & Audio Accessory mode - Micro-SDCard Slot - Audio Jack with Playback and Microphone - 2 On-board Analog microphones - 2 On-board Speakers - 96Boards Compatible Low-Speed and High-Speed connectors [1] - For Camera, Sensors and external Display cards - Compatible with the Linaro Debug board [2] - SIM Slot for Modem - Debug connectors - 6x On-Board LEDs Product Page: [3] [1] https://www.96boards.org/specifications/ [2] https://git.codelinaro.org/linaro/qcomlt/debugboard [3] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240125-topic-sm8550-upstream-hdk8550-v3-2-73bb5ef11cf8@linaro.orgSigned-off-by:
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Neil Armstrong authored
Document the Qualcomm SM8550 based HDK (Hardware Development Kit) embedded development platform designed by Qualcomm and sold by Lantronix. [1] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/Reviewed-by:
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- 23 Jan, 2024 6 commits
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Konrad Dybcio authored
Add the sleep stats node to enable peeking at the power collapse reports coming from the AOSS. Signed-off-by:
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Konrad Dybcio authored
The AOSS_QMP region is overallocated, bleeding into space that's supposed to be used by other peripherals. Fix it. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
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Konrad Dybcio authored
To guarantee the required resources are enabled, describe the interconnect path between the MDSS and the CPU. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by:
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Konrad Dybcio authored
To ensure the PLLs are getting enough power, cast a vote with DISPCC so that MMCX is at least at LOW_SVS. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by:
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Konrad Dybcio authored
There's an OPP table to handle this, drop the permanent vote. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by:
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Konrad Dybcio authored
The (e)DP PHYs are powered by the MX line, not through the MDSS GDSC. Fix that up. Fixes: 494dec9b ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by:
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