This adds the cpus node to the Integrator/CP device tree so
that we have a proper placeholder to put in the DT-defined
operating points for the generic DT/OPP cpufreq driver,
along with two working operating points.

I have only put in 48 and 50 MHz because going to e.g. 36
MHz hangs the system when CLCD graphics are active.
Presumably the memory bus gets to slow to feed the display
and the systems hangs for this reason. The ideal solution
would be for the display controller to put constraints on
the memory bus frequency, but that need to be a separate
longer-term project.

We define a CPU node since this is required for cpufreq-dt,
however we do not define any compatible string for the CPU
since this architecture has pluggable CPU modules and we
do not know which one will be used. If necessary, the CPU
compatible can be filled in by the boot loader, but for
just cpufreq-dt it is not required.

Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>

- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701

* tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek:
  arm: dts: mt2701: Use real clock for UARTs
  arm: dts: mt2701: Add clock controller device nodes
  arm64: dts: mt8173: Fix auxadc node
  soc: mediatek: Add MT2701 power dt-bindings
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

32bit devicetree changes for Rockchip including removal of skeleton.dtsi
inclusion, missing unit names for memory nodes, various frequency
optimizations allowing for better performance on rk3066, the usage of
pin constants to bridge between the two numbering schemes used (gpio
controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
and UHS/HS modes for the mmc controllers on the popmetal board.

Two new boards, the PX3-based evaluation board, with the PX3 being an
industrial variant of the rk3188 soc and the Rikomagic MK808 board
based around the rk3066 are also added.

* tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
  ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
  ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a
  ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288
  include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl
  ARM: dts: rockchip: Add rk3066 MK808 board
  devicetree: Add vendor prefix for Rikomagic
  ARM: dts: rockchip: initialize rk3066 PLL clock rate
  clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
  ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal
  ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board
  ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb
  ARM: dts: rockchip: update compatible strings for Rockchip efuse
  ARM: dts: rockchip: add rockchip PX3 Evaluation board
  ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards
  ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards
  ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards
  ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards
  ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi
  ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi
  ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS update for v4.10, part 2
- Add specific compatible strings for variants of Cyclone5 boards
- Add QSPI node on Arria10
- Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit
- Add NAND controller node on Cyclone5

* tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: socfpga: add nand controller nodes
  ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
  ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
  ARM: dts: socfpga: Enable QSPI in Arria10 devkit
  ARM: dts: socfpga: Add QSPI node for the Arria10
  ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
  ARM: dts: socfpga: add specific compatible strings for boards
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'sti-dt-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/dt

STi dts update:

Change sound card name for B2120
Enable sound card for B2260
Remove stih415-clks.h
Identify critical clocks for STiH407
Fix typo in stih407-pinctrl.dtsi

* tag 'sti-dt-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
  ARM: dts: STiHxxx-b2120: change sound card name
  ARM: dts: STiH410-B2260: enable sound card
  ARM: dts: remove stih415-clks.h
  ARM: dts: stih407-clocks: Identify critical clocks
  ARM: dts: STiH407: DT fix s/interrupts-names/interrupt-names/
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'samsung-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DeviceTree update for v4.10:
1. Add TOPEET itop core and Elite boards, based on Exynos4412.
2. Remove the Exynos4415 DTSI. We did not have any mainlined boards
   using it. I am also not aware of any popular out-of-tree boards using it.
3. Add Snoop Control Unit node for Exynos4.
4. Minor cleanups.

* tag 'samsung-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Add SCU device node to exynos4.dtsi
  ARM: dts: exynos: Remove exynos4415.dtsi
  ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards
  ARM: dts: exynos: Add TOPEET itop elite based board
  ARM: dts: exynos: Add TOPEET itop core board SCP package version
  ARM: dts: exynos: Add entries for sound support on Odroid-XU board
  ARM: dts: exynos: Remove "simple-bus" compatible from fimc-is node
Signed-off-by: Olof Johansson <olof@lixom.net>

NXP LPC32xx ARM SoC device tree updates for v4.10

This includes a single functional change:
* set default parent clock for PWM1 & PWM2.

* tag 'lpc32xx-dt-v4.10' of https://github.com/sylemieux/linux-lpc32xx:
  ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

UniPhier ARM SoC DT updates for v4.10

- Add OPP tables to support generic cpufreq driver
- Use more clocks/resets properties
- Misc fixes and cleanups

* tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: dts: uniphier: make compatible of syscon nodes SoC-specific
  ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
  ARM: dts: uniphier: remove redundant serial fifo-size properties
  ARM: dts: uniphier: make 32bit SoC DTSI linear
  ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
  ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC
  ARM: dts: uniphier: increase register region size of sysctrl node
Signed-off-by: Olof Johansson <olof@lixom.net>

Linux 4.9-rc3

* tag 'v4.9-rc3': (292 commits)
  Linux 4.9-rc3
  x86/smpboot: Init apic mapping before usage
  ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
  ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
  ACPICA: Dispatcher: Fix order issue of method termination
  ARC: module: print pretty section names
  ARC: module: elide loop to save reference to .eh_frame
  ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
  ARC: build: retire old toggles
  ARC: boot log: refactor cpu name/release printing
  ARC: boot log: remove awkward space comma from MMU line
  ARC: boot log: don't assume SWAPE instruction support
  ARC: boot log: refactor printing abt features not captured in BCRs
  ARCv2: boot log: print IOC exists as well as enabled status
  ubifs: Fix regression in ubifs_readdir()
  ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
  MAINTAINERS: Add entry for genwqe driver
  VMCI: Doorbell create and destroy fixes
  GenWQE: Fix bad page access during abort of resource allocation
  vme: vme_get_size potentially returning incorrect value on failure
  ...

Merge tag 'stm32-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt

STM32 DT updates for v4.10, round 1.

Highlights:
----------
 - Add LSI and LSE clocks support for STM32F429
 - Add GPIO IRQ support for STM32F429
 - Declare push button as GPIO keys on STM32F429 boards
 - Add DMA supports on USART1 & USART3 on STM32F429
 - Add Ethernet fixes

* tag 'stm32-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32f429: add LSI and LSE clocks
  ARM: dts: stm32f429: remove Ethernet wake on Lan support
  ARM: dts: stm32f429: Fix Ethernet node on Eval Board
  ARM: dts: stm32f429: Align Ethernet node with new bindings properties
  ARM: DT: stm32: move dma translation to board files
  ARM: DT: STM32: add dma for usart3 on F429
  ARM: DT: STM32: add dma for usart1 on F429
  ARM: dts: Declare push button as GPIO key on stm32f429 boards
  ARM: dts: Add GPIO irq support to STM32F429
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.10

Clean-Ups and Corrections:
* Removed Z clock from r8a7794 SoC; it is not present in hardware
* Use generic pinctrl properties in SDHI nodes in gose board
* Correct W=1 dtc warnings on r8a7794 SoC
* Correct DU reg property on r8a7779 SoC
* Correct SCIFB reg properties to cover all registers

Enhancements:
* Configure pinmuxing for the DU0 input clock on the Marzen board
* Enable VIN 0 - 2 on r8a7793 SoC
* Enable HDMI input on Koelsch and Lager boards
* Enable SDHI1 on rskrza1 board
* Add MMCIF nodes to r7s72100 SoC
* Add MSIOF clocks to r8a7792 SoC
* Enable UHS for SDHI 0 & 1 on koelsch and alt boards

* tag 'renesas-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (29 commits)
  ARM: dts: r8a7794: remove Z clock
  ARM: dts: r8a7779: marzen: Configure pinmuxing for the DU0 input clock
  ARM: dts: sh73a0: Remove skeleton.dtsi inclusion
  ARM: dts: r8a7740: Remove skeleton.dtsi inclusion
  ARM: dts: r8a7779: Remove skeleton.dtsi inclusion
  ARM: dts: r8a7778: Remove skeleton.dtsi inclusion
  ARM: dts: emev2: Remove skeleton.dtsi inclusion
  ARM: dts: r8a7779: Fix DU reg property
  ARM: dts: r8a7793: Enable VIN0-VIN2
  ARM: dts: koelsch: add HDMI input
  ARM: dts: lager: Add entries for VIN HDMI input support
  ARM: dts: rskrza1: add sdhi1 DT support
  ARM: dts: r7s72100: add sdhi to device tree
  ARM: dts: r8a7794: Fix W=1 dtc warnings
  ARM: dts: gose: use generic pinctrl properties in SDHI nodes
  ARM: dts: r7s72100: add sdhi clock to device tree
  ARM: dts: r7s72100: add mmcif to device tree
  ARM: dts: r8a7792: add MSIOF support
  ARM: dts: r8a7792: add MSIOF clocks
  ARM: dts: wheat: add DU support
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg and apmixedsys. This patch also add two oscillators that
provide clocks for MT2701.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Rename sound card to differentiate B2120 and B2260 sound card.
Sound card name is used by alsa-lib to load associated card
configuration file.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>

Enable simple card with HDMI device.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>

Since v4.8, STiH415/416 clock support has
been removed [1], these platform doesn't boot.
We can remove DTS files related to these socs.

[1] https://patchwork.kernel.org/patch/9157571/Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Lots of platforms contain clocks which if turned off would prove fatal.
The only way to recover is to restart the board(s).  This driver takes
references to clocks which are required to be always-on.  The Common
Clk Framework will then take references to them.  This way they will
not be turned off during the clk_disabled_unused() procedure.

In this patch we are identifying clocks, which if gated would render
the STiH407 development board unserviceable.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>

Add the denali nand controller to the socfpga dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

In drivers/mmc/core/host.c, there is "max-frequency" property.
It should be same behavior. So use the "max-frequency" instead of
"clock-freq-min-max".
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: Use n25q00 for the compatible entry for the flash part and
    tested on SoCKit
v2: Remove partition entries for the SoCKIT

Enable the QSPI node and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the QSPI device node for Arria10 SOC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Enable the qspi controller on the devkit and add the flash chip.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add a more specific board compatible entry for all of the SOCFPGA
Cyclone 5 based boards.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: Be a bit more specific with the c5 dk and sockit, use
    "altr,socfpga-cyclone5-socdk" and "terasic,socfpga-cyclone5-sockit"
v2: remove extra space and add a comma between compatible entries

Merge tag 'davinci-for-v4.10/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt

DaVinci device-tree source additions for
LCD, SPI and cfgchip syscon.

* tag 'davinci-for-v4.10/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: dts: da850: Add cfgchip syscon node
  ARM: dts: da850: Add DMA to SPI0
  ARM: dts: da850: add a node for the LCD controller
Signed-off-by: Olof Johansson <olof@lixom.net>

Currently driver leaves sdmmc frequency at its default.
So lets set this to 50MHz.
This gives us performance boost in mmc transfers.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Exynos4 like other Cortex-A9 SoC's has a Snoop Control Unit(SCU)
and its SFR are used during SMP boot and S2R. Add SCU node to the device tree.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well.  This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Now, the clock/reset controller driver is available for this SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

These are the default of the optional property.  No need to describe
them explicitly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

I notice some mistakes in the SoC DTSI; wrong interrupts properties
of timer nodes, mismatch between the node name and the compatible
for sdctrl block.  Given those problems fixed, the common parts
among SoCs are less than I had first expected.  The more and more
property overrides are making the SoC DTSI unreadable.

Stretch out the SoC DTSI files and fix the following:

 - Fix the 3rd cell of the interrupts property of the timer nodes
   for Pro4, Pro5, PXs2

 - Fix the node name mioctrl to sdctrl for Pro5, PXs2

 - Fix the second region of l2 node for PXs2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

The System Control node has 0x10000 byte of registers.  The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable these clocks.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

This patch removes WoL (Wake on Lan) support as it is not yet
fully supported and tested.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

"phy-handle" entry is mandatory when mdio subnode is used in
Ethernet node.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

This patch aligns clocks names and node reference according to new
stm32-dwmac glue binding. It also renames Ethernet pinctrl phandle
(indeed there is no need to add 0 as Ethernet instance as there is only
one IP in SOC).
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>

stm32f469-disco and stm32f429-eval boards use SDRAM start address remapping
(to @0) to boost performances. A DMA translation through "dma-ranges"
property was needed for other masters than the M4 CPU.
stm32f429-disco doesn't use remapping so doesn't need this DMA translation.
This patches moves this DMA translation definition from stm32f429 soc file
to board files.
Tested-by: Bruno Herrera <bruherrera@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>