- 20 Sep, 2022 15 commits
-
-
Johan Hovold authored
The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220907110728.19092-16-johan+linaro@kernel.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
-
Johan Hovold authored
The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by:
-
Johan Hovold authored
Drop the secondary register initialisation tables which aren't used by this driver. Signed-off-by:
-
Johan Hovold authored
The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by:
-
Johan Hovold authored
Drivers should in general not log anything during unless there are errors. Drop the pointless registration info message from the QMP drivers. Signed-off-by:
-
Johan Hovold authored
Drop defines and enums that are unused since the QMP driver split. Signed-off-by:
-
Johan Hovold authored
Make sure to disable runtime PM also on driver unbind. Fixes: ac0d2399 ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by:
-
Johan Hovold authored
Drop defines and enums that are unused since the QMP driver split. Signed-off-by:
-
Johan Hovold authored
Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d2399 ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by:
-
Johan Hovold authored
Drop defines and enums that are unused since the QMP driver split. Signed-off-by:
-
Johan Hovold authored
Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d2399 ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by:
-
Johan Hovold authored
Drop defines and enums that are unused since the QMP driver split. Signed-off-by:
-
Johan Hovold authored
Drop the unused and incomplete runtime PM implementation, which was only used by USB PHYs before splitting the QMP driver. Note that the runtime PM was never disabled (and state restored) on driver unbind. This effectively reverts commit ac0d2399 ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by:
-
Johan Hovold authored
Drop defines and enums that are unused since the QMP driver split. Signed-off-by:
-
Johan Hovold authored
Make sure to disable runtime PM also on driver unbind. Fixes: ac0d2399 ("phy: qcom-qmp: Add support for runtime PM"). Signed-off-by:
-
- 13 Sep, 2022 14 commits
-
-
Siddharth Vadapalli authored
Each of the CPSW5G ports in J7200 support additional modes like QSGMII. Add a new compatible for J7200 to support the additional modes. In TI's J7200, each of the CPSW5G ethernet interfaces can act as a QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. To indicate the interface which will serve as the main QSGMII interface, add a property "ti,qsgmii-main-ports", whose value indicates the port number of the interface which shall serve as the main QSGMII interface. The rest of the interfaces are then assigned QSGMII-SUB mode by default. The property "ti,qsgmii-main-ports" is used to configure the CTRLMMR_ENETx_CTRL register. Depending on the device, it is possible for more than one QSGMII main port to exist. Thus, the property "ti,qsgmii-main-ports" is defined as an array of values in order to reuse the property for other devices. Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20220912085650.83263-4-s-vadapalli@ti.comSigned-off-by:
-
Siddharth Vadapalli authored
TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII that are not supported on earlier SoCs. Add a compatible for it. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220912085650.83263-3-s-vadapalli@ti.comSigned-off-by:
-
Siddharth Vadapalli authored
Change node name in example from "phy-gmii-sel" to "phy", following the device-tree convention of using generic node names. Signed-off-by:
-
Johan Jonker authored
Add rockchip,rk3128-usb2phy compatible string. Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/d477a077-a68f-e752-5192-807db80a9e68@gmail.comSigned-off-by:
-
Colin Foster authored
Convert the phy-ocelot-serdes device tree binding to the new YAML format. Additionally, add the file to MAINTAINERS since the original file didn't exist. Signed-off-by:
Colin Foster <colin.foster@in-advantage.com> Reviewed-by:
-
Wei Yongjun authored
In case of error, the function nvmem_cell_read() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 99d9ccd9 ("phy: usb: Add USB2.0 phy driver for Sunplus SP7021") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20220909094709.1790970-1-weiyongjun@huaweicloud.comSigned-off-by:
-
Krishna Kurapati authored
Add support for overriding electrical signal tuning parameters for SNPS HS Phy. Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662480933-12326-3-git-send-email-quic_kriskura@quicinc.comSigned-off-by:
-
Sandeep Maheswaram authored
Add device tree bindings for SNPS phy tuning parameters. Signed-off-by:
Sandeep Maheswaram <quic_c_sanm@quicinc.com> Signed-off-by:
-
Johan Hovold authored
Drop the obsolete and misleading dual-lane comments which gave the impression that only combo PHYs have a second lane. Signed-off-by:
-
Johan Hovold authored
The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by:
-
Dmitry Baryshkov authored
Drop unused if (table) conditions, since the function qcom_qmp_phy_pcie_configure_lane() has this check anyway. Signed-off-by:
-
Johan Hovold authored
At least the "qcom,sc8280xp-qmp-usb43dp-phy" binding requires a power domain to be specified. Fixes: aa27597e ("dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys") Signed-off-by:
-
Johan Hovold authored
At least the "sc8280xp-qmp-usb3-uni-phy" binding requires a power domain to be specified. Fixes: aa27597e ("dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys") Signed-off-by:
-
Horatiu Vultur authored
The serdes driver contains also a mux to decide which interface type to use. Currently the driver supports GMII/SGMII/QSGMII and partially RGMII. As it doesn't support all the other RGMII interfaces like RGMII_TXID/RXID/ID and it could run only at 1G. Therefore extend this for all the other speeds(10/100) and also allow the other interfaces. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220901121455.245103-1-horatiu.vultur@microchip.comSigned-off-by:
-
- 04 Sep, 2022 4 commits
-
-
Peter Geis authored
The otg sync state patch reuses the ret variable, but fails to set it to zero after use. This leads to a situation when the otg port is in peripheral mode where the otg phy aborts halfway through setup. It also fails to account for a failure to register the extcon notifier. Fix this by using our own variable and skipping otg sync in case of failure. Fixes: 8dc60f8d ("phy: rockchip-inno-usb2: Sync initial otg state") Reported-by:
Markus Reichl <m.reichl@fivetechno.de> Reported-by:
Michael Riesch <michael.riesch@wolfvision.net> Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Tested-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220902184543.1234835-1-pgwipeout@gmail.comSigned-off-by:
-
Heiner Kallweit authored
Simplify the code by using devm_clk_get_enabled(). Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/9308a2a3-e828-bd9d-ab83-a68376aab5c3@gmail.comSigned-off-by:
-
Shawn Lin authored
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add data-lanes property for splitting pcie-lanes across controllers. The data-lanes is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Suggested-by:
Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.deSigned-off-by:
-
Frank Wunderlich authored
Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by:
-
- 02 Sep, 2022 6 commits
-
-
Michael Riesch authored
This adds support for variant found in Rockchip RK356x SoCs. Note that only the basic operating mode is supported, in which all four CSI lines are controlled by the Rockchip ISP. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220720091527.1270365-3-michael.riesch@wolfvision.netSigned-off-by:
-
Michael Riesch authored
The driver for the Innosilicon MIPI CSI DPHY is compatible with the variant in the Rockchip RK356x SoCs. Add the compatible string to the binding. Signed-off-by:
-
Krzysztof Kozlowski authored
Emails to Pratyush Yadav bounce ("550 Invalid recipient"), so update to match one in commit 92714596 ("MAINTAINERS: Use my kernel.org email"). Signed-off-by:Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20220816132131.75591-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
-
Bjorn Andersson authored
When the platform was booted with the involved clocks enabled the clk_set_rate() of the link and pixel clocks will perculate to the children, which will fail to update because the PHY driver has just shut down the PLL. Postpone the clock rate updates until the PLL is back online to avoid reconfiguring the clocks while the PLL is not ticking. Fixes: f199223c ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220805154432.546740-1-bjorn.andersson@linaro.orgSigned-off-by:
-
Vincent Shih authored
Add bindings doc for Sunplus USB2 PHY driver Reviewed-by:
Vincent Shih <vincent.sunplus@gmail.com> Link: https://lore.kernel.org/r/1658717052-26142-3-git-send-email-vincent.sunplus@gmail.comSigned-off-by:
-
Vincent Shih authored
Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by:
-
- 30 Aug, 2022 1 commit
-
-
Johan Hovold authored
The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by:
-
