- 08 Mar, 2022 5 commits
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https://github.com/intel/gvt-linuxJoonas Lahtinen authored
- add the missing attribute "name" in VFIO mdev hierarchy. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: "Wang, Zhi A" <zhi.a.wang@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e38f0725-6b22-8e49-b8f6-41986b0ece06@intel.com
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Ville Syrjälä authored
The current implementation of the async flip wm0/ddb optimization does not work at all. The biggest problem is that we skip the whole intel_pipe_update_{start,end}() dance and thus never actually complete the commit that is trying to do the wm/ddb change. To fix this we need to move the do_async_flip flag to the crtc state since we handle commits per-pipe, not per-plane. Also since all planes can now be included in the first/last "async flip" (which gets converted to a sync flip to do the wm/ddb mangling) we need to be more careful when checking if the plane state is async flip comptatible. Only planes doing the async flip should be checked and other planes are perfectly fine not adhereing to any async flip related limitations. However for subsequent commits which are actually going do the async flip in hardware we want to make sure no other planes are in the state. That should never happen assuming we did our job correctly, so we'll toss in a WARN to make sure we catch any bugs here. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220214105532.13049-4-ville.syrjala@linux.intel.comReviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (cherry picked from commit 2e084371) Signed-off-by:
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Ville Syrjälä authored
Since the async flip state check is done very late and thus it can see potentially all the planes in the state (due to the wm/ddb optimization) we need to move the "can the requested plane do async flips at all?" check much earlier. For this purpose we introduce intel_async_flip_check_uapi() that gets called early during the atomic check. And for good measure we'll throw in a couple of basic checks: - is the crtc active? - was a modeset flagged? - is+was the plane enabled? Though atm all of those should be guaranteed by the fact that the async flip can only be requested through the legacy page flip ioctl. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:
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Ville Syrjälä authored
data_rate==0 no longer means a plane is disabled, it could also mean we want to use the minimum ddb allocation for it. Hence we can't bail out early during ddb allocation or else we'll simply forget to allocate any ddb for such planes. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: 6a4d8cc6 ("drm/i915: Don't allocate extra ddb during async flip for DG2") Signed-off-by:
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Ville Syrjälä authored
bigjoiner_pipes==0 leads bigjoiner_master_pipe() to do BIT(ffs(0)-1) which is undefined behaviour. The code should actually still work fine since the only place we provoke that is intel_crtc_bigjoiner_slave_pipes() and it'll bitwise AND the result with 0, so doesn't really matter what we get out of bigjoiner_master_pipe(). But best not provoke undefined behaviour anyway. Reported-by:
kernel test robot <oliver.sang@intel.com> Fixes: a6e7a006 ("drm/i915: Change bigjoiner state tracking to use the pipe bitmask") Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> (cherry picked from commit cccc71b5) Signed-off-by:
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- 07 Mar, 2022 1 commit
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Zhi Wang authored
The mdev attribute "name" is required by some middle software, e.g. KubeVirt, an open source SW that manages VM on Kubernetes cluster uses the mdev sysfs directory/file structure to discover mediated device in nodes in the cluster. v2: - Fix the missing defination in gvt_type_attrs. (Zhenyu) Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Hui Chun Ong <hui.chun.ong@intel.com> Cc: Terrence Xu <terrence.xu@intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by:
Zhi Wang <zhi.wang.linux@gmail.com> Link: http://patchwork.freedesktop.org/patch/msgid/20220222150532.9090-1-zhi.a.wang@intel.comReviewed-by:
Zhenyu Wang <zhenyuw@linux.intel.com>
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- 04 Mar, 2022 5 commits
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
We're experimenting a bit with the process this time, with Dmitry collecting display patches and merging them into msm-next with me handling the gpu/etc side of things. Summary of interesting new bits and pieces * dpu + dp support for sc8180x * dp support for sm8350 * dpu + dsi support for qcm2290 * 10nm dsi phy tuning support * bridge support for dp encoder * gpu support for additional 7c3 SKUs * assorted cleanups and fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGu=Jdrw6DqYOYPTMks7=zatrsvdR=o6DpjqZ=TQQhFZuw@mail.gmail.com
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2022-03-03' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Cross-subsystem Changes: - drm-next backmerge for buddy allocator changes Driver Changes: - Skip i915_perf init for DG2 as it is not yet enabled (Ram) - Add missing workarounds for DG2 (Clint) - Add 64K page/align support for platforms like DG2 that require it (Matt A, Ram, Bob) - Add accelerated migration support for DG2 (Matt A) - Add flat CCS support for XeHP SDV (Abdiel, Ram) - Add Compute Command Streamer (CCS) engine support for XeHP SDV (Michel, Daniele, Aravind, Matt R) - Don't support parallel submission on compute / render (Matt B, Matt R) - Disable i915 build on PREEMPT_RT until RT behaviour fixed (Sebastian) - Remove RPS interrupt support for TGL+ (Jose) - Fix S/R with PM_EARLY for non-GTT mappable objects on DG2 (Matt, Lucas) - Skip stolen memory init if it is fully reserved (Jose) - Use iosys_map for GuC data structures that may be in LMEM BAR or SMEM (Lucas) - Do not complain about stale GuC reset notifications for banned contexts (John) - Move context descriptor fields to intel_lrc.h - Start adding support for small BAR (Matt A) - Clarify vma lifetime (Thomas) - Simplify subplatform detection on TGL (Jose) - Correct the param count for unset GuC SLPC param (Vinay, Umesh) - Read RP_STATE_CAP correctly on Gen12 with GuC SLPC (Vinay) - Initialize GuC submission locks and queues early (Daniele) - Fix GuC flag query helper function to not modify state (John) - Drop fake lmem support now we have real hardware available (Lucas) - Move misplaced W/A to their correct locations (Srinivasan) - Use get_reset_domain() helper (Tejas) - Move context descriptor fields to intel_lrc.h (Matt R) - Selftest improvements (Matt A) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for v5.18: UAPI Changes: Cross-subsystem Changes: - Improve performance of some fbdev ops, in some cases up to 6x faster. Core Changes: - Some small DP fixes. - Find panels in subnodes of OF devices, and add of_get_drm_panel_display_mode to retrieve mode. - Add drm_object_property_get_default_value and use it for resetting zpos in plane state reset, removing the need for individual drivers to do it. - Same for color encoding and color range props. - Update panic handling todo doc. - Add todo that format conversion helpers should be sped up similarly to fbdev ops. Driver Changes: - Add panel orientation property to simpledrm for quirked panels. - Assorted small fixes to tiny/repaper, nouveau, stm, omap, ssd130x. - Add crc support to stm/ltdc. - Add MIPI DBI compatible SPI driver - Assorted small fixes to tiny panels and bridge drivers. - Add AST2600 support to aspeed. Signed-off-by:
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git://linuxtv.org/pinchartl/mediaDave Airlie authored
- R-Car LVDS support for M3-W+ (R8A77961) SoC - R-Car DU misc fixes and cleanups Signed-off-by:
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https://gitlab.freedesktop.org/drm/tegraDave Airlie authored
drm/tegra: Changes for v5.18-rc1 This contains a couple more minor fixes that didn't seem urgent enough for v5.17. On top of that this improves YUV format support on older chips. Signed-off-by:
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- 03 Mar, 2022 6 commits
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Laurent Pinchart authored
On Gen3 hardware enabling a VSP plane doesn't change any register that requires DRES to take effect. Avoid a group restart in that case. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
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Laurent Pinchart authored
The VSP1 sink selection through register DEFR8 is only available on Gen2 hardware. Skip it on Gen3. Signed-off-by:
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Laurent Pinchart authored
The rcar-du driver goes to great lengths to preserve device tree backward compatibility for the LVDS encoders by patching old device trees at runtime. The last R-Car Gen2 platform was converted to the new bindings commit edb0c3af ("ARM: dts: r8a7793: Convert to new LVDS DT bindings"), in v4.17, and the last RZ/G1 platform converted in commit 6a6a7976 ("ARM: dts: r8a7743: Convert to new LVDS DT bindings"), in v5.0. Both are older than commit 58256143 ("clk: renesas: Remove R-Car Gen2 legacy DT clock support"), in v5.5, which removes support for legacy bindings for clocks. The LVDS compatibility code is thus not needed anymore. Drop it. Signed-off-by:
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Nikita Yushchenko authored
The M3-W+ SoC has the same LVDS encoder as other R-Car Gen3 chips. Add support for M3-W+ (R8A77961) SoC to the LVDS encoder driver. Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Nikita Yushchenko authored
Document the R-Car M3-W+ (R8A77961) SoC in the R-Car LVDS encoder bindings. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Colin Ian King authored
Pointer mode is being assigned a value that is never read, it is being re-assigned later with a new value. The initialization is redundant and can be removed. Cleans up clang scan build warning: drivers/gpu/drm/solomon/ssd130x.c:582:27: warning: Value stored to 'mode' during its initialization is never read [deadcode.DeadStores] Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Acked-by:
Javier Martinez Canillas <javierm@redhat.com> Signed-off-by:
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- 02 Mar, 2022 23 commits
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Tommy Haung authored
Add AST2600 chip support and setting. Signed-off-by:
Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
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Tommy Haung authored
Add interrupt clear register define for further chip support. Signed-off-by:
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Thomas Zimmermann authored
Add a TODO item for optimizing blitting and format-conversion helpers in DRM and fbdev. There's always demand for faster graphics output. v4: * fix typos (Sam) Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220223193804.18636-6-tzimmermann@suse.de
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Thomas Zimmermann authored
Improve the performance of cfb_imageblit() by manually unrolling the inner blitting loop and moving some invariants out. The compiler failed to do this automatically. This change keeps cfb_imageblit() in sync with sys_imagebit(). A microbenchmark measures the average number of CPU cycles for cfb_imageblit() after a stabilizing period of a few minutes (i7-4790, FullHD, simpledrm, kernel with debugging). cfb_imageblit(), new: 15724 cycles cfb_imageblit(): old: 30566 cycles In the optimized case, cfb_imageblit() is now ~2x faster than before. v3: * fix commit description (Pekka) Signed-off-by:
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Thomas Zimmermann authored
Fix coding style. No functional changes. Signed-off-by:
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Thomas Zimmermann authored
Improve the performance of sys_imageblit() by manually unrolling the inner blitting loop and moving some invariants out. The compiler failed to do this automatically. The resulting binary code was even slower than the cfb_imageblit() helper, which uses the same algorithm, but operates on I/O memory. A microbenchmark measures the average number of CPU cycles for sys_imageblit() after a stabilizing period of a few minutes (i7-4790, FullHD, simpledrm, kernel with debugging). The value for CFB is given as a reference. sys_imageblit(), new: 25934 cycles sys_imageblit(), old: 35944 cycles cfb_imageblit(): 30566 cycles In the optimized case, sys_imageblit() is now ~30% faster than before and ~20% faster than cfb_imageblit(). v2: * move switch out of inner loop (Gerd) * remove test for alignment of dst1 (Sam) Signed-off-by:
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Thomas Zimmermann authored
Improve the performance of sys_fillrect() by using word-aligned 32/64-bit mov instructions. While the code tried to implement this, the compiler failed to create fast instructions. The resulting binary instructions were even slower than cfb_fillrect(), which uses the same algorithm, but operates on I/O memory. A microbenchmark measures the average number of CPU cycles for sys_fillrect() after a stabilizing period of a few minutes (i7-4790, FullHD, simpledrm, kernel with debugging). The value for CFB is given as a reference. sys_fillrect(), new: 26586 cycles sys_fillrect(), old: 166603 cycles cfb_fillrect(): 41012 cycles In the optimized case, sys_fillrect() is now ~6x faster than before and ~1.5x faster than the CFB implementation. Signed-off-by:
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Srinivasan Shanmugam authored
Registers that exist in the shared render/compute reset domain need to be placed on an engine workaround list to ensure that they are properly re-applied whenever an RCS or CCS engine is reset. We have a number of workarounds (updating registers MLTICTXCTL, L3SQCREG1_CCS0, GEN12_MERT_MOD_CTRL, and GEN12_GAMCNTRL_CTRL) that are incorrectly implemented on the 'gt' workaround list and need to be moved accordingly. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.s@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Matt Roper authored
Additional workarounds are required once we start exposing CCS engines. Note that we have a number of workarounds that update registers in the shared render/compute reset domain. Historically we've just added such registers to the RCS engine's workaround list. But going forward we should be more careful to place such workarounds on a wa_list for an engine that definitely exists and is not fused off (e.g., a platform with no RCS would never apply the RCS wa_list). We'll keep rcs_engine_wa_init() focused on RCS-specific workarounds that only need to be applied if the RCS engine is present. A separate general_render_compute_wa_init() function will be used to define workarounds that touch registers in the shared render/compute reset domain and that we need to apply regardless of what render and/or compute engines actually exist. Any workarounds defined in this new function will internally be added to the first present RCS or CCS engine's workaround list to ensure they get applied (and only get applied once rather than being needlessly re-applied several times). Co-author: Srinivasan Shanmugam Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-13-matthew.d.roper@intel.com
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Daniele Ceraolo Spurio authored
HW resources are divided across the active CCS engines at the compute slice level, with each CCS having priority on one of the cslices. If a compute slice has no enabled DSS, its paired compute engine is not usable in full parallel execution because the other ones already fully saturate the HW, so consider it fused off. v2 (José): - moved it to its own function - fixed definition of ccs_mask v3 (Matt): - Replace fls() condition with a simple IP version test v4 (Matt): - Don't try to calculate a ccs_mask using intel_slicemask_from_dssmask() until we've determined that we're running on an Xe_HP platform where the logic makes sense (and won't overflow). Cc: Stuart Summers <stuart.summers@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
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Matthew Brost authored
A different emit breadcrumbs ring programming is required for compute / render and we don't have UMD user so just reject parallel submission for these engine classes. Signed-off-by:
Matthew Brost <matthew.brost@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
Tell GuC that CCS is enabled by setting the CCS mask in its ADS. Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Original-author: Michel Thierry Signed-off-by:
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Matt Roper authored
We have to specify in the Render Control Unit Mode register when CCS is enabled. v2: - Move RCU_MODE programming to a helper function. (Tvrtko) - Clean up and clarify comments. (Tvrtko) - Add RCU_MODE to the GuC save/restore list. (Daniele) v3: - Move this patch before the GuC ADS update to enable compute engines; the definition of RCU_MODE and its insertion into the save/restore list moves to this patch. (Daniele) v4: - Call xehp_enable_ccs_engines() directly in guc_resume() and execlists_resume() rather than adding an extra layer of wrapping to the engine->resume() vfunc. (Umesh) Bspec: 46034 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by:
Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220302001554.1836066-1-matthew.d.roper@intel.com
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Matt Roper authored
In Dual Context mode the EUs are shared between render and compute command streamers. The hardware provides a field in the lrc descriptor to indicate the prioritization of the thread dispatch associated to the corresponding context. The context priority is set to 'low' at creation time and relies on the existing context priority to set it to low/normal/high. Bspec: 46145, 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by:
Prasad Nallani <prasad.nallani@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-8-matthew.d.roper@intel.com
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Matt Roper authored
This is a more appropriate header for these definitions. v2: - Cleanup whitespace. (Lucas) Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-7-matthew.d.roper@intel.com
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Matt Roper authored
The compute engine handles the same commands the render engine can (except 3D pipeline), so it makes sense that CCS is more similar to RCS than non-render engines. The CCS context state (lrc) is also similar to the render one, so reuse it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE register. In order to avoid having multiple RCS && CCS checks, add the following engine flag: - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx. BSpec: 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
CCS will reuse the RCS functions for breadcrumb and flush emission. However, CCS pipe_control has additional programming restrictions: - Command Streamer Stall Enable must be always set - Post Sync Operations must not be set to Write PS Depth Count - 3D-related bits must not be set v2: - Drop unwanted blank line. (Lucas) Bspec: 47112 Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by:
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Matt Roper authored
Add execlists and GuC interrupts for compute CS into existing IRQ handlers. All compute command streamers belong to the same compute class, so the only change needed to enable their interrupts is to program their GT engine interrupt mask registers. CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one. BSpec: 50844, 54029, 54030, 53223, 53224. Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by:
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Matt Roper authored
The reset domain is shared between render and all compute engines, so resetting one will affect the others. Note: Before performing a reset on an RCS or CCS engine, the GuC will attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid impacting other clients (since some shared modules will be reset). If other engines are executing non-preemptable workloads, the impact is unavoidable and some work may be lost. Bspec: 52549 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by:
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Matt Roper authored
Introduce a Compute Command Streamer (CCS), which has access to the media and GPGPU pipelines (but not the 3D pipeline). To begin with, define the compute class/engine common functions, based on the existing render ones. v2: - Add kerneldoc for drm_i915_gem_engine_class since we're adding a new element to it. (Daniel) - Make engine class <-> guc class converters use lookup tables to make it more clear/explicit how the IDs map. (Tvrtko) v3: - Don't update uapi for now; we'll just include the driver-internal changes for the time being. Bspec: 46167, 45544 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Tom Rix authored
For spdx change tab to space delimiter Use // for *.c Replacements commited to committed regsiters to registers initialze to initialize Signed-off-by:
Tom Rix <trix@redhat.com> Reviewed-by:
Steven Price <steven.price@arm.com> Signed-off-by:
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Liu Ying authored
To initialize register NWL_DSI_IRQ_MASK, it's enough to write it only once in function nwl_dsi_init_interrupts(). Signed-off-by:
Liu Ying <victor.liu@nxp.com> Reviewed-by:
Guido Günther <agx@sigxcpu.org> Signed-off-by:
Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220216085842.1973868-1-victor.liu@nxp.com
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Hsin-Yi Wang authored
If the previous transfer didn't end with a command without DP_AUX_I2C_MOT, the next read trasnfer will miss the first byte. But if the command in previous transfer is requested with length 0, it's a no-op to anx7625 since it can't process this command. anx7625 requires the last command to be read command with length > 0. It's observed that if we clear the DP_AUX_I2C_MOT in read transfer, we can still get correct data. Clear the read commands with DP_AUX_I2C_MOT bit to fix this issue. Fixes: adca62ec ("drm/bridge: anx7625: Support reading edid through aux channel") Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
Xin Ji <xji@analogixsemi.com> Signed-off-by:
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