- 27 Sep, 2012 4 commits
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Michael Ellerman authored
In commit 407821a3 we assigned a poison value to the paca->data_offset. Unfortunately with CONFIG_LOCK_STAT=y lockdep will read & write to percpu data very early in boot, prior to us initialising the percpu areas, leading to a crash. We have been getting away with this because the data_offset was previously set to zero. This causes lockdep to read & write to the initial copy of the percpu variables, which are discarded later in boot. Although that is "fishy", it does work, and for lock statistics it is no big deal to discard the counts from early boot. So set the paca->data_offset = 0 for the boot cpu paca only. Reported-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Tested-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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sukadev@linux.vnet.ibm.com authored
powerpc/perf: Sample only if SIAR-Valid bit is set in P7+ On POWER7+ two new bits (mmcra[35] and mmcra[36]) indicate whether the contents of SIAR and SDAR are valid. For marked instructions on P7+, we must save the contents of SIAR and SDAR registers only if these new bits are set. This code/check for the SIAR-Valid bit is specific to P7+, so rather than waste a CPU-feature bit use the PVR flag. Note that Carl Love proposed a similar change for oprofile: https://lkml.org/lkml/2012/6/22/309Signed-off-by:Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
A few more fsl updates from Kumar
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Benjamin Herrenschmidt authored
mpc5xxx updates from Anatolij
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- 19 Sep, 2012 4 commits
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Jia Hongtao authored
Fix the following warning: arch/powerpc/sysdev/fsl_pci.c: In function 'fsl_pci_probe': arch/powerpc/sysdev/fsl_pci.c:867:25: error: unused variable 'hose' Signed-off-by:
Jia Hongtao <B38951@freescale.com> Acked-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Prabhakar Kushwaha authored
IFC may have one or two interrupts. If two interrupt specifiers are present, the first is the "common" interrupt (CM_EVTER_STAT), and the second is the NAND interrupt (NAND_EVTER_STAT). If there is only one, that interrupt reports both types of event. Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
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Chunhe Lan authored
Signed-off-by:
Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by:
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Zhao Chenhui authored
During suspend, all interrupts including IPI will be disabled. In this case, the suspend process will hang in SMP. To prevent this, pass the flag IRQF_NO_SUSPEND when requesting IPI irq. Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
Li Yang <leoli@freescale.com> Acked-by:
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- 18 Sep, 2012 11 commits
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Benjamin Herrenschmidt authored
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Gavin Shan authored
The kernel crash was reported by Alexy. He was testing some feature with private kernel, in which Alexy added some code in pci_pm_reset() to read the CSR after writting it. The bug could be reproduced on Fiber Channel card (Fibre Channel: Emulex Corporation Saturn-X: LightPulse Fibre Channel Host Adapter (rev 03)) by the following commands. # echo 1 > /sys/devices/pci0004:01/0004:01:00.0/reset # rmmod lpfc # modprobe lpfc The history behind the test case is that those additional config space reading operations in pci_pm_reset() would cause EEH error, but we didn't detect EEH error until "modprobe lpfc". For the case, all the PCI devices on PCI bus (0004:01) were removed and added after PE reset. Then the EEH devices would be figured out again based on the OF nodes. Unfortunately, there were some child OF nodes under PCI device (0004:01:00.0), but they didn't have attached PCI_DN since they're invisible from PCI domain. However, we were still trying to convert OF node to EEH device without checking on the attached PCI_DN. Eventually, it caused the kernel crash as follows: Unable to handle kernel paging request for data at address 0x00000030 Faulting instruction address: 0xc00000000004d888 cpu 0x0: Vector: 300 (Data Access) at [c000000fc797b950] pc: c00000000004d888: .eeh_add_device_tree_early+0x78/0x140 lr: c00000000004d880: .eeh_add_device_tree_early+0x70/0x140 sp: c000000fc797bbd0 msr: 8000000000009032 dar: 30 dsisr: 40000000 current = 0xc000000fc78d9f70 paca = 0xc00000000edb0000 softe: 0 irq_happened: 0x00 pid = 2951, comm = eehd enter ? for help [c000000fc797bc50] c00000000004d848 .eeh_add_device_tree_early+0x38/0x140 [c000000fc797bcd0] c00000000004d848 .eeh_add_device_tree_early+0x38/0x140 [c000000fc797bd50] c000000000051b54 .pcibios_add_pci_devices+0x34/0x190 [c000000fc797bde0] c00000000004fb10 .eeh_reset_device+0x100/0x160 [c000000fc797be70] c0000000000502dc .eeh_handle_event+0x19c/0x300 [c000000fc797bf00] c000000000050570 .eeh_event_handler+0x130/0x1a0 [c000000fc797bf90] c000000000020138 .kernel_thread+0x54/0x70 The patch changes of_node_to_eeh_dev() and just returns NULL if the passed OF node doesn't have attached PCI_DN. Cc: stable@vger.kernel.org Reported-by:Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by:
Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by:
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Gavin Shan authored
The EEH core is talking with the PCI device driver to determine the action (purely reset, or PCI device removal). During the period, the driver might be unloaded and in turn causes kernel crash as follows: EEH: Detected PCI bus error on PHB#4-PE#10000 EEH: This PCI device has failed 3 times in the last hour lpfc 0004:01:00.0: 0:2710 PCI channel disable preparing for reset Unable to handle kernel paging request for data at address 0x00000490 Faulting instruction address: 0xd00000000e682c90 cpu 0x1: Vector: 300 (Data Access) at [c000000fc75ffa20] pc: d00000000e682c90: .lpfc_io_error_detected+0x30/0x240 [lpfc] lr: d00000000e682c8c: .lpfc_io_error_detected+0x2c/0x240 [lpfc] sp: c000000fc75ffca0 msr: 8000000000009032 dar: 490 dsisr: 40000000 current = 0xc000000fc79b88b0 paca = 0xc00000000edb0380 softe: 0 irq_happened: 0x00 pid = 3386, comm = eehd enter ? for help [c000000fc75ffca0] c000000fc75ffd30 (unreliable) [c000000fc75ffd30] c00000000004fd3c .eeh_report_error+0x7c/0xf0 [c000000fc75ffdc0] c00000000004ee00 .eeh_pe_dev_traverse+0xa0/0x180 [c000000fc75ffe70] c00000000004ffd8 .eeh_handle_event+0x68/0x300 [c000000fc75fff00] c0000000000503a0 .eeh_event_handler+0x130/0x1a0 [c000000fc75fff90] c000000000020138 .kernel_thread+0x54/0x70 1:mon> The patch increases the reference of the corresponding driver modules while EEH core does the negotiation with PCI device driver so that the corresponding driver modules can't be unloaded during the period and we're safe to refer the callbacks. Cc: stable@vger.kernel.org Reported-by: -
Tiejun Chen authored
We don't do the real store operation for kprobing 'stwu Rx,(y)R1' since this may corrupt the exception frame, now we will do this operation safely in exception return code after migrate current exception frame below the kprobed function stack. So we only update gpr[1] here and trigger a thread flag to mask this. Note we should make sure if we trigger kernel stack over flow. Signed-off-by:
Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by:
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Tiejun Chen authored
We can't emulate stwu since that may corrupt current exception stack. So we will have to do real store operation in the exception return code. Firstly we'll allocate a trampoline exception frame below the kprobed function stack and copy the current exception frame to the trampoline. Then we can do this real store operation to implement 'stwu', and reroute the trampoline frame to r1 to complete this exception migration. Signed-off-by:
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Tiejun Chen authored
We need to add a new thread flag, TIF_EMULATE_STACK_STORE, for emulating stack store operation while exiting exception. Signed-off-by:
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Bharat Bhushan authored
__get_user64() and __put_user64() are not used. Signed-off-by:
Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by:
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Gavin Shan authored
We have missed lots of situations where the PE hierarchy tree need protection through the EEH global mutex. The patch fixes that for those public APIs implemented in eeh_pe.c. The only exception is eeh_pe_restore_bars() because it calls eeh_pe_dev_traverse(), which has been protected by the mutex. Signed-off-by:
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Gavin Shan authored
Function eeh_rmv_from_parent_pe() could be called by the path of either normal PCI hotplug, or EEH recovery. For the former case, we need purge the corresponding PE on removal of the associated PE bus. The patch tries to cover that by passing more information to function pcibios_remove_pci_devices() so that we know if the corresponding PE needs to be purged or be marked as "invalid". Signed-off-by:
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Gavin Shan authored
When EEH error happens on the PE whose PCI devices don't have attached drivers. In function eeh_handle_event(), the default value PCI_ERS_RESULT_NONE will be returned after iterating all drivers of those PCI devices belonging to the PE. Actually, we don't have installed drivers for the PCI devices. Under the circumstance, we will remove the corresponding PCI bus of the PE, including the associated EEH devices and PE instance. However, we still need the information stored in the PE instance to do PE reset after that. So it's unsafe to free the PE instance. The patch introduces EEH_PE_INVALID type PE to address the issue. When the PCI bus and the corresponding attached EEH devices are removed, we will mark the PE as EEH_PE_INVALID. At later point, the PE will be changed to EEH_PE_DEVICE or EEH_PE_BUS when the corresponding EEH devices are attached again. Signed-off-by:
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Michael Ellerman authored
This was originally motivated by a desire to see the mapping between logical and hardware cpu numbers. But it seemed that it made more sense to just add a command to dump (most of) the paca. With no arguments "dp" will dump the paca for the current cpu. It also takes an argument, eg. "dp 3" which is the logical cpu number in hex. This form does not check if the cpu is possible, but displays the paca regardless, as well as the cpu's state in the possible, present and online masks. Thirdly, "dpa" will display the paca for all possible cpus. If there are no possible cpus, like early in boot, it will tell you that. Sample output, number in brackets is the offset into the struct: 2:mon> dp 3 paca for cpu 0x3 @ c00000000ff20a80: possible = yes present = yes online = yes lock_token = 0x8000 (0x8) paca_index = 0x3 (0xa) kernel_toc = 0xc00000000144f990 (0x10) kernelbase = 0xc000000000000000 (0x18) kernel_msr = 0xb000000000001032 (0x20) stab_real = 0x0 (0x28) stab_addr = 0x0 (0x30) emergency_sp = 0xc00000003ffe4000 (0x38) data_offset = 0xa40000 (0x40) hw_cpu_id = 0x9 (0x50) cpu_start = 0x1 (0x52) kexec_state = 0x0 (0x53) __current = 0xc00000007e568680 (0x218) kstack = 0xc00000007e5a3e30 (0x220) stab_rr = 0x1a (0x228) saved_r1 = 0xc00000007e7cb450 (0x230) trap_save = 0x0 (0x240) soft_enabled = 0x0 (0x242) irq_happened = 0x0 (0x243) io_sync = 0x0 (0x244) irq_work_pending = 0x0 (0x245) nap_state_lost = 0x0 (0x246) Signed-off-by:
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- 17 Sep, 2012 21 commits
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Gavin Shan authored
We don't need them anymore. The patch removes those functions. Signed-off-by:
Ram Pai <linuxram@us.ibm.com> Reviewed-by:
Richard Yang <weiyang@linux.vnet.ibm.com> Signed-off-by:
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Gavin Shan authored
Currently, the PCI probe flags "PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC" used on powernv platform. That means the platform has to do the PCI resource assignment by itself. The patch changes the PCI probe flag to "PCI_REASSIGN_ALL_RSRC" so that the PCI core will do the resource assignment. Also, the I/O and MMIO minimal alignment for P2P bridges have been configured while doing fixup for the PHBs. Signed-off-by:
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Gavin Shan authored
There're 2 arrays introduced to trace which PE has occupied the corresponding resource (I/O or MMIO) segment. However, we didn't allocate enough memory for them and that possiblly leads to PE descriptor corruption. The patch fixes that by allocating enough memory for those 2 arrays. Signed-off-by:
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Gavin Shan authored
While the device driver or PCI core tries to enable PCI device, the platform dependent callback "ppc_md.pcibios_enable_device_hook" will be called to check if there has one associated PE for the PCI device. If we don't have the associated PE for the PCI device, it's not allowed to enable the PCI device. Unfortunately, there might have some cases we have to enable the PCI device (e.g. P2P bridge), but the PEs have not been created yet. The patch handles the unfortunate cases. Each PHB (struct pnv_phb) has one field "initialized" to trace if the PEs have been created and configured or not. When the PEs are not available, we won't check the associated PE for the PCI device to be enabled. Signed-off-by:
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Gavin Shan authored
The patch introduces additional wrapper function to call the original implementation so that the DMA can be configured for all existing PEs. Signed-off-by:
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Gavin Shan authored
There're 2 types of PCI bus sensitive PEs: (A) The PE includes single PCI bus. (B) The PE includes the PCI bus and all the subordinate PCI buses, and the patch tries to assign I/O and MMIO resources based on created PEs. Fortunately, we figured out unified scheme to do resource assignment for all types of PCI bus based PEs according to Ben's idea: - Resource assignment based on PE from top to bottom. - The soureces, either I/O or MMIO, of the PE are figured out from the assigned PCI bus. - The occupied resource by parent PE could possibilly be overrided by children PEs. Signed-off-by: -
Gavin Shan authored
The resource (I/O and MMIO) will be assigned on basis of PE from top to bottom so that we can implement the trick here: the resource that has been assigned to parent PE could be taken by child PE if necessary. The current implementation already has PE list per PHB basis, but the list doesn't meet our requirment: tracing PE based on their cration time from top to bottom. So the patch does rename for the DMA based PE list and introduces the list to trace the PEs sequentially based on their creation time. Signed-off-by:
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Gavin Shan authored
Basically, there're 2 types of PCI bus sensitive PEs: (A) The PE includes single PCI bus. (B) The PE includes the PCI bus and all the subordinate PCI buses. At present, we'd like to put PCI bus originated by PCI-e link to form PE that contains single PCI bus, and the PCIe-to-PCI bridge will form the 2nd type of PE. We don't figure out to detect PLX bridge yet. Once we can detect PLX bridge some day, we have to put PCI buses originated from the downstream port of PLX bridge to the 2nd type of PE. The patch changes the original implementation for a little bit to support 2 types of PCI bus sensitive PEs described as above. Also, the function used to retrieve the corresponding PE according to the given PCI device has been changed based on that because each PCI device should trace the directly associated PE. Signed-off-by:
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Li Zhong authored
There are a few tracepoints in the interrupt code path, which is before irq_enter(), or after irq_exit(), like trace_irq_entry()/trace_irq_exit() in do_IRQ(), trace_timer_interrupt_entry()/trace_timer_interrupt_exit() in timer_interrupt(). If the interrupt is from idle(), and because tracepoint contains RCU read-side critical section, we could see following suspicious RCU usage reported: [ 145.127743] =============================== [ 145.127747] [ INFO: suspicious RCU usage. ] [ 145.127752] 3.6.0-rc3+ #1 Not tainted [ 145.127755] ------------------------------- [ 145.127759] /root/.workdir/linux/arch/powerpc/include/asm/trace.h:33 suspicious rcu_dereference_check() usage! [ 145.127765] [ 145.127765] other info that might help us debug this: [ 145.127765] [ 145.127771] [ 145.127771] RCU used illegally from idle CPU! [ 145.127771] rcu_scheduler_active = 1, debug_locks = 0 [ 145.127777] RCU used illegally from extended quiescent state! [ 145.127781] no locks held by swapper/0/0. [ 145.127785] [ 145.127785] stack backtrace: [ 145.127789] Call Trace: [ 145.127796] [c00000000108b530] [c000000000013c40] .show_stack +0x70/0x1c0 (unreliable) [ 145.127806] [c00000000108b5e0] [c0000000000f59d8] .lockdep_rcu_suspicious+0x118/0x150 [ 145.127813] [c00000000108b680] [c00000000000fc58] .do_IRQ+0x498/0x500 [ 145.127820] [c00000000108b750] [c000000000003950] hardware_interrupt_common+0x150/0x180 [ 145.127828] --- Exception: 501 at .plpar_hcall_norets+0x84/0xd4 [ 145.127828] LR = .check_and_cede_processor+0x38/0x70 [ 145.127836] [c00000000108bab0] [c0000000000665dc] .shared_cede_loop +0x5c/0x100 [ 145.127844] [c00000000108bb70] [c000000000588ab0] .cpuidle_enter +0x30/0x50 [ 145.127850] [c00000000108bbe0] [c000000000588b0c] .cpuidle_enter_state+0x3c/0xb0 [ 145.127857] [c00000000108bc60] [c000000000589730] .cpuidle_idle_call +0x150/0x6c0 [ 145.127863] [c00000000108bd30] [c000000000058440] .pSeries_idle +0x10/0x40 [ 145.127870] [c00000000108bda0] [c00000000001683c] .cpu_idle +0x18c/0x2d0 [ 145.127876] [c00000000108be60] [c00000000000b434] .rest_init +0x124/0x1b0 [ 145.127884] [c00000000108bef0] [c0000000009d0d28] .start_kernel +0x568/0x588 [ 145.127890] [c00000000108bf90] [c000000000009660] .start_here_common +0x20/0x40 This is because the RCU usage in interrupt context should be used in area marked by rcu_irq_enter()/rcu_irq_exit(), called in irq_enter()/irq_exit() respectively. Move them into the irq_enter()/irq_exit() area to avoid the reporting. Signed-off-by:
Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by:
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Aneesh Kumar K.V authored
slice array size and slice mask size depend on PGTABLE_RANGE. Reviewed-by:
Paul Mackerras <paulus@samba.org> Signed-off-by:
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Aneesh Kumar K.V authored
This update the proto-VSID and VSID scramble related information to be more generic by using names instead of current values. Reviewed-by:
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Aneesh Kumar K.V authored
Increase max addressable range to 64TB. This is not tested on real hardware yet. Reviewed-by:
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Aneesh Kumar K.V authored
With larger vsid we need to track more bits of ESID in slb cache for slb invalidate. Reviewed-by:
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Aneesh Kumar K.V authored
ASM_VSID_SCRAMBLE can leave non-zero bits in the high 28 bits of the result for 256MB segment (40 bits for 1T segment). Properly mask them before using the values in slbmte Reviewed-by:
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Aneesh Kumar K.V authored
This patch makes the high psizes mask as an unsigned char array so that we can have more than 16TB. Currently we support upto 64TB Reviewed-by:
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Aneesh Kumar K.V authored
As we keep increasing PGTABLE_RANGE we need not increase the virual map area for kernel. Reviewed-by:
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Aneesh Kumar K.V authored
This patch convert different functions to take virtual page number instead of virtual address. Virtual page number is virtual address shifted right by VPN_SHIFT (12) bits. This enable us to have an address range of upto 76 bits. Reviewed-by:
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Aneesh Kumar K.V authored
This patch simplify hpte_decode for easy switching of virtual address to virtual page number in the later patch Reviewed-by:
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Aneesh Kumar K.V authored
Don't open code the same Reviewed-by:
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Aneesh Kumar K.V authored
To clarify the meaning for future readers, replace the open coded 19 with CONTEXT_BITS Reviewed-by:
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Scott Wood authored
PTRS_PER_PUD should be based on PUD_INDEX_SIZE, not PMD_INDEX_SIZE. We got away with it because PUD and PMD had the same index size, but this is no longer true with Aneesh's patchset to support a 46-bit user effective address space. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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