1. 22 Jun, 2015 6 commits
    • Vineet Gupta's avatar
      ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks · 4de0e528
      Vineet Gupta authored
      The issue was, on HS when interrupt is taken, IRQ_ACT is set and that is
      NOT cleared unless we do RTIE (or manually clear it). Linux interrupt
      handling has top and bottom halves. Latter lead to softirqs (which can
      reschedule) AND expect interrupts to be REALLY re-enabled which was NOT
      happening for us since we only SETI, dont clear IRQ_ACT
      
      So we can have a state when both cores have taken interrupt (IRQ_ACT set),
      get rescheduled, both send IPI and wait in CSD lock which will never be
      cleared as cores can't take the pending IPI IRQ due to existing IRQ_ACT
      set.
      
      So local_irq_enable() now drops the IRQ_ACT.act bit to re-enable IRQs.
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      4de0e528
    • Vineet Gupta's avatar
      ARCv2: STAR 9000808988: signals involving Delay Slot · 0d7b8855
      Vineet Gupta authored
      Reported by Anton as LTP:munmap01 failing with Illegal Instruction
      Exception.
      
         --------------------->8--------------------------------------
         mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
         munmap(0x200d2000, 24576)               = 0
         --- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
         ---
         potentially unexpected fatal signal 4.
         Path: /munmap01
         CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
         task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
      
         [ECR   ]: 0x00020100 => Illegal Insn
         [EFA   ]: 0x0001354c
         [BLINK ]: 0x200515d4
         [ERET  ]: 0x1354c
             @off 0x1354c in [/munmap01]
             VMA: 0x00010000 to 0x00018000
         [STAT32]: 0x800802c0
         ...
         --------------------->8--------------------------------------
      
      The issue was
      1. munmap01 accessed unmapped memory (on purpose) with signal handler
         installed for SIGSEGV
      
      2. The faulting instruction happened to be in Delay Slot
         00011864 <main>:
            11908:	bl.d       13284 <tst_resm>
            1190c:	stb        r16,[r2]
      
      3. kernel sets up the reg file for signal handler and correctly clears
         the DE bit in pt_regs->status32 placeholder
      
      4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
         and it over-writes the above with orig/stale value of status32
      
      5. After RTIE, userspace signal handler executes a non branch
         instruction with DE bit set, triggering Illegal Instruction Exception.
      Reported-by: default avatarAnton Kolesov <akolesov@synopsys.com>
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      0d7b8855
    • Vineet Gupta's avatar
    • Vineet Gupta's avatar
      ARCv2: Support for ARCv2 ISA and HS38x cores · 1f6ccfff
      Vineet Gupta authored
      The notable features are:
          - SMP configurations of upto 4 cores with coherency
          - Optional L2 Cache and IO-Coherency
          - Revised Interrupt Architecture (multiple priorites, reg banks,
              auto stack switch, auto regfile save/restore)
          - MMUv4 (PIPT dcache, Huge Pages)
          - Instructions for
      	* 64bit load/store: LDD, STD
      	* Hardware assisted divide/remainder: DIV, REM
      	* Function prologue/epilogue: ENTER_S, LEAVE_S
      	* IRQ enable/disable: CLRI, SETI
      	* pop count: FFS, FLS
      	* SETcc, BMSKN, XBFU...
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      1f6ccfff
    • Vineet Gupta's avatar
      ARCv2: [intc] HS38 core interrupt controller · 820970a5
      Vineet Gupta authored
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      820970a5
    • Vineet Gupta's avatar
      ARC: uncached base is hard constant for ARC, don't save it · 10d11e58
      Vineet Gupta authored
      ioremap already uses the hard define, just make sure BCR value matches
      that
      Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
      10d11e58
  2. 19 Jun, 2015 34 commits