1. 17 Dec, 2012 3 commits
  2. 13 Dec, 2012 1 commit
  3. 11 Dec, 2012 1 commit
    • Takashi Iwai's avatar
      drm/i915: Fix shifted screen on top of LVDS on IVY laptop · 335c07b7
      Takashi Iwai authored
      The commit [23670b32: drm/i915: CPT+ pch transcoder workaround]
      caused a regression on some HP laptops with IvyBridge.  The whole
      laptop screen is shifted downward for a few pixels constantly.
      The problem appears only on LVDS while DP and VGA seem unaffected.
      Also, the problem disappears once when go and back from S3.
      (S4 resume still shows the same problem.)
      
      This patch revives the minimum part the commit above dropped.
      For fixing this regression, only the setup of CHICKEN2 bit in
      cpt_init_clock_gating() is needed.
      Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      335c07b7
  4. 10 Dec, 2012 4 commits
    • Daniel Vetter's avatar
      drm/i915: disable cpt phase pointer fdi rx workaround · 539526b4
      Daniel Vetter authored
      We've originally added this in
      
      commit 291427f5
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Fri Jul 29 12:42:37 2011 -0700
      
          drm/i915: apply phase pointer override on SNB+ too
      
      and then copy-pasted it over to ivb/ppt. The w/a was originally added
      for ilk/ibx in
      
      commit 5b2adf89
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Thu Oct 7 16:01:15 2010 -0700
      
          drm/i915: add Ironlake clock gating workaround for FDI link training
      
      and fixed up a bit in
      
      commit 6f06ce18
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Tue Jan 4 15:09:38 2011 -0800
      
          drm/i915: set phase sync pointer override enable before setting phase sync pointer
      
      It turns out that this w/a isn't actually required on cpt/ppt and
      positively harmful on ivb/ppt when using fdi B/C links - it results in
      a black screen occasionally, with seemingfully everything working as
      it should. The only failure indication I've found in the hw is that
      eventually (but not right after the modeset completes) a pipe underrun
      is signalled.
      
      Big thanks to Arthur Runyan for all the ideas for registers to check
      and changes to test, otherwise I couldn't ever have tracked this down!
      
      Cc: "Runyan, Arthur J" <arthur.j.runyan@intel.com>
      Cc: stable@vger.kernel.org
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      539526b4
    • Paulo Zanoni's avatar
      drm/i915: set the LPT FDI RX polarity reversal bit when needed · 68d18ad7
      Paulo Zanoni authored
      If we fail to set the bit when needed we get some nice FDI link
      training failures (AKA "black screen on VGA output").
      
      While we don't really know how to properly choose whether we need to
      set the bit or not (VBT?), just read the initial value set by the BIOS
      and store it for later usage.
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      68d18ad7
    • Paulo Zanoni's avatar
      drm/i915: add lpt_init_pch_refclk · dde86e2d
      Paulo Zanoni authored
      We need this code to init the PCH SSC refclk and the FDI registers.
      The BIOS does this too and that's why VGA worked before this patch,
      until you tried to suspend the machine...
      
      This patch implements the "Sequence to enable CLKOUT_DP for FDI usage
      and configure PCH FDI/IO" from our documentation.
      
      v2:
      - Squash Damien Lespiau's reset spelling fix on top.
      - Add a comment that we don't need to bother about the ULT special
        case Damien noticed, since ULT won't have VGA.
      - Add a comment to rip out the SDV codepaths once haswell ships for
        real.
      
      Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      dde86e2d
    • Paulo Zanoni's avatar
      drm/i915: add support for mPHY destination on intel_sbi_{read, write} · 988d6ee8
      Paulo Zanoni authored
      This way we should be able to write mPHY registers using the Sideband
      Interface in the next commit. Also fixed some syntax oddities in the
      related code.
      Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      988d6ee8
  5. 08 Dec, 2012 2 commits
  6. 06 Dec, 2012 1 commit
    • Chris Wilson's avatar
      drm/i915: Close race between processing unpin task and queueing the flip · e7d841ca
      Chris Wilson authored
      Before queuing the flip but crucially after attaching the unpin-work to
      the crtc, we continue to setup the unpin-work. However, should the
      hardware fire early, we see the connected unpin-work and queue the task.
      The task then promptly runs and unpins the fb before we finish taking
      the required references or even pinning it... Havoc.
      
      To close the race, we use the flip-pending atomic to indicate when the
      flip is finally setup and enqueued. So during the flip-done processing,
      we can check more accurately whether the flip was expected.
      
      v2: Add the appropriate mb() to ensure that the writes to the page-flip
      worker are complete prior to marking it active and emitting the MI_FLIP.
      On the read side, the mb should be enforced by the spinlocks.
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: stable@vger.kernel.org
      [danvet: Review the barriers a bit, we need a write barrier both
      before and after updating ->pending. Similarly we need a read barrier
      in the interrupt handler both before and after reading ->pending. With
      well-ordered irqs only one barrier in each place should be required,
      but since this patch explicitly sets out to combat spurious interrupts
      with is staged activation of the unpin work we need to go full-bore on
      the barriers, too. Discussed with Chris Wilson on irc and changes
      acked by him.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      e7d841ca
  7. 05 Dec, 2012 1 commit
  8. 04 Dec, 2012 2 commits
  9. 03 Dec, 2012 2 commits
  10. 29 Nov, 2012 12 commits
  11. 23 Nov, 2012 1 commit
  12. 22 Nov, 2012 3 commits
  13. 21 Nov, 2012 7 commits