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  1. 09 May, 2012 8 commits
    • Archit Taneja's avatar
      OMAPDSS: APPLY: Don't check manager settings if it is disabled · 5dd747e8
      Archit Taneja authored 
      If a manager is disabled, there is no guarantee at any point in time that all
it's parameters are configured. There is always a chance that some more
parameters are yet to be configured by a user of DSS, or by DSS itself.

However, when the manager is enabled, we can be certain that all the parameters
have been configured, as we can't enable a manager with an incomplete
configuration. Therefore, if a manager is disabled, don't check for the validity
of it's parameters or the parameters of the overlays connected to it. Only check
once it is enabled. Add a check in dss_check_settings_low() to achieve the same.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      5dd747e8
    • Archit Taneja's avatar
      OMAPDSS: MANAGER: Create a function to check manager timings · b917fa39
      Archit Taneja authored 
      Create a function dss_mgr_check_timings() which wraps around the function
dispc_mgr_timings_ok(). This is mainly a clean up to hide dispc functions
from interface drivers.

dss_mgr_check_timings() is added in the function dss_mgr_check(), it currently
takes the timings maintained in the omap_dss_device struct. This would be later
replaced by the timings stored in the manager's private data.

Make dss_mgr_check_timings() and dispc_mgr_timings_ok() take a const
omap_video_timings pointer since these functions just check the timings.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      b917fa39
    • Archit Taneja's avatar
      OMAPDSS: Apply manager timings instead of direct DISPC writes · 41721163
      Archit Taneja authored 
      Replace the function dispc_mgr_set_timings() with dss_mgr_set_timings() in the
interface drivers. The latter function ensures that the timing related DISPC
registers are configured according to the shadow register programming model.

Remove the call to dispc_mgr_go() in dpi_set_timings() as the manager's go bit
is set by dss_mgr_set_timings().
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      41721163
    • Archit Taneja's avatar
      OMAPDSS: APPLY: Add manager timings as extra_info in private data · 45324a26
      Archit Taneja authored 
      DISPC manager size and DISPC manager blanking parameters(for LCD managers)
follow the shadow register programming model. Currently, they are programmed
directly by the interface drivers.

To configure manager timings using APPLY, there is a need to introduce extra
info flags for managers, similar to what is done for overlays. This is needed
because timings aren't a part of overlay_manager_info struct configured by a
user of DSS, they are configured internally by the interface or panel drivers.

Add dirty and shadow_dirty extra_info flags for managers, update these flags
at the appropriate places. Rewrite the function extra_info_update_ongoing()
slightly as checking for manager's extra_info flags can simplify the code a bit.

Create function dss_mgr_set_timings() which applies the new manager timings to
extra_info.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
      45324a26
    • Archit Taneja's avatar
      OMAPDSS: DISPC: Remove Fake VSYNC support · 408d9dbb
      Archit Taneja authored 
      Fake VSYNC support is a hack and has some bugs in it. It isn't used by any user
of DSS. Remove Fake VSYNC support. For DSI command mode and RFBI panels, a user
of DSS should wait for the completion of a frame by using the panel driver's
sync op.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      408d9dbb
    • Archit Taneja's avatar
      OMAPDSS: Fix DSI_FCLK clock source selection · a2e5d827
      Archit Taneja authored 
      The wrong bit field was being updated in DSS_CTRL when trying to configure the
clock source of DSI2 functional clock. Use the correct bit field based on the
dsi module number.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      a2e5d827
    • Archit Taneja's avatar
      OMAPDSS: HDMI: define and dump CORE registers in correct order · 9b9c457b
      Archit Taneja authored 
      The HDMI core register offset macros aren't defined in ascending order of their
values, some of the offset macros are also redefined. The same issues occur when
these core registers are dumped.

Clean up the ordering of HDMI core registers and remove repeated registers in
the definition in ti_hdmi_4xxx_ip.h and in ti_hdmi_4xxx_core_dump().
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      9b9c457b
    • Archit Taneja's avatar
      OMAPDSS: HDMI: Fix ti_hdmi_4xxx_core_dump · 3c7de247
      Archit Taneja authored 
      The function ti_hdmi_4xxx_core_dump has some bugs, the following mention the
bugs and the solutions:

- The macros DUMPCORE and DUMPCOREAV in ti_hdmi_4xxx_core_dump() use
  hdmi_pll_base() for the offsets needed to calculate register addresses, use
  functions hdmi_core_sys_base() amd hdmi_av_base() to calculate the correct
  offsets for CORE_SYS and CORE_AV registers.

- Many of the CORE_AV registers use the DUMPCORE macro, and hence the register
  addresses are calculated incorrectly. Rename the current DUMPCOREAV macro as
  DUMPCOREAV2 as it takes 2 arguments to dump indexed CORE_AV registers, create
  a new macro called DUMPCOREAV which is now used for dumping non-indexed
  CORE_AV registers.

Thanks to Ancy Tom <ancytom@gmail.com> for pointing out the issues.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      3c7de247
  3. 03 May, 2012 3 commits
    • Chandrabhanu Mahapatra's avatar
      OMAPDSS: DISPC: Correct DISPC functional clock usage · 8b53d991
      Chandrabhanu Mahapatra authored 
      DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling
calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC.
DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC
divisor LCD.
Signed-off-by: default avatarChandrabhanu Mahapatra <cmahapatra@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      8b53d991
    • Chandrabhanu Mahapatra's avatar
      OMAPDSS: DISPC: Handle synclost errors in OMAP3 · 7faa9233
      Chandrabhanu Mahapatra authored 
      In OMAP3 DISPC video overlays suffer from some undocumented horizontal position
and timing related limitations leading to SYNCLOST errors. Whenever the image
window is moved towards the right of the screen SYNCLOST errors become
frequent. Checks have been implemented to see that DISPC driver rejects
configuration exceeding above limitations.

This code was successfully tested on OMAP3. This code is written based on code
written by Ville Syrjälä <ville.syrjala@nokia.com> in Linux OMAP kernel. Ville
Syrjälä <ville.syrjala@nokia.com> had added checks for video overlay horizontal
timing and DISPC horizontal blanking length limitations.
Signed-off-by: default avatarChandrabhanu Mahapatra <cmahapatra@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      7faa9233
    • Chandrabhanu Mahapatra's avatar
      OMAPDSS: DISPC: Enable predecimation · aed74b55
      Chandrabhanu Mahapatra authored 
      In OMAP3 and OMAP4, the DISPC Scaler can downscale an image up to 4 times, and
up to 2 times in OMAP2. However, with predecimation, the image can be reduced
to 16 times by fetching only the necessary pixels in memory. Then this
predecimated image can be downscaled further by the DISPC scaler.

The pipeline is configured to use a burst of size 8 * 128 bits which consists
of 8 mini bursts of 16 bytes each. So, horizontal predecimation more than 16
can lead to complete discarding of such mini bursts. L3 interconnect may
handover the bus to some other initiator and inturn delay the fetching of
pixels leading to underflows. So, maximum predecimation limit is fixed at 16.

Based on the downscaling required, a prior calculation of predecimation values
for width and height of an image is done. Since, Predecimation reduces quality
of an image higher priorty is given to DISPC Scaler for downscaling.

This code was successfully tested on OMAP2, OMAP3 and OMAP4. Horizontal and
vertical predecimation worked fine except for some synclost errors due to
undocumented errata in OMAP3 which are fixed later and skewed images were seen
on OMAP2 and OMAP3 during horizontal predecimation which will be addressed in
the future patches.

This code is based on code written by Lajos Molnar <lajos@ti.com> who had added
predecimation support for NV12/YUV/rotated/SDMA buffers.
Signed-off-by: default avatarChandrabhanu Mahapatra <cmahapatra@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      aed74b55
  5. 23 Apr, 2012 17 commits
  7. 21 Apr, 2012 12 commits
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