- 31 Aug, 2019 4 commits
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Marek Behún authored
This adds support for the Turris Mox board from CZ.NIC. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic board can be extended by different modules. If those are connected, U-Boot lets the kernel know via device-tree. Since modules can be connected in different order and some modules can be connected multiple times (up to three modules containing 8-port ethernet switch in DSA configuration can be connected) we decided against using device-tree overlays, because it got complicated rather quickly. (For example the SFP module can be connected directly to the CPU, or after a switch module. There are four cases and all would need different SFP overlay. There are two types of switch modules (8-port with pass-through and 4-port with no pass-through). For those we would again need at least 6 more overlays.) We therefore decided to put all the possibly connected devices in one device-tree and disable them by default. When U-Boot finds out which modules are connected, it fixes the loaded device-tree accordingly just before boot. By Rob Herring's suggestion we also made it so that U-Boot completely removes nodes which are disabled after this fixup. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Cc: Rob Herring <robh@kernel.org> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Marek Behún authored
This adds the documentation for the Turris Mox compatible in armada-37xx device-tree binding documentation. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Rob Herring <robh@kernel.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Marek Behún authored
This adds pinctrl node for the GPIO to be used as SPI chip select 1. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Gregory CLEMENT authored
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- 27 Aug, 2019 7 commits
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Gregory CLEMENT authored
Add cpu clock node on AP Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Miquel Raynal authored
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent) generic PHY framework instead of the (legacy) usb-phy preperty. Both enable the supply when the PHY is enabled. The COMPHY nodes only provide SERDES lanes configuration. The power supply that is represented by the phy-supply property is just a regulator wired to the USB connector, hence the creation of connector nodes as child of the COMPHY nodes and the supply attached to it. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Miquel Raynal authored
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k based boards. The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports x4 link widths and in this case the PHY for each lane must be referenced. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Miquel Raynal authored
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k based boards. Only update nodes actually enabling USB3 in the default (mainline) configuration. A few USB nodes are enabled but there is only USB2 working on them. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Miquel Raynal authored
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Miquel Raynal authored
Declare the three clocks feeding the COMPHY block. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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Marek Behún authored
This adds the rWTM BIU mailbox node for communication with the secure processor. The driver already exists in drivers/mailbox/armada-37xx-rwtm-mailbox.c. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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- 15 Aug, 2019 1 commit
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Arnd Bergmann authored
Merge tag 'tee-optee-for-5.4' of git://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers Add might_sleep() in OP-TEE RPC requests * tag 'tee-optee-for-5.4' of git://git.linaro.org/people/jens.wiklander/linux-tee: tee: optee: add might_sleep for RPC requests Link: https://lore.kernel.org/r/20190815065659.GA13498@jaxSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 14 Aug, 2019 7 commits
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Arnd Bergmann authored
Merge tag 'scmi-updates-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers ARM SCMI updates/fixes for v5.4 Handful of fixes/updates including: 1. SCMI v2.0(recently released) support for: - Performance protocol fast channels - Reset Management Protocol 2. SCMI infrastructure/core support for recieve(Rx) channels, asynchronous commands and delayed response 3. Usage of asynchronous commands for clock rate setting and sensor reading based on the attributes read from the firmware 4. Miscellaneous cleanups(typos, naming alignment with specification, and SPDX License identifier) 5. Couple of fixes: removal of extra check for invalid length and additional check to ensure platform/firmware has released shared memory before using it in OSPM * tag 'scmi-updates-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (22 commits) reset: Add support for resets provided by SCMI firmware: arm_scmi: Add RESET protocol in SCMI v2.0 dt-bindings: arm: Extend SCMI to support new reset protocol firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels firmware: arm_scmi: Use {get,put}_unaligned_le{32,64} accessors firmware: arm_scmi: Use asynchronous CLOCK_RATE_SET when possible firmware: arm_scmi: Drop config flag in clk_ops->rate_set firmware: arm_scmi: Add asynchronous sensor read if it supports firmware: arm_scmi: Drop async flag in sensor_ops->reading_get firmware: arm_scmi: Add support for asynchronous commands and delayed response firmware: arm_scmi: Add mechanism to unpack message headers firmware: arm_scmi: Separate out tx buffer handling and prepare to add rx firmware: arm_scmi: Add receive channel support for notifications firmware: arm_scmi: Segregate tx channel handling and prepare to add rx firmware: arm_scmi: Reorder some functions to avoid forward declarations firmware: arm_scmi: Check if platform has released shmem before using firmware: arm_scmi: Use the term 'message' instead of 'command' firmware: arm_scmi: Fix few trivial typos in comments firmware: arm_scmi: Remove extra check for invalid length message responses ... Link: https://lore.kernel.org/r/20190814172454.26191-1-sudeep.holla@arm.comSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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Marek Behún authored
This patch adds documentation of the device tree bindings for GPIOs on the devices connected via Moxtet bus. Link: https://lore.kernel.org/r/20190812161118.21476-6-marek.behun@nic.czSigned-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Marek Behún authored
This adds support for interpreting the input and output bits of one device on Moxtet bus as GPIOs. This is needed for example by the SFP cage module of Turris Mox. Link: https://lore.kernel.org/r/20190812161118.21476-5-marek.behun@nic.czSigned-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Marek Behún authored
Add sysfs ABI documentation for the attribute files module_id and module_name Add debugfs ABI documentation for reading input from the shift registers and reading last written output or write output to the shift registers. Link: https://lore.kernel.org/r/20190812161118.21476-4-marek.behun@nic.czSigned-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Marek Behún authored
This adds device tree binding documentation for the Moxtet bus, a bus via which the different modules connected to the Turris Mox router can be configured. Link: https://lore.kernel.org/r/20190812161118.21476-3-marek.behun@nic.czSigned-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Marek Behún authored
On the Turris Mox router different modules can be connected to the main CPU board: currently a module with a SFP cage, a module with MiniPCIe connector, a PCIe pass-through MiniPCIe connector module, a 4-port switch module, an 8-port switch module, and a 4-port USB3 module. For example: [CPU]-[PCIe-pass-through]-[PCIe]-[8-port switch]-[8-port switch]-[SFP] Each of this modules has an input and output shift register, and these are connected via SPI to the CPU board. Via SPI we are able to discover which modules are connected, in which order, and we can also read some information about the modules (eg. their interrupt status), and configure them. From each module 8 bits can be read (of which low 4 bits identify the module) and 8 bits can be written. For example from the module with a SFP cage we can read the LOS, TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and RATE-SELECT signals. This driver creates a new bus type, called "moxtet". For each Mox module it finds via SPI, it creates a new device on the moxtet bus so that drivers can be written for them. It also implements a virtual interrupt controller for the modules which send their interrupt status over the SPI shift register. These modules do this in addition to sending their interrupt status via the shared interrupt line. When the shared interrupt is triggered, we read from the shift register and handle IRQs for all devices which are in interrupt. The topology of how Mox modules are connected can then be read by listing /sys/bus/moxtet/devices. Link: https://lore.kernel.org/r/20190812161118.21476-2-marek.behun@nic.czSigned-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'renesas-drivers-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.4 - Fix a flexible array member definition in the R-Car SYSC driver. * tag 'renesas-drivers-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-sysc: Use [] to denote a flexible array member Link: https://lore.kernel.org/r/20190802120355.1430-3-geert+renesas@glider.beSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 13 Aug, 2019 1 commit
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git://git.pengutronix.de/git/pza/linuxArnd Bergmann authored
Reset controller changes for v5.4 This tag adds support for the i.MX8MM SRC via the reset-imx7 driver and for DesignWare IP reset controllers via the reset-simple driver. A typo in the i.MX8MQ DSI reset definitions is fixed, and the Meson reset driver and binding headers are updated to SPDX license identifiers. * tag 'reset-for-v5.4' of git://git.pengutronix.de/git/pza/linux: reset: Add DesignWare IP support to simple reset dt-bindings: Document the DesignWare IP reset bindings dt-bindings: reset: amlogic,meson8b-reset: update with SPDX Licence identifier dt-bindings: reset: amlogic,meson-gxbb-reset: update with SPDX Licence identifier reset: reset-meson: update with SPDX Licence identifier dt-bindings: reset: Fix typo in imx8mq resets dt-bindings: reset: imx7: Add support for i.MX8MM Link: https://lore.kernel.org/r/1565603668.5017.2.camel@pengutronix.deSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 12 Aug, 2019 20 commits
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Sudeep Holla authored
On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Management Interface(SCMI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. Adds support for the resets provided using SCMI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different ARM SCMI device operations provided by the ARM SCMI framework. Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SCMIv2.0 adds a new Reset Management Protocol to manage various reset states a given device or domain can enter. Device(s) that can be collectively reset through a common reset signal constitute a reset domain for the firmware. A reset domain can be reset autonomously or explicitly through assertion and de-assertion of the signal. When autonomous reset is chosen, the firmware is responsible for taking the necessary steps to reset the domain and to subsequently bring it out of reset. When explicit reset is chosen, the caller has to specifically assert and then de-assert the reset signal by issuing two separate RESET commands. Add the basic SCMI reset infrastructure that can be used by Linux reset controller driver. Reviewed-by:
Peng Fan <peng.fan@nxp.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SCMIv2.0 adds a new Reset Management Protocol to manage various reset states a given device or domain can enter. Extend the existing SCMI bindings to add reset protocol support by re-using the reset bindings for both reset providers and consumers. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SCMI v2.0 adds support for "FastChannel" which do not use a message header as they are specialized for a single message. Only PERFORMANCE_LIMITS_{SET,GET} and PERFORMANCE_LEVEL_{SET,GET} commands are supported over fastchannels. As they are optional, they need to be discovered by PERFORMANCE_DESCRIBE_FASTCHANNEL command. Further {LIMIT,LEVEL}_SET commands can have optional doorbell support. Add support for making use of these fastchannels. Cc: Ionela Voinescu <Ionela.Voinescu@arm.com> Cc: Chris Redpath <Chris.Redpath@arm.com> Cc: Quentin Perret <Quentin.Perret@arm.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional channel that is dedicated to a single SCMI message type for controlling a specific platform resource. They do not use a message header as they are specialized for a single message. Only PERFORMANCE_LIMITS_{SET,GET} and PERFORMANCE_LEVEL_{SET,GET} commands are supported over fastchannels. As they are optional, they need to be discovered by PERFORMANCE_DESCRIBE_FASTCHANNEL command. Further {LIMIT,LEVEL}_SET commands can have optional doorbell support. Add support for discovery of these fastchannels. Cc: Ionela Voinescu <Ionela.Voinescu@arm.com> Cc: Chris Redpath <Chris.Redpath@arm.com> Cc: Quentin Perret <Quentin.Perret@arm.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
Instead of type-casting the {tx,rx}.buf all over the place while accessing them to read/write __le{32,64} from/to the firmware, let's use the existing {get,put}_unaligned_le{32,64} accessors to hide all the type cast ugliness. Suggested-by:
Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
CLOCK_PROTOCOL_ATTRIBUTES provides attributes to indicate the maximum number of pending asynchronous clock rate changes supported by the platform. If it's non-zero, then we should be able to use asynchronous clock rate set for any clocks until the maximum limit is reached. Tracking the current count of pending asynchronous clock set rate requests, we can decide if the incoming/new request for clock set rate can be handled asynchronously or not until the maximum limit is reached. Cc: linux-clk@vger.kernel.org Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
CLOCK_PROTOCOL_ATTRIBUTES provides attributes to indicate the maximum number of pending asynchronous clock rate changes supported by the platform. If it's non-zero, then we should be able to use asynchronous clock rate set for any clocks until the maximum limit is reached. In order to add that support, let's drop the config flag passed to clk_ops->rate_set and handle the asynchronous requests dynamically. Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Acked-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SENSOR_DESCRIPTION_GET provides attributes to indicate if the sensor supports asynchronous read. We can read that flag and use asynchronous reads for any sensors with that attribute set. Let's use the new scmi_do_xfer_with_response to support asynchronous sensor reads. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
SENSOR_DESCRIPTION_GET provides attributes to indicate if the sensor supports asynchronous read. Ideally we should be able to read that flag and use asynchronous reads for any sensors with that attribute set. In order to add that support, let's drop the async flag passed to sensor_ops->reading_get and dynamically switch between sync and async flags based on the attributes as provided by the firmware. Cc: linux-hwmon@vger.kernel.org Acked-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
Messages that are sent to platform, also known as commands and can be: 1. Synchronous commands that block the channel until the requested work has been completed. The platform responds to these commands over the same channel and hence can't be used to send another command until the previous command has completed. 2. Asynchronous commands on the other hand, the platform schedules the requested work to complete later in time and returns almost immediately freeing the channel for new commands. The response indicates the success or failure in the ability to schedule the requested work. When the work has completed, the platform sends an additional delayed response message. Using the same transmit buffer used for sending the asynchronous command even for the delayed response corresponding to it simplifies handling of the delayed response. It's the caller of asynchronous command that is responsible for allocating the completion flag that scmi driver can complete to indicate the arrival of delayed response. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
In order to identify the message type when a response arrives, we need a mechanism to unpack the message header similar to packing. Let's add one. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
Currently we pre-allocate transmit buffers only and use the first free slot in that pre-allocated buffer for transmitting any new message that are generally originated from OS to the platform firmware. Notifications or the delayed responses on the other hand are originated from the platform firmware and consumes by the OS. It's better to have separate and dedicated pre-allocated buffers to handle the notifications. We can still use the transmit buffers for the delayed responses. In addition, let's prepare existing scmi_xfer_{get,put} for acquiring and releasing a slot to identify the right(tx/rx) buffers. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
With scmi_mbox_chan_setup enabled to identify and setup both Tx and Rx, let's consolidate setting up of both the channels under the function scmi_mbox_txrx_setup. Since some platforms may opt not to support notifications or delayed response, they may not need support for Rx. Hence Rx is optional and failure of setting one up is not considered fatal. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
The transmit(Tx) channels are specified as the first entry and the receive(Rx) channels are the second entry as per the device tree bindings. Since we currently just support Tx, index 0 is hardcoded at all required callsites. In order to prepare for adding Rx support, let's remove those hardcoded index and add boolean parameter to identify Tx/Rx channels when setting them up. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
Re-shuffling few functions to keep definitions and their usages close. This is also needed to avoid too many unnecessary forward declarations while adding new features(delayed response and notifications). Keeping this separate to avoid mixing up of these trivial change that doesn't affect functionality into the ones that does. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
Sometimes platfom may take too long to respond to the command and OS might timeout before platform transfer the ownership of the shared memory region to the OS with the response. Since the mailbox channel associated with the channel is freed and new commands are dispatch on the same channel, OS needs to wait until it gets back the ownership. If not, either OS may end up overwriting the platform response for the last command(which is fine as OS timed out that command) or platform might overwrite the payload for the next command with the response for the old. The latter is problematic as platform may end up interpretting the response as the payload. In order to avoid such race, let's wait until the OS gets back the ownership before we prepare the shared memory with the payload for the next command. Reported-by:
Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
In preparation to adding support for other two types of messages that SCMI specification mentions, let's replace the term 'command' with the correct term 'message'. As per the specification the messages are of 3 types: commands(synchronous or asynchronous), delayed responses and notifications. Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
While adding new comments found couple of typos that are better fixed. s/informfation/information/ s/statues/status/ Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
scmi_xfer_get_init ensures both transmit and receive buffer lengths are within the maximum limits. If receive buffer length is not supplied by the caller, it's set to the maximum limit value. Receive buffer length is never modified after that. So there's no need for the extra check when receive transmit completion for a command essage. Further, if the response header length is greater than the prescribed receive buffer length, the response buffer is truncated to the latter. Reported-by:
Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com>
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