- 01 Sep, 2017 2 commits
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Masahiro Yamada authored
Add basic clock data for Socionext's new SoC PXs3. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Leo Yan authored
The old code uses tcxo (19.2MHz) as watchdog clock but actually the watchdog uses 32K clock, as result the watchdog timeout cannot be set correctly and delay long time to reset SoC. So this patch is to use 'ref32k' as clock source for watchdog. Fixes: 72ea4861 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC") Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 31 Aug, 2017 14 commits
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Elaine Zhang authored
The RK808 and RK805 PMICs are using a similar register map. We can reuse the clk driver for the RK805 PMIC. So let's add the RK805 in the Kconfig description. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by:
Joseph Chen <chenjh@rock-chips.com> Signed-off-by:
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Gaku Inami authored
This patch adds the common function to reset the clk rate in order to be able to use it in other cases. Signed-off-by:
Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by:
Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Lucas Stach authored
This propagates rate requests from the display interface to the divider or PLL output, allowing to hit the required display rate in many more cases. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Tested-By:
Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull more Allwinner clock changes from Maxime Ripard: * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework * tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add sun4i/sun7i CCU driver dt-bindings: List devicetree binding for the CCU of Allwinner A10 dt-bindings: List devicetree binding for the CCU of Allwinner A20
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Arnd Bergmann authored
gcc-8 reports an uninitialized variable access in a code path that we would see with incorrect DTB input: drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init': drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized] This works around by skipping invalid input and printing a warning instead if it ever happens. The problem was apparently part of the initiali driver submission, but older compilers don't notice it. Fixes: ab6e23a4 ("clk: sunxi: Add H3 clocks support") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Bhumika Goyal authored
Make this const as it is only stored in the const field of a clk_init_data structure. Signed-off-by:
Bhumika Goyal <bhumirks@gmail.com> Acked-by:
Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by:
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Eugeniy Paltsev authored
HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by:
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by:
Vineet Gupta <vgupta@synopsys.com> Signed-off-by:
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Arvind Yadav authored
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Arvind Yadav authored
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by:
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Kunihiko Hayashi authored
Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by:
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Linus Walleij authored
This bit is pin control, and needs to be carefully managed by the new pin control driver. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcc" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcc non-const clk_ops argument as const. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_sysctrl non-const clk_ops argument as const. Signed-off-by:
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Arvind Yadav authored
clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcmu" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcmu non-const clk_ops argument as const. Signed-off-by:
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- 24 Aug, 2017 3 commits
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Priit Laes authored
Introduce a clock controller driver for sun4i A10 and sun7i A20 series SoCs. Signed-off-by:
Priit Laes <plaes@plaes.org> Signed-off-by:
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Priit Laes authored
Allwinner A10 is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Priit Laes authored
Allwinner A20 is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Acked-by:
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- 23 Aug, 2017 21 commits
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Srinivas Kandagatla authored
This patch adds missing LPASS smmu clks which are required by the audio driver. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Alex Frid authored
- Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by:
Alex Frid <afrid@nvidia.com> Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Thierry Reding <treding@nvidia.com> Acked-by:
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Alex Frid authored
Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by:
Jon Mayo <jmayo@nvidia.com> Tested-by:
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Alex Frid authored
Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by:
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Alex Frid authored
Remove from Tegra210 PLLSS registration code sections that - attempt to set PLL minimum rate (unnecessary, and dangerous if PLL is already enabled on boot) - apply pre-Tegra210 defaults settings - check IDDQ setting (duplicated with Tegra210 PLLSS check defaults) Replaced setting of reference clock with check that default oscillator selection is not changed, and failed registration otherwise as validation was only done with the oscillator as the reference clock. Reordered registration, so that PLL initialization is called after VCOmin adjustment. Signed-off-by:
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Alex Frid authored
Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
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Peter De Schrijver authored
If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by:
Timo Alho <talho@nvidia.com> Tested-by:
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Peter De Schrijver authored
Increase delay after PLL IDDQ release to 5us per PLL specifications. based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
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Alex Frid authored
I2C controllers are also on the APB bus and therefor need this flag to handle resets correctly. Signed-off-by:
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Alex Frid authored
Don't take the fractional part into account to calculate the effective NDIV if fractional ndiv is not enabled. Signed-off-by:
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Peter De Schrijver authored
Not all fields are read from the hw depending on the PLL type. Make sure the other fields are 0 by clearing the structure beforehand to prevent users such as the rate re-calculation code from using bogus values. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by:
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Peter De Schrijver authored
Signed-off-by:
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Peter De Schrijver authored
PLLD2 is used for HDMI which does not allow Spread Spectrum clocking. Signed-off-by:
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Peter De Schrijver authored
Make sure the pll_ss ops are compiled even when only building for Tegra210. Signed-off-by:
Shreshtha Sahu <ssahu@nvidia.com> Tested-by:
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Peter De Schrijver authored
PLL SS was only controlled when setting the PLL rate, not when the PLL itself is enabled or disabled. Signed-off-by:
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Georgi Djakov authored
The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2 ops, which are for RCGs with child branches controlled by different CPUs. The result of the incorrect ops is that the GPU's PM runtime may leave this clock set at a very low rate. Fix this issue by using the correct rcg2 ops. Fixes: a2e8272f ("clk: qcom: Add MSM8916 gpu clocks") Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Bhumika Goyal authored
Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: * Add more module clocks for R-Car V2H and M3-W, * Add support for the R-Car Gen3 USB 2.0 clock selector PHY, * Add support for the new R-Car D3 SoC, * Allow compile-testing of all (sub)drivers now all dummy infrastructure is available, * Small fixes and cleanups. * tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add USB3.0 clock clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY clk: renesas: cpg-mssr: Add R8A77995 support clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 clk: renesas: Add r8a77995 CPG Core Clock Definitions clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table clk: renesas: rcar-gen3-cpg: Drop superfluous variable clk: renesas: Allow compile-testing of all (sub)drivers clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks clk: renesas: div6: Document fields used for parent selection
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Stephen Boyd authored
Silence the sparse warning clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static? Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: -
Stephen Boyd authored
Merge tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: The biggest change is fixing the jitter on the fractional clock-type Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). * tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rv1108 clk_mac sel register description clk: rockchip: rename rv1108 macphy clock to mac clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID clk: rockchip: add rk3228 sclk_sdio_src ID clk: rockchip: add special approximation to fix up fractional clk's jitter clk: fractional-divider: allow overriding of approximation clk: rockchip: modify rk3128 clk driver to also support rk3126 dt-bindings: add documentation for rk3126 clock clk: rockchip: add some critical clocks for rv1108 SoC clk: rockchip: rename some of clks for rv1108 SoC clk: rockchip: fix up some clks describe error for rv1108 SoC clk: rockchip: support more clks for rv1108 clk: rockchip: fix up the pll clks error for rv1108 SoC clk: rockchip: support more rates for rv1108 cpuclk clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock changes from Chen-Yu Tsai: * Added support for fixed post-divider on divider and NKM-style clocks * Added driver for R40 CCU * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo * Make fractional clock modes really used and correctly configured * Make H3 cpu clock rate change correctly to be used with cpufreq * tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: support R40 SoC dt-bindings: add compatible string for Allwinner R40 CCU clk: sunxi-ng: nkm: add support for fixed post-divider clk: sunxi-ng: div: Add support for fixed post-divider dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change clk: sunxi-ng: Wait for lock when using fractional mode clk: sunxi-ng: Make fractional helper less chatty clk: sunxi-ng: multiplier: Fix fractional mode clk: sunxi-ng: Fix fractional mode for N-M clocks clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h
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