- 30 Apr, 2024 40 commits
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Jesse Zhang authored
Check the return of function smum_send_msg_to_smc as it may fail to initialize the variable. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ma Jun authored
Check the return value of smum_send_msg_to_smc, otherwise we might use an uninitialized variable "now" Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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YiPeng Chai authored
Remove redundant function call. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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YiPeng Chai authored
Remove unused code. Signed-off-by:
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Tim Huang authored
Clear overflowed array index read warning by cast operation. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Tim Huang authored
Clear resource leak warning that when the prepare fails, the allocated amdgpu job object will never be released. Signed-off-by:
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Yang Wang authored
because the ue valid mca count will only be cleared after gpu reset, so only dump mca log on the first time to get mca bank after receive RAS interrupt. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yang Wang authored
v1: because SMU CE valid mca bank will be cleared after reading, this patch adds mca cache at the driver level to ensure that the mca bank is not lost. v2: refine amdgpu_mca_init/fini/reset() function name. v3: add mca_cache.lock support only add CE bank to mca bank cache. Signed-off-by:
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Yang Wang authored
- Refine mca driver code. - Centralize mca bank dispatch code logic. Signed-off-by:
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Hawking Zhang authored
Add initial support for MMHUB 4.1.0. v1: Add mmhub v4_1_0 ip block support. v2: Switch to AMDGPU_MMHUB0(0). v3: squash in fix for ip version check (Alex) v4: squash in vm_contexts_disable fix (Alex) Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Philip Yang authored
When TTM failed to alloc VRAM, TTM try evict BOs from VRAM to system memory then retry the allocation, this skips the KFD BOs from the same process because KFD require all BOs are resident for user queues. If TTM with TTM_PL_FLAG_CONTIGUOUS flag to alloc contiguous VRAM, allow TTM evict KFD BOs from the same process, this will evict the user queues first, and restore the queues later after contiguous VRAM allocation. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Philip Yang authored
Define macro AMDGPU_MAX_SG_SEGMENT_SIZE 2GB, because struct scatterlist length is unsigned int, and some users of it cast to a signed int, so every segment of sg table is limited to size 2GB maximum. For contiguous VRAM allocation, don't limit the max buddy block size in order to get contiguous VRAM memory. To workaround the sg table segment size limit, allocate multiple segments if contiguous size is bigger than AMDGPU_MAX_SG_SEGMENT_SIZE. Signed-off-by:
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Sunil Khatri authored
Add function description of the new functions added in amd_ip_funcs. new functions added are: a. dump_ip_state b. print_ip_state Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - Disable seamless boot on 128b/132b encoding - Have cursor and surface updates together - Change ASSR disable sequence to avoid corruption - Fix few IPS problems - Enable Replay for DCN315 - Fix few ODM problems - Fix FEC_READY write timing - Fix few FPO problems - Adjust DML21 gpuvm_enable assignment - Fix divide by 0 error in VM environment - Fix few DCN35 problems - Fix flickering on DCN321 - Fix mst resume problem - Fix multi-disp FAMS problem - Refactor Replay - Update some of the dcn303 parameters - Enable legacy fast update for dcn301 - Add VCO parameter for DCN31 FPU - Fix problems reported by Coverity Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] preOS will not support display mode programming and link training for UHBR rates. [how] If we detect a sink that's UHBR capable, disable seamless boot Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Swapnil Patel authored
[Why] Currently disabling ASSR before stream is disabled causes visible display corruption. [How] Move disable ASSR command to after stream has been disabled. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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Roman Li authored
[Why] HPD interrupt cannot be handled in IPS2 state. So if there's a display topology change while system in IPS2 it can be missed. [How] Implement worker to check each 5 sec in IPS for HPD. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] We can hang in IPS2 checking DMCUB_SCRATCH0 for link detection state. [How] Replace the HW access with a check on the shared state bit. This will work the same way as the SCRATCH0 but won't require a wake in the case where link detection isn't required. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Joan Lee authored
[why & how] Enable Replay for DCN315. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Joan Lee <joan.lee@amd.com> Tested-by:
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Wenjing Liu authored
[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Ilya Bakoulin authored
[Why/How] We can miss writing FEC_READY in some cases before LT start, which violates DP spec. Remove the condition guarding the DPCD write so that the write happens unconditionally. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Alvin Lee authored
[Description] For FPO + Vactive scenarios we must check that all non-FPO pipes have VACTIVE margin to allow it. The previous check only confirmed that there is at least one pipe that has vactive margin, but this is incorrect as the vactive display could be using two pipes (MPO) where the desktop plane has vactive margin, and the video plane does not. Reviewed-by:
Samson Tam <samson.tam@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Nevenko Stupar authored
[Why & How] Currently in DML2.1 gpuvm_enable was hardcoded. Use passed info from DC for DML21 to be in sync with what is used in DC. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Tested-by:
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Alvin Lee authored
[Description] Assign linear_pitch_alignment so we don't cause a divide by 0 error in VM environments Reviewed-by:
Sohaib Nadeem <sohaib.nadeem@amd.com> Acked-by:
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Revalla Hari Krishna authored
[why] cleaning up the code refactor requires hubbub to be in its own component. [how] Move all files under newly created hubbub folder and fix the makefiles. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Revalla Hari Krishna <harikrishna.revalla@amd.com> Tested-by:
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Alvin Lee authored
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by:
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Webb Chen authored
This reverts commit 4d4d3ff1 ("drm/amd/display: Keep VBios pixel rate div setting util next mode set") which causes issue. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Webb Chen <yi-lchen@amd.com> Tested-by:
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Daniel Miess authored
[Why & How] Enable root clock optimization for PHYSYMCLK and only disable it when it's actively being used v2: Fix array-index-out-of-bounds in dcn35_calc_blocks_to_gate Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] FIFO error can occur if we don't trigger a DISPCLK change after touching K1/K2 dividers. For 4k144 eDP + hotplug of USB-C DP display we see FIFO underflow. [How] We have the path to trigger the resync as the workaround in DCN314/DCN32, it just needs to be ported over to DCN35. Reviewed-by:
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Roman Li authored
[Why] IPS stability was fixed in bios. [How] Set disable_ips init flag to DMUB_IPS_ENABLE. Reviewed-by:
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Wenjing Liu authored
[why] DSC slice must be divisible by ODM slice count. [how] If DSC slice count is not a multiple of ODM slice count, increase DSC slice until it is. Otherwise fail to compute DSC configuration. Reviewed-by:
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Leo Ma authored
[Why && How] Screen flickering saw on 4K@60 eDP with high refresh rate external monitor when booting up in DC mode. DC Mode Capping is disabled which caused wrong UCLK being used. Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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Wayne Lin authored
[Why] Like commit ec5fa9fc ("drm/amd/display: Adjust the MST resume flow"), we want to avoid handling mst topology changes before restoring the old state. If we enable DP_UP_REQ_EN before calling drm_atomic_helper_resume(), have changce to handle CSN event first and fire hotplug event before restoring the cached state. [How] Disable mst branch sending up request event before we restoring the cached state. DP_UP_REQ_EN will be set later when we call drm_dp_mst_topology_mgr_resume(). Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[HOW&WHY] In multi-monitor cases the VBLANK stretch that is required to align both monitors may be so large that it may create issues for gaming performance. Use debug value to restrict in-game FAMS support for multi-disp use case. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by:
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Dennis Chan authored
[why] To refine for link off frame count in diagnose tool, the driver show the link off frame count number instead of showing link off frame count level. Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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Rodrigo Siqueira authored
Add code to handle case when quad_part is 0 in gpu_addr_to_uma(). Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Rodrigo Siqueira authored
Set up to enable log color state for multiple DCNs. Acked-by:
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Rodrigo Siqueira authored
This commit just remove some trivial legacy code in some of the DC files. Acked-by:
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Rodrigo Siqueira authored
Adjust to update some of the dcn303 parameters. Acked-by:
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Rodrigo Siqueira authored
Set up to enable legacy fast update. Acked-by:
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