- Fix designware-ep Header Type check (Hou Zhiqiang)

- Use DBI accessors instead of own config accessors (Rob Herring)

- Allow overriding bridge pci_ops (Rob Herring)

- Allow root and child buses to have different pci_ops (Rob Herring)

- Add default dwc pci_ops.map_bus (Rob Herring)

- Use pci_ops for root config space accessors in al, exynos, histb,
  keystone, kirin, meson, tegra (Rob Herring)

- Remove dwc own/other config accessor ops (Rob Herring)

- Use generic config accessors in dwc (Rob Herring)

- Also call .add_bus() callback for root bus (Rob Herring)

- Convert keystone .scan_bus() callback to use pci_ops.add_bus (Rob
  Herring)

- Convert dwc to use pci_host_probe() (Rob Herring)

- Remove dwc root_bus pointer (Rob Herring)

- Remove storing of PCI resources in dwc-specific structs (Rob Herring)

- Simplify config space handling (Rob Herring)

- Drop keystone duplicated DT num-viewport handling (Rob Herring)

- Check CONFIG_PCI_MSI in dw_pcie_msi_init() instead of duplicating it in
  all the drivers (Rob Herring)

- Remove imx6 duplicate PCIE_LINK_WIDTH_SPEED_CONTROL definition (Rob
  Herring)

- Add dwc num_lanes for use when it's lacking from DT (Rob Herring)

- Ensure "Fast Link Mode" simulation environment setting is cleared (Rob
  Herring)

- Drop meson duplicate number of lanes setup (Rob Herring)

- Drop meson unnecessary RC config space init (Rob Herring)

- Rework meson config and dwc port logic register accesses (Rob Herring)

- Use common PCI register definitions in imx6 and qcom (Rob Herring)

- Search for DesignWare PCIe Capability instead of hard-coding its location
  (Rob Herring)

- Use common DesignWare register definitions in tegra (Rob Herring)

- Drop keystone unused DBI2 code (Rob Herring)

- Make dwc ATU accessors private (Rob Herring)

- Centralize link gen setting in dwc (Rob Herring)

- Set PORT_LINK_DLL_LINK_EN in common dwc setup code (Rob Herring)

- Drop intel-gw unnecessary DT 'device_type' checking (Rob Herring)

- Move intel-gw PCI_CAP_ID_EXP discovery to the single place it's used (Rob
  Herring)

- Drop intel-gw unused max_width (Rob Herring)

- Move N_FTS (fast training sequence) setup to common dwc setup (Rob
  Herring)

- Convert spear13xx, tegra194 to use DBI accessors (Rob Herring)

- Add multiple PFs support for DWC (Xiaowei Bao)

- Add MSI-X doorbell mode for endpoint mode (Xiaowei Bao)

- Update MSI/MSI-X capability management for endpoints (Xiaowei Bao)

- Add layerscape ls1088a and ls2088a compatible strings (Xiaowei Bao)

- Update layerscape MSI/MSI-X management (Xiaowei Bao)

- Use doorbell to support MSI-X on layerscape (Xiaowei Bao)

- Add layerscape endpoint mode support for ls1088a and ls2088a (Xiaowei
  Bao)

- Add layerscape ls1088a node to DT (Xiaowei Bao)

- Add Freescale/Layerscape ls1088a to endpoint test (Xiaowei Bao)

- Add endpoint test driver data for Layerscape PCIe controllers (Hou
  Zhiqiang)

- Fix 'cast truncates bits from constant value' warning (Gustavo Pimentel)

- Add uniphier iATU register description (Kunihiko Hayashi)

- Add common iATU register support (Kunihiko Hayashi)

- Remove keystone iATU register mapping in favor of generic dwc support
  (Kunihiko Hayashi)

- Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang)

- Fix MSI page leakage in suspend/resume (Jisheng Zhang)

- Check whether link is up before attempting config access (best-effort fix
  even though it's racy) (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()
  PCI: dwc: Fix MSI page leakage in suspend/resume
  PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled
  PCI: keystone: Remove iATU register mapping
  PCI: dwc: Add common iATU register support
  dt-bindings: PCI: uniphier-ep: Add iATU register description
  dt-bindings: PCI: uniphier: Add iATU register description
  PCI: dwc: Fix 'cast truncates bits from constant value'
  misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers
  misc: pci_endpoint_test: Add LS1088a in pci_device_id table
  PCI: layerscape: Add EP mode support for ls1088a and ls2088a
  PCI: layerscape: Modify the MSIX to the doorbell mode
  PCI: layerscape: Modify the way of getting capability with different PEX
  PCI: layerscape: Fix some format issue of the code
  dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a
  PCI: designware-ep: Modify MSI and MSIX CAP way of finding
  PCI: designware-ep: Move the function of getting MSI capability forward
  PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
  PCI: designware-ep: Add multiple PFs support for DWC
  PCI: dwc: Use DBI accessors
  PCI: dwc: Move N_FTS setup to common setup
  PCI: dwc/intel-gw: Drop unused max_width
  PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
  PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property
  PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
  PCI: dwc: Centralize link gen setting
  PCI: dwc: Make ATU accessors private
  PCI: dwc: Remove read_dbi2 code
  PCI: dwc/tegra: Use common Designware port logic register definitions
  PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
  PCI: dwc/qcom: Use common PCI register definitions
  PCI: dwc/imx6: Use common PCI register definitions
  PCI: dwc/meson: Rework PCI config and DW port logic register accesses
  PCI: dwc/meson: Drop unnecessary RC config space initialization
  PCI: dwc/meson: Drop the duplicate number of lanes setup
  PCI: dwc: Ensure FAST_LINK_MODE is cleared
  PCI: dwc: Add a 'num_lanes' field to struct dw_pcie
  PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL
  PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
  PCI: dwc/keystone: Drop duplicated 'num-viewport'
  PCI: dwc: Simplify config space handling
  PCI: dwc: Remove storing of PCI resources
  PCI: dwc: Remove root_bus pointer
  PCI: dwc: Convert to use pci_host_probe()
  PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus
  PCI: Also call .add_bus() callback for root bus
  PCI: dwc: Use generic config accessors
  PCI: dwc: Remove dwc specific config accessor ops
  PCI: dwc: histb: Use pci_ops for root config space accessors
  PCI: dwc: exynos: Use pci_ops for root config space accessors
  PCI: dwc: kirin: Use pci_ops for root config space accessors
  PCI: dwc: meson: Use pci_ops for root config space accessors
  PCI: dwc: tegra: Use pci_ops for root config space accessors
  PCI: dwc: keystone: Use pci_ops for config space accessors
  PCI: dwc: al: Use pci_ops for child config space accessors
  PCI: dwc: Add a default pci_ops.map_bus for root port
  PCI: dwc: Allow overriding bridge pci_ops
  PCI: dwc: Use DBI accessors instead of own config accessors
  PCI: Allow root and child buses to have different pci_ops
  PCI: designware-ep: Fix the Header Type check

- Remove obsolete path from comment (Flavio Suligoi)

- Simplify cdns_pcie_host_init_address_translation() (Qinglang Miao)

* remotes/lorenzo/pci/cadence:
  PCI: cadence: Simplify cdns_pcie_host_init_address_translation() return expression
  PCI: cadence-ep: Remove obsolete path from comment

- Make PCIE_BRCMSTB depend on and default to ARCH_BRCMSTB (Jim Quinlan)

- Add DT bindings for 7278, 7216, 7211, and new properties (Jim Quinlan)

- Add bcm7278 register info (Jim Quinlan)

- Add suspend and resume pm_ops (Jim Quinlan)

- Add bcm7278 PERST# support (Jim Quinlan)

- Add control of RESCAL reset (Jim Quinlan)

- Set additional internal memory DMA viewport sizes (Jim Quinlan)

- Accommodate MSI for older chips (Jim Quinlan)

- Set bus max burst size by chip type (Jim Quinlan)

- Add bcm7211, bcm7216, bcm7445, bcm7278 to match list (Jim Quinlan)

* remotes/lorenzo/pci/brcmstb:
  PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list
  PCI: brcmstb: Set bus max burst size by chip type
  PCI: brcmstb: Accommodate MSI for older chips
  PCI: brcmstb: Set additional internal memory DMA viewport sizes
  PCI: brcmstb: Add control of rescal reset
  PCI: brcmstb: Add bcm7278 PERST# support
  PCI: brcmstb: Add suspend and resume pm_ops
  PCI: brcmstb: Add bcm7278 register info
  dt-bindings: PCI: Add bindings for more Brcmstb chips
  PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB

- Fix s390 build error (Pali Rohár)

- Check for errors from pci_bridge_emul_init() (Pali Rohár)

- Export pci-bridge-emul functions for use by modules (Pali Rohár)

- Make aardvark driver modular (Pali Rohár)

- Move PCIe reset code to advk_pcie_train_link() (Pali Rohár)

- Convert internal SMCC firmware return codes to errno (Pali Rohár)

- Fix initialization with old Marvell's Arm Trusted Firmware (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Fix initialization with old Marvell's Arm Trusted Firmware
  phy: marvell: comphy: Convert internal SMCC firmware return codes to errno
  PCI: aardvark: Move PCIe reset card code to advk_pcie_train_link()
  PCI: aardvark: Implement driver 'remove' function and allow to build it as module
  PCI: pci-bridge-emul: Export API functions
  PCI: aardvark: Check for errors from pci_bridge_emul_init() call
  PCI: aardvark: Fix compilation on s390

- Remove unused msi_ctrl, io_optional and align_resource fields from ARM
  struct hw_pci (Lorenzo Pieralisi)

* remotes/lorenzo/pci/arm:
  ARM/PCI: Remove unused fields from struct hw_pci

- Remove useless __KERNEL__ preprocessor guard in sparc io_32.h (Lorenzo
  Pieralisi)

- Move ioremap/iounmap declaration so it's visible in asm-generic/io.h
  (Lorenzo Pieralisi)

- Fix memory leak in generic !CONFIG_GENERIC_IOMAP pci_iounmap()
  implementation (Lorenzo Pieralisi)

* remotes/lorenzo/pci/pci-iomap:
  asm-generic/io.h: Fix !CONFIG_GENERIC_IOMAP pci_iounmap() implementation
  sparc32: Move ioremap/iounmap declaration before asm-generic/io.h include
  sparc32: Remove useless io_32.h __KERNEL__ preprocessor guard

- Add ACPI APEI notifier chain for unknown (vendor) CPER records (Shiju
  Jose)

- Add handling of HiSilicon HIP PCIe controller errors (Yicong Yang)

* remotes/lorenzo/pci/apei:
  PCI: hip: Add handling of HiSilicon HIP PCIe controller errors
  ACPI / APEI: Add a notifier chain for unknown (vendor) CPER records

- Remove unnecessary #includes (Gustavo Pimentel)

- Fix intel_mid_pci.c build error when !CONFIG_ACPI (Randy Dunlap)

- Use scnprintf(), not snprintf(), in sysfs "show" functions (Krzysztof
  Wilczyński)

- Simplify pci-pf-stub by using module_pci_driver() (Liu Shixin)

- Print IRQ used by Link Bandwidth Notification (Dongdong Liu)

- Update sysfs mmap-related #ifdef comments (Clint Sbisa)

- Simplify pci_dev_reset_slot_function() (Lukas Wunner)

- Use "NULL" instead of "0" to fix sparse warnings (Gustavo Pimentel)

- Simplify bool comparisons (Krzysztof Wilczyński)

- Drop double zeroing for P2PDMA sg_init_table() (Julia Lawall)

* pci/misc:
  PCI: v3-semi: Remove unneeded break
  PCI/P2PDMA: Drop double zeroing for sg_init_table()
  PCI: Simplify bool comparisons
  PCI: endpoint: Use "NULL" instead of "0" as a NULL pointer
  PCI: Simplify pci_dev_reset_slot_function()
  PCI: Update mmap-related #ifdef comments
  PCI/LINK: Print IRQ number used by port
  PCI/IOV: Simplify pci-pf-stub with module_pci_driver()
  PCI: Use scnprintf(), not snprintf(), in sysfs "show" functions
  x86/PCI: Fix intel_mid_pci.c build error when ACPI is not enabled
  PCI: Remove unnecessary header includes

- Remove unused pcibios_pm_ops (Vaibhav Gupta)

- Rename pci_dev.d3_delay to d3hot_delay (Krzysztof Wilczyński)

- Apply D2 transition delay as microseconds, not milliseconds (Bjorn
  Helgaas)

* pci/pm:
  PCI/PM: Revert "PCI/PM: Apply D2 delay as milliseconds, not microseconds"
  PCI/PM: Remove unused PCI_PM_BUS_WAIT
  PCI/PM: Rename pci_dev.d3_delay to d3hot_delay
  PCI/PM: Remove unused pcibios_pm_ops

- Use for_each_child_of_node() and for_each_node_by_name() instead of
  open-coding them (Qinglang Miao)

- Reduce pciehp noisiness on hot removal (Lukas Wunner)

- Remove unused assignment in shpchp (Krzysztof Wilczyński)

* pci/hotplug:
  PCI: shpchp: Remove unused 'rc' assignment
  PCI: pciehp: Reduce noisiness on hot removal
  PCI: rpadlpar: Use for_each_child_of_node() and for_each_node_by_name()

- Tone down message about missing optional MCFG (Jeremy Linton)

- Add schedule point in pci_read_config() (Jiang Biao)

- Add Ampere Altra SOC MCFG quirk (Tuan Phan)

- Add Kconfig options for MPS/MRRS strategy (Jim Quinlan)

* pci/enumeration:
  PCI: Add Kconfig options for MPS/MRRS strategy
  PCI/ACPI: Add Ampere Altra SOC MCFG quirk
  PCI: Add schedule point in pci_read_config()
  PCI/ACPI: Tone down missing MCFG message

- Remove struct aspm_register_info (Saheed O. Bolarinwa)

- Remove struct pcie_link_state.l1ss (Saheed O. Bolarinwa)

* pci/aspm:
  PCI/ASPM: Remove struct pcie_link_state.l1ss
  PCI/ASPM: Remove struct aspm_register_info.l1ss_cap
  PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_info
  PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl1
  PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl2 (unused)
  PCI/ASPM: Remove struct aspm_register_info.l1ss_cap_ptr
  PCI/ASPM: Remove struct aspm_register_info.latency_encoding
  PCI/ASPM: Remove struct aspm_register_info.enabled
  PCI/ASPM: Remove struct aspm_register_info.support
  PCI/ASPM: Use 'parent' and 'child' for readability
  PCI/ASPM: Move LTR path check to where it's used
  PCI/ASPM: Move pci_clear_and_set_dword() earlier

- Enable Translation Blocking for external devices (Rajat Jain)

* pci/acs:
  PCI/ACS: Enable Translation Blocking for external devices

A break is not needed if it is preceded by a return

Link: https://lore.kernel.org/r/20201019190249.7825-1-trix@redhat.comSigned-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either
programmed or statically configured to forward the error triggered by a
link-down state (eg no connected endpoint device) on the system bus for
PCI configuration transactions; these errors are reported as an SError
at system level, which is fatal.

Enumerating a PCI tree when the PCIe link is down is not sensible
either, so even if the link-up check is racy (link can go down after
map_bus() is called) add a link-up check in map_bus() to prevent issuing
configuration transactions when the link is down.

SError report:

 SError Interrupt on CPU2, code 0xbf000002 -- SError
 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
 Hardware name: LS1046A RDB Board (DT)
 pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--)
 pc : pci_generic_config_read+0x3c/0xe0
 lr : pci_generic_config_read+0x24/0xe0
 sp : ffff80001003b7b0
 x29: ffff80001003b7b0 x28: ffff80001003ba74
 x27: ffff000971d96800 x26: ffff00096e77e0a8
 x25: ffff80001003b874 x24: ffff80001003b924
 x23: 0000000000000004 x22: 0000000000000000
 x21: 0000000000000000 x20: ffff80001003b874
 x19: 0000000000000004 x18: ffffffffffffffff
 x17: 00000000000000c0 x16: fffffe0025981840
 x15: ffffb94c75b69948 x14: 62203a383634203a
 x13: 666e6f635f726568 x12: 202c31203d207265
 x11: 626d756e3e2d7375 x10: 656877202c307830
 x9 : 203d206e66766564 x8 : 0000000000000908
 x7 : 0000000000000908 x6 : ffff800010900000
 x5 : ffff00096e77e080 x4 : 0000000000000000
 x3 : 0000000000000003 x2 : 84fa3440ff7e7000
 x1 : 0000000000000000 x0 : ffff800010034000
 Kernel panic - not syncing: Asynchronous SError Interrupt
 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
 Hardware name: LS1046A RDB Board (DT)
 Call trace:
  dump_backtrace+0x0/0x1c0
  show_stack+0x18/0x28
  dump_stack+0xd8/0x134
  panic+0x180/0x398
  add_taint+0x0/0xb0
  arm64_serror_panic+0x78/0x88
  do_serror+0x68/0x180
  el1_error+0x84/0x100
  pci_generic_config_read+0x3c/0xe0
  dw_pcie_rd_other_conf+0x78/0x110
  pci_bus_read_config_dword+0x88/0xe8
  pci_bus_generic_read_dev_vendor_id+0x30/0x1b0
  pci_bus_read_dev_vendor_id+0x4c/0x78
  pci_scan_single_device+0x80/0x100

Link: https://lore.kernel.org/r/20200916054130.8685-1-Zhiqiang.Hou@nxp.comSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[lorenzo.pieralisi@arm.com: rewrote the commit log, remove Fixes tag]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Previously we computed L1.2 parameters in the enumeration path, saved them
in struct pcie_link_state.l1ss, and programmed them into the devices
whenever we enabled or disabled L1.2 on the link.  But these parameters are
constant and don't need to be updated when enabling/disabling L1.2.

Compute and program the L1.2 parameters once during enumeration and remove
the struct pcie_link_state.l1ss member.  No functional change intended.

[bhelgaas: rework to program L1.2 parameters during enumeration]
Link: https://lore.kernel.org/r/20201015193039.12585-13-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously we stored the L1SS Capabilities value in the struct
aspm_register_info.

We only need this information in one place, so read it there and remove
struct aspm_register_info completely, since it's now empty.  No functional
change intended.

[bhelgaas: split up, don't cache l1ss_cap in pci_dev]
Link: https://lore.kernel.org/r/20201015193039.12585-12-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

aspm_calc_l1ss_info() needs only the L1SS Capabilities.  It doesn't need
anything else from struct aspm_register_info, so pass only the Capabilities
value.  No functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-11-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously we stored the L1SS Control 1 register in the struct
aspm_register_info.

We only need this information in one place, so read it there and remove it
from struct aspm_register_info.  No functional change intended.

[bhelgaas: split ctl1/ctl2]
Link: https://lore.kernel.org/r/20201015193039.12585-10-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

We never use the aspm_register_info.l1ss_ctl2 value, so remove it.  No
functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-9-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

Save the L1 Substates Capability pointer in struct pci_dev.  Then we don't
have to keep track of it in the struct aspm_register_info and struct
pcie_link_state, which makes the code easier to read.  No functional change
intended.

[bhelgaas: split to a separate patch]
Link: https://lore.kernel.org/r/20201015193039.12585-8-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously we stored L0s and L1 Exit Latency information from the Link
Capabilities register in the struct aspm_register_info.

We only need these latencies when we already have the Link Capabilities
values, so use those directly and remove the latencies from struct
aspm_register_info.  No functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-7-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously we stored the "ASPM Control" bits from the Link Control register
in the struct aspm_register_info.

Read PCI_EXP_LNKCTL directly when needed.  This means we can use the
PCI_EXP_LNKCTL_ASPM_* bits directly instead of the similar but different
PCIE_LINK_STATE_* bits.  No functional change intended.

[bhelgaas: drop get_aspm_enable() and read LNKCTL once directly]
Link: https://lore.kernel.org/r/20201015193039.12585-6-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously we stored the "ASPM Support" field from the Link Capabilities
register in the struct aspm_register_info.

Read the Link Capabilities directly when needed and remove it from the
struct aspm_register_info.  No functional change intended.

[bhelgaas: remove pci_dev cached copy since LNKCAP isn't truly read-only,
add PCI_EXP_LNKCAP_ASPM_L0S & PCI_EXP_LNKCAP_ASPM_L1, check them directly
instead of adding aspm_support()]
Link: https://lore.kernel.org/r/20201015193039.12585-5-helgaas@kernel.orgSigned-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Other users of link->pdev and link->downstream, e.g., pcie_aspm_cap_init(),
pcie_config_aspm_l1ss(), and pcie_config_aspm_link(), use "parent" and
"child" as local names.

Do the same in aspm_calc_l1ss_info() for readability.  No functional change
intended.

Link: https://lore.kernel.org/r/20201015193039.12585-4-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

pcie_get_aspm_reg() mostly reads ASPM-related registers, but in some cases
it also updates the value read from PCI_L1SS_CAP based on LTR properties.

Move this update to the point where the value is used to make the code more
readable.

No functional change intended, although previously we could clear
PCI_L1SS_CAP_ASPM_L1_2 for both ends of the link, and now we'll only do it
for the downstream end of a link.  This shouldn't matter because we always
test that bit by ANDing l1ss_cap for the upstream and downstream ends.

Link: https://lore.kernel.org/r/20201015193039.12585-3-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

Move pci_clear_and_set_dword() earlier in file to prepare for future patch.
No functional change intended.

Link: https://lore.kernel.org/r/20201015193039.12585-2-helgaas@kernel.orgSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>

Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during suspend-to-RAM, so when we resume, we want to
redo the latter but not the former. If designware based driver (for
example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the
msi page will be leaked.

As pointed out by Rob and Ard, there's no need to allocate a page for
the MSI address, we could use an address in the driver data.

To avoid map the MSI msg again during resume, we move the map MSI msg
from dw_pcie_msi_init() to dw_pcie_host_init().
Suggested-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201009155505.5a580ef5@xhacker.debianSigned-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK
and PCIE_MSI_INTR0_ENABLE registers.

Link: https://lore.kernel.org/r/20201009155436.27e67238@xhacker.debianSigned-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Suggested-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1601444167-11316-5-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iATU register area is
separated from core register area, this area is necessary to get from
DT independently.
Suggested-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>

In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsis DWC version 4.80 or later.

Link: https://lore.kernel.org/r/1601444167-11316-3-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

In the dt-bindings, "atu" reg-names is required to get the register space
for iATU in Synopsys DWC version 4.80 or later.

Link: https://lore.kernel.org/r/1601444167-11316-2-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>

For arches that do not select CONFIG_GENERIC_IOMAP, the current
pci_iounmap() function does nothing causing obvious memory leaks
for mapped regions that are backed by MMIO physical space.

In order to detect if a mapped pointer is IO vs MMIO, a check must made
available to the pci_iounmap() function so that it can actually detect
whether the pointer has to be unmapped.

In configurations where CONFIG_HAS_IOPORT_MAP && !CONFIG_GENERIC_IOMAP,
a mapped port is detected using an ioport_map() stub defined in
asm-generic/io.h.

Use the same logic to implement a stub (ie __pci_ioport_unmap()) that
detects if the passed in pointer in pci_iounmap() is IO vs MMIO to
iounmap conditionally and call it in pci_iounmap() fixing the issue.

Leave __pci_ioport_unmap() as a NOP for all other config options.
Tested-by: George Cherian <george.cherian@marvell.com>
Link: https://lore.kernel.org/lkml/20200905024811.74701-1-yangyingliang@huawei.com
Link: https://lore.kernel.org/lkml/20200824132046.3114383-1-george.cherian@marvell.com
Link: https://lore.kernel.org/r/a9daf8d8444d0ebd00bc6d64e336ec49dbb50784.1600254147.git.lorenzo.pieralisi@arm.comReported-by: George Cherian <george.cherian@marvell.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: George Cherian <george.cherian@marvell.com>
Cc: Will Deacon <will@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Yang Yingliang <yangyingliang@huawei.com>

Move the ioremap/iounmap declaration before asm-generic/io.h is
included so that it is visible within it.

Link: https://lore.kernel.org/r/93e2f23cda474a92a4708d4c50c9c359426a2162.1600254147.git.lorenzo.pieralisi@arm.comSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: "David S. Miller" <davem@davemloft.net>
Cc: "David S. Miller" <davem@davemloft.net>

The __KERNEL_ preprocessor guard is useless in non-uapi headers.

Remove it.

Link: https://lore.kernel.org/r/084753d3064fe946ff1963eda2eb425cfd7daa7b.1600254147.git.lorenzo.pieralisi@arm.comSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: David S. Miller <davem@davemloft.net>

Old ATF automatically power on pcie phy and does not provide SMC call for
phy power on functionality which leads to aardvark initialization failure:

[    0.330134] mvebu-a3700-comphy d0018300.phy: unsupported SMC call, try updating your firmware
[    0.338846] phy phy-d0018300.phy.1: phy poweron failed --> -95
[    0.344753] advk-pcie d0070000.pcie: Failed to initialize PHY (-95)
[    0.351160] advk-pcie: probe of d0070000.pcie failed with error -95

This patch fixes above failure by ignoring 'not supported' error in
aardvark driver. In this case it is expected that phy is already power on.
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Link: https://lore.kernel.org/r/20200902144344.16684-3-pali@kernel.org
Fixes: 36669701 ("PCI: aardvark: Add PHY support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f1: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno

Driver ->power_on and ->power_off callbacks leaks internal SMCC firmware
return codes to phy caller. This patch converts SMCC error codes to
standard linux errno codes. Include file linux/arm-smccc.h already provides
defines for SMCC error codes, so use them instead of custom driver defines.
Note that return value is signed 32bit, but stored in unsigned long type
with zero padding.
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Link: https://lore.kernel.org/r/20200902144344.16684-2-pali@kernel.orgSigned-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

Simplify the return expression.

Link: https://lore.kernel.org/r/20200921131053.92752-1-miaoqinglang@huawei.comSigned-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.

Link: https://lore.kernel.org/r/20200911175232.19016-11-james.quinlan@broadcom.comSigned-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>