Merge tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "Rockchip dts64 updates (using arm/arm64 symlinks) for 4.12 part1" from Heiko Stübner

Rockchip dts changes based on the newly created arm/arm64 symlinks.
The core addition is the support for the rk3399-based Gru family of
ChromeOS devices, like the Kevin board which is the recently released
Samsung Chromebook Plus. Additionally the usb3 controllers are added
to rk3399 as they're used on Gru devices and even without full type-c
support they can at least drive usb2 devices already.

* tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add regulator info for Kevin digitizer
  arm64: dts: rockchip: describe Gru/Kevin OPPs + CPU regulators
  arm64: dts: rockchip: add Gru/Kevin DTS
  dt-bindings: Document rk3399 Gru/Kevin
  arm64: dts: rockchip: support dwc3 USB for rk3399

Merge tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "Rockchip dts64 updates for 4.12 part1" from Heiko Stübner:

Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that
do not match the hardware's capabilities, as well as some general rk3399
pcie fixes as well as also the mmc resets.

* tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: fix PCIe domain number for rk3399
  arm64: dts: rockchip: add rk3399 dw-mmc resets
  arm64: dts: rockchip: add rk3368 dw-mmc resets
  arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default
  arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
  arm64: dts: rockchip: add dmac nodes for rk3368 SoCs
  arm64: dts: rockchip: remove wrongly added idle states on rk3368
  arm64: dts: rockchip: sort rk3399-pcie by unit address

Pull "Broadcom devicetree-arm64 changes for 4.12" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs Device Tree updates for
4.12, please pull the following:

- Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
  Device Tree nodes

- Jon replaces all occurences of: status = "ok" with status = "okay" to better
  conform to the Device Tree specification

* tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: convert "ok" to "okay"
  arm64: dts: NS2: Add Broadcom SPU driver DT entry

Pull "mvebu dt64 for 4.12 (part 1)" from Gregory CLEMENT:

- Add RTC support on Armada 7k/8k
- Improve i2c support on Armada 37xx
- Add gpio expander and RTC on Armada 3720 board
- Improve USB3 support on Armada 37xx
- Add network support on Armada 7k/8k

* tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
  ARM64: dts: marvell: armada-3720 add RTC support
  ARM64: dts: marvell: armada-3720-db: Add phy for USB3
  ARM64: dts: marvell: armada-37xx: Add clock resource for USB3
  ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3
  ARM64: dts: marvell: armada-3720-db: add gpio expander
  ARM64: dts: marvell: armada37xx: add address and size property for i2c cells
  arm64: dts: marvell: add RTC description for Armada 7K/8K

Merge tag 'uniphier-dt64-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64

Pull "UniPhier ARM64 SoC DT updates for v4.12" from Masahiro Yamada:

- Fix W=* build warnings
- Add pinctrl properties to eMMC nodes
- Fix resets properties of USB nodes

* tag 'uniphier-dt64-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  arm64: dts: uniphier: re-order reset deassertion of USB of LD11
  arm64: dts: uniphier: add pinctrl property to eMMC node for LD11/LD20
  arm64: dts: uniphier: move memory node below aliases node
  arm64: dts: uniphier: fix no unit name warnings

Move and update device tree files as part of transition from Broadcom
Vulcan to Cavium ThunderX2.

The changes are to:
 * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi,
   update cpu cores to be "cavium,thunder2", and update SoC to be
   "cavium,thunderx2-cn9900"
 * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi
   and update board name string
 * Update dts/broadcom/Makefile not to build vulcan dtbs
 * Update dts/cavium/Makefile to build thunder2 dtbs

No changes to the dts contents except the updated "compatible" and
"model" properties.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This
SoC will use "cavium,thunderx2-cn9900" as the compatible property.

Also add a documentation entry for the "cavium,thunder2" cpu core
present in these SoCs.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The Armada 3720 DB board has an RTC on the I2C bus. It's a PT7C4337A from
Pericom but which claims to be fully compatible with the ds1337.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Now that the gpio expander is present in the dts, use it to add an USB3
PHY using one of these gpio as a regulator.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Now that clocks are available provide a clock resource for xhci node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

IRQ number for xhci controller was wrong, fix it.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

We need to enable this regulator before the digitizer can be used. Wacom
recommended waiting for 100 ms before talking to the HID.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[store chip ident as comment until i2c multi-compatibles are sorted]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

It's suggested to fix the domain number for all PCIe
host bridges or not set it at all. However, if we don't
fix it, the domain number will keep increasing ever when
doing unbind/bind test, which makes the bus tree of lspci
introduce pointless domain hierarchy. More investigation shows
the domain number allocater of PCI doesn't consider the conflict
of domain number if we have more than one PCIe port belonging to
different domains. So once unbinding/binding one of them and keep
others would going to overflow the domain number so that finally
it will share the same domain as others, but actually it shouldn't.
We should fix the domain number for PCIe or invent new indexing
ID mechanisms. However it isn't worth inventing new indexing ID
mechanisms personlly, Just look at how other Root Complex drivers
did, for instance, broadcom and qualcomm, it seems fixing the domain
number was more popular. So this patch gonna fix the domain number
of PCIe for rk3399.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3399.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

dw-mmc got its reset-properties specified, so add the softresets
for it on the rk3368.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

Default to disable mailbox in rk3368 core dts file.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add dmac bus and dmac peri dts nodes for peripherals,
such as I2S, SPI, UART and so on.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

As reported by Lorenzo, the residency/latency values defined in the
idle-state for rk3368 "make no sense". When introducing them I
simply took the idle-state node from the vendor kernel in error
as I didn't look up if these values were sane in the first place.

Talking to people and determining why they were used in this way
showed that it was meant to make sure the cpu_suspend callback
got initialized which at the 3.10 time was somehow required even
for wfi-based idle handling.

Of course the generic arch_cpu_idle() now does wfi-based idle-handling
already and the rk3368 does not implement any other idle states than
the default WFI, so these wrong idle-states should go away.
Reported-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Used for Gru/Kevin only, as they're the only ones which have a described
CPU regulator. Also, I'm not sure we've validated this table non-Gru
boards.

At the same time, partially describe PWM regulators for Gru, so cpufreq
doesn't think it can crank up the clock speed without changing the
voltage. However, we don't yet have the DT bindings to fully describe
the Over Voltage Protection (OVP) circuits on these boards. Without that
description, we might end up changing the voltage too much, too fast.

Add the pwm-regulator descriptions and associate the CPU OPPs, but leave
them disabled.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[shared gru/kevin parts on a gru device]
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[with a bit of reordering]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Kevin is part of a family of boards called Gru. As best as possible, the
properties shared by the Gru family are placed in rk3399-gru.dtsi, while
Kevin-specific bits are in rk3399-gru-kevin.dts. This does not add full
support for the base Gru board.

Working and tested (to some extent):
 * EC support -- including keyboard, battery, PWM, and probably more
 * UART / console
 * Thermal
 * Touchscreen
 * Touchpad
 * Digitizer (regulator still WIP)
 * PCIe / Wifi
 * Bluetooth / Webcam
 * SD card
 * eMMC
 * USB2 on TypeC
   - This works much of the time, but USB3 devices may or may not detect
     properly. Waiting on proper extcon support for USB3 over TypeC.
   - Depends on XHCI/DWC3 fixes for ARM64 that still haven't landed
 * Backlight

Not working:
 * CPUFreq -- relies on special OVP support for our PWM regulator
   circuits
 * EC / extcon support -- and with it, USB3/TypeC/DP
 * DRM -- won't even build on ARM64, so all display, eDP, etc. is not
   enabled

Not tested:
 * Audio
Signed-off-by: Brian Norris <briannorris@chromium.org>
[shared gru/kevin parts on a gru device]
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[with a bit of reordering]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Gru is a base dev board for a family of devices, including Kevin. Both
utilize Rockchip RK3399, and they share much of their design.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
[added Samsung Chromebook Plus hint]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the dwc3 usb needed node information for rk3399.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Merge tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.12

Cleanup:
* Drop superfluous status update for frequency override from all
  r8a779[56] boards
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs

Enhancements:
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
* Add Cortex-A53 CPU cores to r8a7795 SoC
* Update memory node to 4 GiB map on h3ulcb board
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
* Set drive-strength for ravb pins for r8a7795/salvator-x board
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
* Enable I2C for DVFS device r8a779[56]/salvator-x boards

* tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
  arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override
  arm64: dts: m3ulcb: Drop superfluous status update for frequency override
  arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides
  arm64: dts: h3ulcb: Drop superfluous status update for frequency override
  arm64: dts: r8a7796: Add Cortex-A53 PMU node
  arm64: dts: r8a7796: Add Cortex-A53 CPU cores
  arm64: dts: r8a7796: Add CA53 L2 cache-controller node
  arm64: dts: r8a7796: Add Cortex-A57 PMU node
  arm64: dts: r8a7796: Add Cortex-A57 CPU cores
  arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC
  arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins
  arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
  arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
  arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM
  arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM
  arm64: dts: r8a7795: Add Cortex-A53 PMU node
  arm64: dts: r8a7795: Add Cortex-A53 CPU cores
  arm64: dts: r8a7796: Enable HSCIF DMA
  arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1)
  arm64: dts: r8a7796: Enable SCIF DMA
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

* shared/dt-symlinks:
  arm64: dts: add arm/arm64 include symlinks
  ARM: dts: add arm/arm64 include symlinks
Signed-off-by: Olof Johansson <olof@lixom.net>

Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
    #include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>

Allow including of dtsi files in an architecture-independent manner.
Some dtsi files may be shared between architectures and one suggestion
was to have symlinks and let these includes get accessed via a
    #include <arm64/foo.dtsi>
So add the necessary symlinks for arm32.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>

Per e-mail from Sergei Shtylyov, the DT spec dictates it should be
"okay" (although "ok" is also recognized).  Thus, changing all "ok" to
"okay" in NS2 device tree files
Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The scif_clk device node is already enabled in r8a7796.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The scif_clk and pcie_bus_clk device nodes are already enabled in
r8a7795.dtsi, so there is no need to update their statuses again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

The scif_clk device node is already enabled in r8a7795.dtsi, so there is
no need to update its status again.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Pull s390 fixes from Martin Schwidefsky:

 - four patches to get the new cputime code in shape for s390

 - add the new statx system call

 - a few bug fixes

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
  s390: wire up statx system call
  KVM: s390: Fix guest migration for huge guests resulting in panic
  s390/ipl: always use load normal for CCW-type re-IPL
  s390/timex: micro optimization for tod_to_ns
  s390/cputime: provide archicture specific cputime_to_nsecs
  s390/cputime: reset all accounting fields on fork
  s390/cputime: remove last traces of cputime_t
  s390: fix in-kernel program checks
  s390/crypt: fix missing unlock in ctr_paes_crypt on error path

Pull x86 fixes from Thomas Gleixner:

 - a fix for the kexec/purgatory regression which was introduced in the
   merge window via an innocent sparse fix. We could have reverted that
   commit, but on deeper inspection it turned out that the whole
   machinery is neither documented nor robust. So a proper cleanup was
   done instead

 - the fix for the TLB flush issue which was discovered recently

 - a simple typo fix for a reboot quirk

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/tlb: Fix tlb flushing when lguest clears PGE
  kexec, x86/purgatory: Unbreak it and clean it up
  x86/reboot/quirks: Fix typo in ASUS EeeBook X205TA reboot quirk

Pull irq fixes from Thomas Gleixner:

 - a workaround for a GIC erratum

 - a missing stub function for CONFIG_IRQDOMAIN=n

 - fixes for a couple of type inconsistencies

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/crossbar: Fix incorrect type of register size
  irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065
  irqdomain: Add empty irq_domain_check_msi_remap
  irqchip/crossbar: Fix incorrect type of local variables

Deassert the bit in the System Control block before the MIO block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Fengguang reported random corruptions from various locations on x86-32
after commits d2852a22 ("arch: add ARCH_HAS_SET_MEMORY config") and
9d876e79 ("bpf: fix unlocking of jited image when module ronx not set")
that uses the former. While x86-32 doesn't have a JIT like x86_64, the
bpf_prog_lock_ro() and bpf_prog_unlock_ro() got enabled due to
ARCH_HAS_SET_MEMORY, whereas Fengguang's test kernel doesn't have module
support built in and therefore never had the DEBUG_SET_MODULE_RONX setting
enabled.

After investigating the crashes further, it turned out that using
set_memory_ro() and set_memory_rw() didn't have the desired effect, for
example, setting the pages as read-only on x86-32 would still let
probe_kernel_write() succeed without error. This behavior would manifest
itself in situations where the vmalloc'ed buffer was accessed prior to
set_memory_*() such as in case of bpf_prog_alloc(). In cases where it
wasn't, the page attribute changes seemed to have taken effect, leading to
the conclusion that a TLB invalidate didn't happen. Moreover, it turned out
that this issue reproduced with qemu in "-cpu kvm64" mode, but not for
"-cpu host". When the issue occurs, change_page_attr_set_clr() did trigger
a TLB flush as expected via __flush_tlb_all() through cpa_flush_range(),
though.

There are 3 variants for issuing a TLB flush: invpcid_flush_all() (depends
on CPU feature bits X86_FEATURE_INVPCID, X86_FEATURE_PGE), cr4 based flush
(depends on X86_FEATURE_PGE), and cr3 based flush.  For "-cpu host" case in
my setup, the flush used invpcid_flush_all() variant, whereas for "-cpu
kvm64", the flush was cr4 based. Switching the kvm64 case to cr3 manually
worked fine, and further investigating the cr4 one turned out that
X86_CR4_PGE bit was not set in cr4 register, meaning the
__native_flush_tlb_global_irq_disabled() wrote cr4 twice with the same
value instead of clearing X86_CR4_PGE in the first write to trigger the
flush.

It turned out that X86_CR4_PGE was cleared from cr4 during init from
lguest_arch_host_init() via adjust_pge(). The X86_FEATURE_PGE bit is also
cleared from there due to concerns of using PGE in guest kernel that can
lead to hard to trace bugs (see bff672e6 ("lguest: documentation V:
Host") in init()). The CPU feature bits are cleared in dynamic
boot_cpu_data, but they never propagated to __flush_tlb_all() as it uses
static_cpu_has() instead of boot_cpu_has() for testing which variant of TLB
flushing to use, meaning they still used the old setting of the host
kernel.

Clearing via setup_clear_cpu_cap(X86_FEATURE_PGE) so this would propagate
to static_cpu_has() checks is too late at this point as sections have been
patched already, so for now, it seems reasonable to switch back to
boot_cpu_has(X86_FEATURE_PGE) as it was prior to commit c109bf95
("x86/cpufeature: Remove cpu_has_pge"). This lets the TLB flush trigger via
cr3 as originally intended, properly makes the new page attributes visible
and thus fixes the crashes seen by Fengguang.

Fixes: c109bf95 ("x86/cpufeature: Remove cpu_has_pge")
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Cc: bp@suse.de
Cc: Kees Cook <keescook@chromium.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: netdev@vger.kernel.org
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: lkp@01.org
Cc: Laura Abbott <labbott@redhat.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernrl.org/r/20170301125426.l4nf65rx4wahohyl@wfg-t540p.sh.intel.com
Link: http://lkml.kernel.org/r/25c41ad9eca164be4db9ad84f768965b7eb19d9e.1489191673.git.daniel@iogearbox.netSigned-off-by: Thomas Gleixner <tglx@linutronix.de>

Pull KVM fixes from Radim Krčmář:
 "ARM updates from Marc Zyngier:
   - vgic updates:
     - Honour disabling the ITS
     - Don't deadlock when deactivating own interrupts via MMIO
     - Correctly expose the lact of IRQ/FIQ bypass on GICv3

   - I/O virtualization:
     - Make KVM_CAP_NR_MEMSLOTS big enough for large guests with many
       PCIe devices

   - General bug fixes:
     - Gracefully handle exception generated with syndroms that the host
       doesn't understand
     - Properly invalidate TLBs on VHE systems

  x86:
   - improvements in emulation of VMCLEAR, VMX MSR bitmaps, and VCPU
     reset

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: nVMX: do not warn when MSR bitmap address is not backed
  KVM: arm64: Increase number of user memslots to 512
  KVM: arm/arm64: Remove KVM_PRIVATE_MEM_SLOTS definition that are unused
  KVM: arm/arm64: Enable KVM_CAP_NR_MEMSLOTS on arm/arm64
  KVM: Add documentation for KVM_CAP_NR_MEMSLOTS
  KVM: arm/arm64: VGIC: Fix command handling while ITS being disabled
  arm64: KVM: Survive unknown traps from guests
  arm: KVM: Survive unknown traps from guests
  KVM: arm/arm64: Let vcpu thread modify its own active state
  KVM: nVMX: reset nested_run_pending if the vCPU is going to be reset
  kvm: nVMX: VMCLEAR should not cause the vCPU to shut down
  KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass
  arm64: KVM: VHE: Clear HCR_TGE when invalidating guest TLBs