* pci/host-layerscape:
  PCI: layerscape: Add support for ls1088a
  PCI: layerscape: Add support for ls2088a
  PCI: artpec6: Stop enabling writes to DBI read-only registers
  PCI: layerscape: Remove unnecessary class code fixup
  PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates
  PCI: dwc: Add accessors for write permission of DBI read-only registers
  PCI: layerscape: Disable outbound windows configured by bootloader
  PCI: layerscape: Refactor ls1021_pcie_host_init()
  PCI: layerscape: Move generic init functions earlier in file
  PCI: layerscape: Add class code and multifunction fixups for ls1021a
  PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket
  PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()

* pci/host-kirin:
  PCI: kirin: Constify dw_pcie_host_ops structure

* pci/host-keystone:
  PCI: keystone: Use PCI_NUM_INTX
  PCI: keystone: Remove duplicate MAX_*_IRQS defs
  PCI: keystone-dw: Remove unused ks_pcie, pci variables

* pci/host-iproc:
  PCI: iproc: Clean up whitespace
  PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP
  PCI: iproc: Add 500ms delay during device shutdown
  PCI: iproc: Work around Stingray CRS defects
  PCI: iproc: Factor out memory-mapped config access address calculation
  PCI: iproc: Remove unused struct iproc_pcie *pcie

* pci/host-imx6:
  PCI: imx6: Explicitly request exclusive reset control

* pci/host-hv:
  PCI: hv: Do not sleep in compose_msi_msg()

* pci/host-hisi:
  PCI: hisi: Constify dw_pcie_host_ops structure
  PCI: hisi: Remove unused variable driver

* pci/host-faraday:
  PCI: faraday: Use PCI_NUM_INTX
  PCI: faraday: Fix of_irq_get() error check

* pci/host-exynos:
  PCI: exynos: Fix platform_get_irq() error handling

* pci/host-dra7xx:
  PCI: dra7xx: Fix platform_get_irq() error handling
  PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe()
  PCI: dra7xx: Use PCI_NUM_INTX

* pci/host-designware:
  PCI: dwc: Clear MSI interrupt status after it is handled, not before
  PCI: qcom: Allow ->post_init() to fail
  PCI: qcom: Don't unroll init if ->init() fails
  PCI: dwc: designware: Handle ->host_init() failures
  PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically
  PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static

* pci/host-artpec6:
  PCI: artpec6: Fix platform_get_irq() error handling

* pci/host-armada:
  PCI: armada8k: Fix platform_get_irq() error handling
  PCI: armada8k: Check the return value from clk_prepare_enable()

* pci/host-altera:
  PCI: altera: Fix platform_get_irq() error handling
  PCI: altera: Use size=4 IRQ domain for legacy INTx
  PCI: altera: Remove unused num_of_vectors variable

* pci/host-aardvark:
  PCI: aardvark: Use PCI_NUM_INTX

* pci/irq-intx:
  PCI: Add pci_irqd_intx_xlate()
  PCI: Move enum pci_interrupt_pin to linux/pci.h

platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ley Foon Tan <lftan@altera.com>

platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Niklas Cassel <niklas.cassel@axis.com>

platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Reported-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>

Use tabs (not spaces) for indentation.  No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

PCI_EXP_CAP is an iProc-specific value, so rename it to IPROC_PCI_EXP_CAP
to make it obvious that it's not related to the generic values like
PCI_EXP_RTCTL, etc.  No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the
LCPLL clock and PERST both go off simultaneously.  This seems in accordance
with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the
clock goes inactive after PERST# goes active, but doesn't specify how long
the clock should be valid after PERST#.

However, we have observed that with the iProc Stingray, some Intel NVMe
endpoints, e.g., the P3700 400GB series, are not detected correctly upon
the next boot sequence unless the clock remains valid for some time after
PERST# is asserted.

Delay 500ms after asserting PERST# before performing a reboot.  The 500ms
is experimentally determined.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown()
export from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>

Add support for ls1088a.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>

The ls2088a PCIe controller's register addresses are different from
ls2080a, so add a match entry to identify ls2088a PCIe.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>

Previously we enabled writes to the DBI read-only registers so the Class
Code fix in dw_pcie_setup_rc() would work.  But now dw_pcie_setup_rc()
enables write permission itself, so we don't need to do it here.

Stop enabling writes to the DBI read-only registers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup
from the Layerscape driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.

Enable write permission before updating the Class Code and Interrupt
Pin.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.

Add accessors to enable and disable write permission, and use them instead
of accessing MISC_CONTROL_1_OFF directly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Disable all the outbound windows to avoid one transaction hitting multiple
outbound windows.  dw_pcie_setup_rc() will reconfigure the outbound
windows, which may conflict with windows configured by the bootloader.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

ls1021_pcie_host_init() duplicated the code in the generic
ls_pcie_host_init().  Call ls_pcie_host_init() instead of duplicating the
code.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from
device-specific routines.  Move the generic functions earlier in the file
so we won't need forward declarations.  This is strictly a code move with
no functional change intended.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

The current code depends on class code and multifunction fixups done by the
bootloader.  Perform these fixups in ls1021_pcie_host_init() to remove this
dependency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

The STRFMR1 is not a DBI read-only register, so move it out from the
write-enable bracket.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

We called dw_pcie_setup_rc() from the ls1021a host init function, but not
from the common ls_pcie_host_init() function, so platforms other than
ls1021a still depended on initialization by the bootloader.

Call dw_pcie_setup_rc() from ls_pcie_host_init() to reduce dependencies on
the bootloader.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>

Configuration Request Retry Status ("CRS") completions are a required part
of PCIe.  A PCIe device may respond to config a request with a CRS
completion to indicate that it needs more time to initialize.  A Root Port
that receives a CRS completion may automatically retry the request, or it
may treat the request as a failed transaction.  For a failed read, it will
likely synthesize all 1's data, i.e., 0xffffffff, to complete the read to
the CPU.

CRS Software Visibility ("CRS SV") is an optional feature.  Per PCIe r3.1,
sec 2.3.2, if supported and enabled, a Root Port that receives a CRS
completion for a config read of the Vendor ID will synthesize 0x0001 data
(an invalid Vendor ID) instead of retrying or failing the transaction.  The
0x0001 data makes the CRS completion visible to software, so it can perform
other tasks while waiting for the device.

The iProc "Stingray" PCIe controller does not support CRS completions
correctly.  From the Stingray PCIe Controller spec:

  4.7.3.3. Retry Status On Configuration Cycle

  Endpoints are allowed to generate retry status on configuration cycles.
  In this case, the RC needs to re-issue the request. The IP does not
  handle this because the number of configuration cycles needed will
  probably be less than the total number of non-posted operations needed.

  When a retry status is received on the User RX interface for a
  configuration request that was sent on the User TX interface, it will be
  indicated with a completion with the CMPL_STATUS field set to 2=CRS, and
  the user will have to find the address and data values and send a new
  transaction on the User TX interface.  When the internal configuration
  space returns a retry status during a configuration cycle (user_cscfg =
  1) on the Command/Status interface, the pcie_cscrs will assert with the
  pcie_csack signal to indicate the CRS status.

  When the CRS Software Visibility Enable register in the Root Control
  register is enabled, the IP will return the data value to 0x0001 for the
  Vendor ID value and 0xffff  (all 1’s) for the rest of the data in the
  request for reads of offset 0 that return with CRS status.  This is true
  for both the User RX Interface and for the Command/Status interface.
  When CRS Software Visibility is enabled, the CMPL_STATUS field of the
  completion on the User RX Interface will not be 2=CRS and the pcie_cscrs
  signal will not assert on the Command/Status interface.

The Stingray hardware never reissues configuration requests when it
receives CRS completions.  Contrary to what sec 4.7.3.3 above says, when it
receives a CRS completion, it synthesizes 0xffff0001 data regardless of the
address of the read or the value of the CRS SV enable bit.

This is broken in two ways:

  1) When CRS SV is disabled, the Root Port should never synthesize the
  0x0001 value.  If it receives a CRS completion, it should fail the
  transaction and synthesize all 1's data.

  2) When CRS SV is enabled, the Root Port should only synthesize 0x0001
  data if it receives a CRS completion for a read of the Vendor ID.  If it
  receives a CRS completion for any other read, it should fail the
  transaction and synthesize all 1's data.

This breaks pci_flr_wait(), which reads the Command register and expects to
see all 1's data if the read fails because of CRS completions.  On
Stingray, it sees the incorrect 0xffff0001 data instead.

It also breaks config registers that contain the 0xffff0001 value.  If we
read such a register, software can't distinguish a CRS completion from the
actual value read from the device.

On Stingray, if we read 0xffff0001 data, assume this indicates a CRS
completion and retry the read for 500ms.  If we time out, return all 1's
(0xffffffff) data.  Note that this corrupts registers that happen to
contain 0xffff0001.

Stingray advertises CRS SV support in its Root Capabilities register, and
the CRS SV enable bit is writable (even though the hardware ignores it).
Mask out PCI_EXP_RTCAP_CRSVIS so software doesn't try to use CRS SV.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add probe-time warning about corruption, don't
advertise CRS SV support, remove duplicate pci_generic_config_read32(),
fix alignment based on patch from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Factor out the address calculation for memory-mapped config accesses as a
separate function.  No functional change intended.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

If the interrupt status is cleared before it is handled, it is possible
that another interrupt will trigger while servicing the previous one.  This
is causing timeouts in some wireless lan cards which use PCIe.

Clear MSI interrupt status after it gets serviced instead of before calling
generic_handler.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>

platform_get_irq() returns an error code, but the pci-dra7xx driver ignores
it and always returns -EINVAL. This is not correct and prevents
-EPROBE_DEFER from being propagated properly.

Print and propagate the return value of platform_get_irq() on failure.

This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>