- 26 Oct, 2021 6 commits
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Joey Gouly authored
This driver adds support for the pinctrl / GPIO hardware found on some Apple SoCs. Co-developed-by:
Stan Skowronek <stan@corellium.com> Signed-off-by:
Joey Gouly <joey.gouly@arm.com> Acked-by:
Hector Martin <marcan@marcan.st> Reviewed-by:
Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Joey Gouly authored
This property is used to describe the total number of pins on this particular pinctrl hardware block. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211026175815.52703-4-joey.gouly@arm.comSigned-off-by:
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Joey Gouly authored
The GPIO/pinctrl hardware can act as an interrupt-controller, so add the #interrupt-cells property to the binding. Signed-off-by:
Sven Peter <sven@svenpeter.dev> Acked-by:
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Linus Walleij authored
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Marc Zyngier authored
The core gpiolib code is able to deal with multiple interrupt parents for a single gpio irqchip. It however only allows a single piece of data to be conveyed to all flow handlers (either the gpio_chip or some other, driver-specific data). This means that drivers have to go through some interesting dance to find the correct context, something that isn't great in interrupt context (see aebdc8ab for a prime example). Instead, offer an optional way for a pinctrl/gpio driver to provide an array of pointers which gets used to provide the correct context to the flow handler. Signed-off-by:
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Prathamesh Shete authored
Fix warnings are errors caused by commit a42c7d95 ("pinctrl: tegra: Use correct offset for pin group"). Signed-off-by:
Prathamesh Shete <pshete@nvidia.com> Signed-off-by:
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- 25 Oct, 2021 2 commits
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Cai Huoqing authored
Adding a configuration menu to hold many Intel pin control drivers helps to make the display more concise. Acked-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Cai Huoqing <caihuoqing@baidu.com> Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Prathamesh Shete authored
Function tegra_pinctrl_gpio_request_enable() and tegra_pinctrl_gpio_disable_free() uses pin offset instead of group offset, causing the driver to use wrong offset to enable gpio. Add a helper function tegra_pinctrl_get_group() to parse the pin group and determine correct offset. Signed-off-by:
Kartik K <kkartik@nvidia.com> Signed-off-by:
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- 24 Oct, 2021 9 commits
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Yang Yingliang authored
I got memory leak as follows when doing fault injection test: unreferenced object 0xffff888020a7a680 (size 64): comm "i2c-mcp23018-41", pid 23090, jiffies 4295160544 (age 8.680s) hex dump (first 32 bytes): 00 48 d3 1e 80 88 ff ff 00 1a 56 c1 ff ff ff ff .H........V..... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<0000000083c79b35>] kmem_cache_alloc_trace+0x16d/0x360 [<0000000051803c95>] pinctrl_init_controller+0x6ed/0xb70 [<0000000064346707>] pinctrl_register+0x27/0x80 [<0000000029b0e186>] devm_pinctrl_register+0x5b/0xe0 [<00000000391f5a3e>] mcp23s08_probe_one+0x968/0x118a [pinctrl_mcp23s08] [<000000006112c039>] mcp230xx_probe+0x266/0x560 [pinctrl_mcp23s08_i2c] If pinctrl_claim_hogs() fails, the 'pindesc' allocated in pinctrl_register_one_pin() need be freed. Cc: stable@vger.kernel.org Reported-by:Hulk Robot <hulkci@huawei.com> Fixes: 950b0d91 ("pinctrl: core: Fix regression caused by delayed work for hogs") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20211022014323.1156924-1-yangyingliang@huawei.comSigned-off-by:
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Florian Fainelli authored
Update the pinctrl-bcm2835 driver to support being built as as a module by converting it to a module_platform_driver() with the appropriate module license, authors and description. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Nicolas Saenz Julienne <nsaenz@kernel.org> Link: https://lore.kernel.org/r/20211019221127.1953001-1-f.fainelli@gmail.comSigned-off-by:
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Rahul Tanwar authored
Ignore the same function with multiple groups. Fix a typo in error print. Fixes: 1948d5c5 ("pinctrl: Add pinmux & GPIO controller driver for a new SoC") Signed-off-by:
Rahul Tanwar <rtanwar@maxlinear.com> Link: https://lore.kernel.org/r/20211020093815.20870-1-rtanwar@maxlinear.comSigned-off-by:
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Prathamesh Shete authored
This change adds pinmux table entries for Tegra194 Signed-off-by:
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Suresh Mangipudi authored
Update lpdr pin-property for supported pins. lpdr property help disable most basic driver fingers leaving only minimal base driver finger. Signed-off-by:
Suresh Mangipudi <smangipudi@nvidia.com> Signed-off-by:
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Sam Shih authored
This commit includes pinctrl driver for Mediatek MT7986 The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by:
Sam Shih <sam.shih@mediatek.com> Acked-by:
Sean Wang <sean.wang@kernel.org> Link: https://lore.kernel.org/r/20211022124036.5291-3-sam.shih@mediatek.comSigned-off-by:
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Sam Shih authored
This updates bindings for MT7986 pinctrl driver. The difference of pinctrl between mt7986a and mt7986b is that pin-41 to pin-65 do not exist on mt7986b Signed-off-by:
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Horatiu Vultur authored
On lan966x platform when the switch gets reseted then also the sgpio gets reseted. The fix for this is to extend also the sgpio driver to call the reset driver which will be reseted only once by the first driver that is probed. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by:
Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20211018085754.1066056-3-horatiu.vultur@microchip.comSigned-off-by:
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Horatiu Vultur authored
This describes the new binding which allows to call a reset driver from the pinctrl-microchip-sgpio driver. Signed-off-by:
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- 17 Oct, 2021 7 commits
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Dmitry Baryshkov authored
Stop specifying individual interrupts properties. Use #interrupt-cells instead as we are switching qcom,spmi-mpp and qcom,ssbi-mpp to hierarchical IRQ setup. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-18-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-17-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,spmi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by:
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Dmitry Baryshkov authored
ssbi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by:
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Dmitry Baryshkov authored
The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by:
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Dmitry Baryshkov authored
Convert Qualcomm PMIC MPP bindings from .txt to .yaml format. Signed-off-by:
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Chanho Park authored
Add pinctrl data for ExynosAuto v9 SoC. - GPA0, GPA1: 10, External wake up interrupt - GPQ0: 2, XbootLDO, Speedy PMIC I/F - GPB0, GPB1, GPB2, GPB3: 29, I2S 7 CH - GPF0, GPF1, GPF2, GPF3,GPF4, GPF5, GPF6, GPF8: 52, FSYS - GPG0, GPG1, GPG2, GPG3: 25, GPIO x 24, SMPL_INT - GPP0, GPP1, GPP2, GPP3, GPP4, GPP5: 48, USI 12 CH Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20211008091443.44625-2-chanho61.park@samsung.comSigned-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211017171912.5044-1-krzysztof.kozlowski@canonical.comSigned-off-by:
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- 16 Oct, 2021 2 commits
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Johan Jonker authored
Convert rockchip,pinctrl.txt to YAML Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20211007144019.7461-1-jbx6244@gmail.comSigned-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.16 (take two) - Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N. - Miscellaneous fixes and improvements.
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- 15 Oct, 2021 6 commits
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Geert Uytterhoeven authored
Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for easier grepping. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by:
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Geert Uytterhoeven authored
Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by:
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Geert Uytterhoeven authored
The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e0 ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by:
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Geert Uytterhoeven authored
If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by:
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Andrey Gusakov authored
This adds pins, groups, and functions for MediaLB devices on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by:
Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com [geert: Fix automotive handling] Signed-off-by:
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- 13 Oct, 2021 5 commits
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Du Huanpeng authored
Signed-off-by:
Du Huanpeng <dhu@hodcarrier.org> Link: https://lore.kernel.org/r/1633879405-11658-1-git-send-email-dhu@hodcarrier.orgSigned-off-by:
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Fabien Dessenne authored
Since the 'st,package' property is optional, outputting the "No package detected" warning-level log when the property is absent is unsuitable. Remove that log. Signed-off-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20211008122454.617556-1-fabien.dessenne@foss.st.comSigned-off-by:
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Kunihiko Hayashi authored
Add pin configuration and pinmux support for UniPhier NX1 SoC. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1633518606-8298-4-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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Kunihiko Hayashi authored
Update pinctrl binding document for UniPhier NX1 SoC. Signed-off-by:
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Kunihiko Hayashi authored
Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs. Signed-off-by:
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- 12 Oct, 2021 2 commits
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Luca Weiss authored
Add support for the GPIO controller in the pm6350 PMIC. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20211007212444.328034-6-luca@z3ntu.xyzSigned-off-by:
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Luca Weiss authored
Add pmic-gpio compatible string for pm6350 pmic. Signed-off-by:
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- 03 Oct, 2021 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.16 - Fix duplicate port register on RZ/G2L, - A minor improvement.
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