- 23 Jul, 2014 1 commit
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Pawel Moll authored
Driver providing perf backend for ARM Cache Coherent Network interconnect. Supports counting all hardware events and crosspoint watchpoints. Currently works with CCN-504 only, although there should be no changes required for CCN-508 (just impossible to test it now). Signed-off-by:
Pawel Moll <pawel.moll@arm.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 20 Jul, 2014 2 commits
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Viresh Kumar authored
Following compilation warning occurs when compiled with: CONFIG_DEBUG_SECTION_MISMATCH=y WARNING: vmlinux.o(.init.data+0x3338): Section mismatch in reference from the variable spear13xx_pcie_driver to the function .exit.text:spear13xx_pcie_remove() This driver isn't allowed to unload, and so doesn't have a *_exit() routine. But it still has spear13xx_pcie_remove() marked with __exit. As this driver can't unload, .remove() would never be called, right? So get rid of it. Fixes: 51b66a6c (PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx) Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Viresh Kumar authored
Following compilation warning occurs when compiled with: CONFIG_DEBUG_SECTION_MISMATCH=y WARNING: drivers/pci/host/built-in.o(.data+0xc0): Section mismatch in reference from the variable spear13xx_pcie_driver to the function .init.text:spear13xx_pcie_probe() Both .probe() and pcie_init() are marked with __init, but spear13xx_pcie_driver isn't. And so section mismatch. Fix it by marking spear13xx_pcie_driver with __initdata. Fixes: 51b66a6c (PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx) Reported-by:
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- 19 Jul, 2014 2 commits
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Olof Johansson authored
Merge tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "ARM: tegra: rework PCIe regulators" from Thierry Reding: This branch reworks the set of regulators that the Tegra PCIe driver uses, so that the driver and DT bindings more correctly model what's really going on in HW. For backwards-compatibility the driver will fallback to using the old set of regulators if the new ones can't be found. I've made this a separate branch in case it needs to be pulled into the PCIe tree to resolve any conflicts. * tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Remove legacy PCIe power supply properties PCI: tegra: Remove deprecated power supply properties PCI: tegra: Implement accurate power supply scheme ARM: tegra: Add new PCIe regulator properties PCI: tegra: Overhaul regulator usage Signed-off-by:
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Olof Johansson authored
Merge branch 'spear/pcie-support-v10' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux into next/drivers Merge "ARM: SPEAr13xx PCIe updates for v3.17" from Viresh Kumar: This is another attempt to merge SPEAr PCIe updates after olof pointed out *enough* issues with initial PULL request: https://lkml.org/lkml/2014/7/9/641 Last version was sent here: http://patchwork.ozlabs.org/patch/368479/ and all the nits pointed out by Kishon & Bjorn are fixed in this pull request. Apart from ARM specific changes, this updates drivers/{pci|phy}. Bjorn advised to get complete series via arm-soc tree earlier: http://www.spinics.net/lists/linux-pci/msg30271.html * 'spear/pcie-support-v10' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux: ARM: SPEAr13xx: Update defconfigs ARM: SPEAr13xx: Add pcie and miphy DT nodes ARM: SPEAr13xx: Add bindings and dt node for misc block ARM: SPEAr13xx: Fix static mapping table phy: Add drivers for PCIe and SATA phy on SPEAr13xx PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx Signed-off-by:
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- 18 Jul, 2014 3 commits
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Thierry Reding authored
These properties are deprecated and no longer of any use. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Thierry Reding authored
These power supply properties are no longer needed since the binding now contains the full set properties to accurately describe the power supply inputs of the Tegra PCIe block. Signed-off-by:
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Thierry Reding authored
The current description of power supplies doesn't match the hardware. Instead it's designed to support the needs of current designs, which will break as soon as a new design appears that cannot be described using the current assumptions. In order to fully support all possible future designs, all power supply inputs to the PCIe block need to be accurately described and separately configurable. Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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- 14 Jul, 2014 6 commits
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Mohit Kumar authored
Enable PCIe, EABI, VFP and NFS configs in default configuration file for SPEAr13xx. Acked-by:
Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist] Signed-off-by:
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Pratyush Anand authored
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by:
Pratyush Anand <pratyush.anand@st.com> Signed-off-by:
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Pratyush Anand authored
SPEAr SOCs have some miscellaneous registers which are used to configure peripheral. This patch adds dt node and binding information for this block. Acked-by:
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Pratyush Anand authored
SPEAr13xx was using virtual address space 0xFE000000 to map physical address space 0xB3000000. But pci_remap_io uses 0xFEE00000 as virtual address and so replace 0xFE000000 with 0xF9000000. Acked-by:
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Pratyush Anand authored
ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys. This also adds proper bindings for miphys. Acked-by:
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Pratyush Anand authored
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip designware PCIe controller. To make that usable, this patch adds a wrapper driver based on existing designware driver. Adds bindings for this new driver and update MAINTAINERS as well. Cc: linux-pci@vger.kernel.org Acked-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
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- 13 Jul, 2014 1 commit
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git://github.com/at91linux/linux-at91Olof Johansson authored
Merge "at91: drivers for 3.17 #1" from Nicolas Ferre: "This update delayed to 3.17, is about replacing the existing calls to the older, non-standard drivers by the use of the newer "pwm-atmel" which takes advantage of the PWM framework. All concerned maintainer gave their acknowledgement to the relevant patches. At the end, it removes three obsolete drivers and the diffstat looks pretty nice as well." Atmel PWM driver update for 3.17 - move to the new PWM driver which uses PWM framework - remove 3 obsolete drivers (atmel-pwm-bl.c, leds-atmel-pwm.c and atmel_pwm.c) * tag 'at91-drivers' of git://github.com/at91linux/linux-at91: misc: atmel_pwm: remove obsolete driver leds: atmel-pwm: remove obsolete driver backlight: atmel-pwm-bl: remove obsolete driver avr32: update defconfig to use the generic PWM framework avr32: favr-32: use generic pwm_bl driver avr32: merisc: use generic leds_pwm driver avr32: MRMT: use generic leds_pwm driver avr32/at32ap: switch to the generic PWM framework PWM: atmel: allow building for AVR32 ARM: at91: remove useless at91_pwm_leds() ARM: at91: at91sam9rl: switch to generic PWM framework ARM: at91: sam9263ek: use generic leds_pwm driver ARM: at91: at91sam9263: switch to generic PWM framework ARM: at91: sam9m10g45ek: use generic leds_pwm driver ARM: at91: at91sam9g45: switch to generic PWM framework Signed-off-by:
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- 09 Jul, 2014 15 commits
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Alexandre Belloni authored
The misc/atmel_pwm is not used by any mainlined boards and has been replaced by the pwm-driver using the generic PWM framework. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Alexandre Belloni authored
The leds-atmel-pwm driver is now obsolete. It is not used by any mainlined boards and is replaced by the generic leds_pwm with the pwm-atmel driver using the generic PWM framework. Signed-off-by:
Bryan Wu <cooloney@gmail.com> Signed-off-by:
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Alexandre Belloni authored
The atmel-pwm-bl driver is now obsolete. It is not used by any mainlined boards and is replaced by the generic pwm_bl with the pawm-atmel driver using the generic PWM framework. Signed-off-by:
Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by:
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Alexandre Belloni authored
Now that all boards have switched to the generic PWM framework, update the defconfigs to use it. Signed-off-by:
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Alexandre Belloni authored
Switch to the generic pwm_bl driver instead of atmel-pwm-bl. Signed-off-by:
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Alexandre Belloni authored
Switch to the generic leds_pwm driver instead of leds-atmel-pwm. Signed-off-by:
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Alexandre Belloni authored
Switch to the generic leds_pwm driver instead of leds-atmel-pwm. Signed-off-by:
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Alexandre Belloni authored
Switch to the pwm/pwm-atmel driver instead of misc/atmel_pwm Signed-off-by:
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Alexandre Belloni authored
The Atmel PWM IP can be found on avr32 chips. This allows selecting and building the driver on avr32. Signed-off-by:
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Alexandre Belloni authored
Now that all at91 boards using leds-atmel-pwm switched to leds-pwm, the at91_pwm_leds() function is not used anymore. Signed-off-by:
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Alexandre Belloni authored
Switch to the pwm/pwm-atmel driver instead of misc/atmel_pwm Signed-off-by:
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Alexandre Belloni authored
Switch to the generic leds_pwm driver instead of leds-atmel-pwm. Signed-off-by:
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Alexandre Belloni authored
Switch to the pwm/pwm-atmel driver instead of misc/atmel_pwm Signed-off-by:
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Alexandre Belloni authored
Switch to the generic leds_pwm driver instead of leds-atmel-pwm. Signed-off-by:
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Alexandre Belloni authored
Switch to the pwm/pwm-atmel driver instead of misc/atmel_pwm Signed-off-by:
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- 29 Jun, 2014 10 commits
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Linus Torvalds authored
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git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds authored
Pull ARM fixes from Russell King: "Another round of ARM fixes. The largest change here is the L2 changes to work around problems for the Armada 37x/380 devices, where most of the size comes down to comments rather than code. The other significant fix here is for the ptrace code, to ensure that rewritten syscalls work as intended. This was pointed out by Kees Cook, but Will Deacon reworked the patch to be more elegant. The remainder are fairly trivial changes" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8087/1: ptrace: reload syscall number after secure_computing() check ARM: 8086/1: Set memblock limit for nommu ARM: 8085/1: sa1100: collie: add top boot mtd partition ARM: 8084/1: sa1100: collie: revert back to cfi_probe ARM: 8080/1: mcpm.h: remove unused variable declaration ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
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Randy Dunlap authored
Note that I don't maintain Documentation/ABI/, Documentation/devicetree/, or the language translation files. Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Dan Carpenter authored
These days most people use git to send patches so I have added a section about that. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Will Deacon authored
On the syscall tracing path, we call out to secure_computing() to allow seccomp to check the syscall number being attempted. As part of this, a SIGTRAP may be sent to the tracer and the syscall could be re-written by a subsequent SET_SYSCALL ptrace request. Unfortunately, this new syscall is ignored by the current code unless TIF_SYSCALL_TRACE is also set on the current thread. This patch slightly reworks the enter path of the syscall tracing code so that we always reload the syscall number from current_thread_info()->syscall after the potential ptrace traps. Acked-by:
Kees Cook <keescook@chromium.org> Tested-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Laura Abbott authored
Commit 1c2f87c2 (ARM: 8025/1: Get rid of meminfo) changed find_limits to use memblock_get_current_limit for calculating the max_low pfn. nommu targets never actually set a limit on memblock though which means memblock_get_current_limit will just return the default value. Set the memblock_limit to be the end of DDR to make sure bounds are calculated correctly. Signed-off-by:
Laura Abbott <lauraa@codeaurora.org> Signed-off-by:
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Andrea Adami authored
The CFI mapping is now perfect so we can expose the top block, read only. There isn't much to read, though, just the sharpsl_params values. Signed-off-by:
Andrea Adami <andrea.adami@gmail.com> Signed-off-by:
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Andrea Adami authored
Reverts commit d26b17ed ARM: sa1100: collie.c: fall back to jedec_probe flash detection Unfortunately the detection was challenged on the defective unit used for tests: one of the NOR chips did not respond to the CFI query. Moreover that bad device needed extra delays on erase-suspend/resume cycles. Tested personally on 3 different units and with feedback of two other users. Signed-off-by:
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Nicolas Pitre authored
The sync_phys variable has been replaced by link time computation in mcpm_head.S before the code was submitted upstream. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
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Thomas Petazzoni authored
When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Contrary to previous versions of this patch, this new version does not simply NULL-ify the ->sync member, because the l2c_init_data structures are now 'const' and therefore cannot be modified, which is a good thing. Therefore, this patch introduces a separate l2c_init_data instance, called of_l2c310_coherent_data. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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