- 17 Jun, 2013 10 commits
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Maxime Ripard authored
Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Maxime Ripard authored
It will allow us to have a cleaner separation between the data needed by the driver to work, and the core logic of the driver in itself, and will allow having too much noise in the core driver in the future. Signed-off-by:
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Linus Walleij authored
It is counter-intuitive to have "0" mean disable in a boolean manner for electronic properties of pins such as pull-up and pull-down. Therefore, define that a pull-up/pull-down argument of 0 to such a generic option means that the pin is short-circuited to VDD or GROUND. Pull disablement shall be done using PIN_CONFIG_BIAS_DISABLE. Cc: James Hogan <james.hogan@imgtec.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by Heiko Stuebner <heiko@sntech.de> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Heiko Stübner authored
Allocating the temorary array in pinconf_generic_parse_dt_config on stack might cause problems later on, when the number of options grows over time. Therefore also allocate this array dynamically to be on the safe side. Suggested-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Heiko Stübner authored
This adds a shortcut when no valid pinconf properties are found in the parsed dt node, to set the values immediately and return. Suggested-by:
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Heiko Stübner authored
The bias-pull-* options use values > 0 to indicate that the pull should be activated and optionally also indicate the strength of the pull. Therefore use an default value of 1 for these options. Split the low-power-mode option into low-power-enable and -disable. Update the documentation to describe the param arguments better. Reported-by:
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Christian Ruppert authored
The comment introduced with the recently added pinctrl_gpio_range.pins element was wrong. This corrects it. Thanks to Patrice Chotard for pointing this out. Signed-off-by:
Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by:
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Linus Walleij authored
This updates the GPIO range documentation with the API changes for sparse/random/arbitrary pin-to-GPIO mappings. Reviewed-by:
Rob Landley <rob@landley.net> Signed-off-by:
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Linus Walleij authored
The stubs for the !PINCTRL case were placed in the wrong part of the file, causing breakage in linux-next when compiling SH without pinctrl. Fix it up by moving the stubs to the right place. Signed-off-by: -
Christian Ruppert authored
Traditionally, GPIO ranges are based on consecutive ranges of both GPIO and pin numbers. This patch allows for GPIO ranges with arbitrary lists of pin numbers. Signed-off-by:
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- 16 Jun, 2013 30 commits
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Doug Anderson authored
This patch does nothing but reorder the functions to improve the readability of a future patch. Signed-off-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Tomasz Figa <t.figa@samsung.com> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
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Doug Anderson authored
The patch: 19846950 pinctrl: samsung: Protect bank registers with a spinlock ...added spinlocks to protect many accesses. However, the irq_mask and irq_unmask functions still do an unprotected read/modify/write. Add the spinlock there. Signed-off-by:
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Patrice Chotard authored
pinctrl-abx500.c: In function 'abx500_gpio_dbg_show_one': pinctrl-abx500.c:534:14: warning: 'pud' may be used uninitialized in this function [-Wuninitialized] Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Heiko Stübner authored
This driver adds support the Cortex-A9 based SoCs from Rockchip, so at least the RK2928, RK3066 (a and b) and RK3188. Earlier Rockchip SoCs seem to use similar mechanics for gpio handling so should be supportable with relative small changes. Pull handling on the rk3188 is currently a stub, due to it being a bit different to the earlier SoCs. Pinmuxing as well as gpio (and interrupt-) handling tested on a rk3066a based machine. Signed-off-by:
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Heiko Stübner authored
pinconf_generic_parse_dt_config() takes a node as input and generates an array of generic pinconfig values from the properties of this node. As I couldn't find a mechanism to count the number of properties of a node the function uses internally an array to accept one of parameter and copies the real present options to a smaller variable at its end. Signed-off-by:
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Mugunthan V N authored
This utilize the new pinctrl core PM helpers to transition the driver to "default" and "sleep" states. Signed-off-by:
Mugunthan V N <mugunthanvnm@ti.com> Acked-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
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Mugunthan V N authored
This utilize the new pinctrl core PM helpers to transition the driver to "default" and "sleep" states. Signed-off-by:
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Linus Walleij authored
This utilize the new pinctrl core PM helpers to transition the driver to "sleep" and "idle" states, cutting away some boilerplate code. Cc: Hebbar Gururaja <gururaja.hebbar@ti.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Kevin Hilman <khilman@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Wolfram Sang <wsa@the-dreams.de> Acked-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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Maxime Ripard authored
The A10 and A13 has a few pins that can be muxed into a particular function that can be used as an interrupt source. Add the available pins for such functions to the A10 and A13 description array. Signed-off-by:
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Maxime Ripard authored
The port controller IP found in the Allwinner A10 and A13 can use few of the pins it manage as an interrupt source, called external interrupts in the datasheet. The number of these external interrupts are SoCs specific, but the current upper limit is 32. In order to work, the external interrupts' pins have to be muxed to a specific function to generate an interrupt. This patch adds the irqchip and the needed logic to use the PIO controller as an interrupt controller. Signed-off-by:
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Maxime Ripard authored
Avoid to use expensive string manipulation functions and search by pin id when possible. Signed-off-by:
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Thomas Abraham authored
This patch fixes issues reported by prevent tool. Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
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Manjunathappa, Prakash authored
Take care to name pin names as register-offset.bit-pos-of-pin-in-register in case configuring multiple pins in register. Signed-off-by:
Manjunathappa, Prakash <prakash.pm@ti.com> Acked-by:
Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Manjunathappa, Prakash authored
Add support to configure multiple pins in each register, existing implementation added by [1] does not support full fledge multiple pin configuration in single register, reports a pin clash when different modules configure different bits of same register. The issue reported and discussed here http://www.spinics.net/lists/arm-kernel/msg235213.html With pinctrl-single,bits-per-mux property specified, use function-mask property to find out number pins to configure. Allocate and register pin control functions based sub mask. Tested on da850/omap-l138 EVM. does not support variable submask for pins. does not support pinconf. [1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux" (9e605cb6), Signed-off-by:
Lad, Prabhakar <prabhakar.csengg@gmail.com> Tested-by:
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Linus Walleij authored
This utilize the new pinctrl core PM helpers to transition the driver to "sleep" and "idle" states, cutting away some boilerplate code. Cc: Hebbar Gururaja <gururaja.hebbar@ti.com> Cc: Mark Brown <broonie@kernel.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Kevin Hilman <khilman@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Wolfram Sang <wsa@the-dreams.de> Signed-off-by:
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Linus Walleij authored
This augments the PL011 UART driver to utilize the new pinctrl core PM helpers to transition the driver to default and sleep states, cutting away some boilerplate code. Cc: Hebbar Gururaja <gururaja.hebbar@ti.com> Cc: Mark Brown <broonie@kernel.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Kevin Hilman <khilman@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Linus Walleij authored
If a device have sleep and idle states in addition to the default state, look up these in the core and stash them in the pinctrl state container. Add accessor functions for pinctrl consumers to put the pins into "default", "sleep" and "idle" states passing nothing but the struct device * affected. Solution suggested by Kevin Hilman, Mark Brown and Dmitry Torokhov in response to a patch series from Hebbar Gururaja. Cc: Hebbar Gururaja <gururaja.hebbar@ti.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
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Heiko Stübner authored
There exist controllers that don't support to set the pull to up or down separately but instead automatically set the pull direction based on embedded knowledge inside the controller, for example depending on the selected mux function of the pin. Therefore this patch adds another config option to use this default pull-state for a pin where it is not possible to know or decide if the pin will be pulled up or down. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Jingchang Lu authored
Adds Freescale Vybrid VF610 pin controller driver to IMX common pinctrl driver framework. Signed-off-by:
Jingchang Lu <b35083@freescale.com> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Jingchang Lu authored
On some platforms such as VF610, offset of mux and pad ctrl register may be zero, and the mux_mode and config_val are in one 32-bit register. This patch adds support to imx core pinctrl framework to handle these cases. Signed-off-by:
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James Hogan authored
Fix typo in "communicate directly with with the pinctrl subsystem". Signed-off-by:
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Patrice Chotard authored
- rework abx500_gpio_dbg_show_one() to take in account pull up/down feature available on AB8540 only. - add abx500_get_pull_updown() needed by abx500_gpio_dbg_show_one() - rename abx500_config_pull_updown() to abx500_set_pull_updown() Signed-off-by:
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Patrice Chotard authored
On ABx500 chip family, all pins support only pull down except for AB8540 which supports pull up/down on some pins. Rework abx500_pin_config_set to be able to set pull up on pins which support this feature. Signed-off-by:
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Patrice Chotard authored
Fix abx500_config_pull_updown() to set correct bit in AB8540_GPIO_PULL_UPDOWN_REG. Signed-off-by:
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James Hogan authored
Add a new PIN_CONFIG_BIAS_BUS_HOLD pin configuration for a bus holder pin mode (also known as bus keeper, or repeater). This is a weak latch which drives the last value on a tristate bus. Another device on the bus can drive the bus high or low before going tristate to change the value driven by the pin. Signed-off-by:
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James Hogan authored
Add the drive strength pinconf to debugfs output (with the unit "mA"). Signed-off-by:
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Patrice Chotard authored
Suppress a mutex which was initialized on probe and destroyed on remove but never used. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
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Barry Song authored
this patch saves the status of pinctrl registers and restore them while resuming. this makes all drivers have coherent status for pinmux after suspending and resuming. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Linus Walleij authored
The pinctrldev_list_mutex is sinked into the functions that actually traverse the list and lock it there. The code makes much more sense in this way. All the callers are in non-performance critical paths and the code is way more readable this way. Also refactor the function get_pinctrl_dev_from_devname() to follow the design pattern of get_pinctrl_dev_from_of_node() which is slightly simpler. Signed-off-by: -
Barry Song authored
atlas6 is a SoC very similar with primaII, the register layput of pinctrl is same, but the pads, groups and functions of atlas6 have different layout with prima2, this patch 1. pull the definition of pads, groups and functions out of the pinctrl-sirf driver,and put them into soc-specific files 2. add pads, groups and functions tables for atlas6 3. let pads, groups and functions tables become the config data of the related dt compatible node, so the pinctrl-sirf can support all SiRF SoCs with the config data as private data. In this patch,we create a sirf dir, and let the old drivers/pinctrl/pinctrl-sirf.c = drivers/pinctrl/sirf/pinctrl-prima2.c + drivers/pinctrl/sirf/pinctrl-sirf.c drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the pin layout of atlas6. Signed-off-by:
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