- Wrap ARM64-specific MCFG quirks in #ifdef so Loongson can use the file
  (Huacai Chen)

- Use generic (not 32-bit only) config accesses for LS2K/LS7A (Huacai Chen)

- Add ACPI and MCFG support for Loongson LS7A (Huacai Chen)

- Avoid config reads to non-existent LS2K/LS7A devices because a hardware
  defect causes machine hangs (Huacai Chen)

- Work around LS7A integrated devices that report incorrect Interrupt Pin
  values (Jianmin Lv)

* pci/ctrl/loongson:
  PCI: loongson: Work around LS7A incorrect Interrupt Pin registers
  PCI: loongson: Don't access non-existent devices
  PCI: loongson: Add ACPI init support
  PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A
  PCI/ACPI: Guard ARM64-specific mcfg_quirks

- Use bitmap API to allocate bitmaps instead of doing it by hand
  (Christophe JAILLET)

* pci/ctrl/iproc:
  PCI: iproc: Use bitmap API to allocate bitmaps

- Factor out ref clock disables to match enables (Bjorn Helgaas)

- Collect clock enables in imx6_pcie_clk_enable() (Richard Zhu)

- Propagate regulator and clock errors back to .host_init() caller (Richard
  Zhu)

- Disable i.MX6QDL clock when disabling ref clocks (Richard Zhu)

- Call host init function directly in resume instead of duplicating the
  code (Richard Zhu)

- Turn off regulators when suspending (Richard Zhu)

- Make link being down a non-fatal error so probe doesn't fail (Richard
  Zhu)

- Start link in resume only if it was up before suspend to reduce resume
  time (Richard Zhu)

- Move PHY init and power-on out of clock- and reset-related functions
  (Richard Zhu)

- Rework suspend callback to be more symmetric with resume (Richard Zhu)

- Set PCIE_DBI_RO_WR_EN before writing DBI registers (Richard Zhu)

- Allow speeds faster than Gen2 (Richard Zhu)

* pci/ctrl/imx6:
  PCI: imx6: Support more than Gen2 speed link mode
  PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registers
  PCI: imx6: Reformat suspend callback to keep symmetric with resume
  PCI: imx6: Move the imx6_pcie_ltssm_disable() earlier
  PCI: imx6: Disable clocks in reverse order of enable
  PCI: imx6: Do not hide PHY driver callbacks and refine the error handling
  PCI: imx6: Reduce resume time by only starting link if it was up before suspend
  PCI: imx6: Mark the link down as non-fatal error
  PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset()
  PCI: imx6: Turn off regulator when system is in suspend mode
  PCI: imx6: Call host init function directly in resume
  PCI: imx6: Disable i.MX6QDL clock when disabling ref clocks
  PCI: imx6: Propagate .host_init() errors to caller
  PCI: imx6: Collect clock enables in imx6_pcie_clk_enable()
  PCI: imx6: Factor out ref clock disable to match enable
  PCI: imx6: Move imx6_pcie_clk_disable() earlier
  PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier
  PCI: imx6: Move PHY management functions together
  PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlier
  PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS()

- Remove unnecessary include files (Bjorn Helgaas)

* pci/ctrl/fu740:
  PCI: fu740: Remove unnecessary include files

- Move samsung phy-exynos-pcie init all to exynos5433_pcie_phy_init()
  instead of splitting across phy_init() and phy_power_on() (Marek
  Szyprowski)

- Call phy_init() before phy_power_on() for samsung phy-exynos-pcie, as
  required by the PHY programming model (Marek Szyprowski)

* pci/ctrl/exynos:
  PCI: exynos: Correct generic PHY usage
  phy: samsung: phy-exynos-pcie: sanitize init/power_on callbacks

- Remove unused struct dw_edma_chip.irq (Frank Li)

- Move eDMA private data from struct dw_edma to struct dw_edma_chip (Frank
  Li)

- Convert "struct dw_edma_region rg_region" to "void __iomem *reg_base"
  since only the virtual address (not physical address or size) is used
  (Frank Li)

- Rename "*_ch_cnt" to "ll_*_cnt" to reflect actual usage (Frank Li)

- Drop dma_slave_config.direction field usage (Serge Semin)

- Fix eDMA Rd/Wr-channels and DMA-direction semantics (Serge Semin)

- Add chip-specific DW_EDMA_CHIP_LOCAL flag to indicate that local eDMA
  doesn't require generating MSIs to remote (Frank Li)

- Enable DMA tests for endpoints that support it (Frank Li)

* pci/ctrl/dwc-edma:
  PCI: endpoint: Enable DMA tests for endpoints with DMA capabilities
  dmaengine: dw-edma: Add support for chip-specific flags
  dmaengine: dw-edma: Fix eDMA Rd/Wr-channels and DMA-direction semantics
  dmaengine: dw-edma: Drop dma_slave_config.direction field usage
  dmaengine: dw-edma: Rename wr(rd)_ch_cnt to ll_wr(rd)_cnt in struct dw_edma_chip
  dmaengine: dw-edma: Change rg_region to reg_base in struct dw_edma_chip
  dmaengine: dw-edma: Detach the private data and chip info structures
  dmaengine: dw-edma: Remove unused irq field in struct dw_edma_chip

- Stop link on host_init errors and de-initialization (Serge Semin)

- Add support for unrolled iATU register space in dw_pcie_disable_atu()
  (Serge Semin)

- Disable outbound windows only for controllers that use iATU (Serge Semin)

- Set INCREASE_REGION_SIZE flag based on limit address, not on the size,
  since even a small size may cross a 4GB boundary (Serge Semin)

- Deallocate EPC memory on dw_pcie_ep_init() errors to avoid a leak (Serge
  Semin)

- Always enable CDM check if "snps,enable-cdm-check" exists instead of
  exiting early if the optional "num-lanes" was absent (Serge Semin)

- Simplify detection of whether we're using unrolled iATU registers (Serge
  Semin)

- Make dw_pcie_link_up() more generic by using dw_pcie_readl_dbi() instead
  of readl() (Serge Semin)

- Add dw_pcie_start_link() and dw_pcie_stop_link() wrappers to factor out
  checks for ops being implemented (Serge Semin)

- Move io_cfg_atu_shared to struct pcie_port and rename to cfg0_io_shared,
  since it's not used by dwc common code or dwc endpoint code (Serge Semin)

- Rename struct pcie_port to dw_pcie_rp to indicate that it's
  DesignWare-specific (Serge Semin)

- Drop unused struct dw_plat_pcie regmap pointer (Serge Semin)

- Fix some coding style issues (Serge Semin)

- Log link speed and width if it comes up (Serge Semin)

- Save DWC IP core version in native format as read from
  PORT_LOGIC.PCIE_VERSION_OFF register (Serge Semin)

- Read DWC IP core version from PORT_LOGIC.PCIE_VERSION_OFF (Serge Semin)

- Add macros to compare Synopsys IP core versions (Serge Semin)

- Drop manual DWC IP core version setup from intel-gw and tegra194 (Serge
  Semin)

- Add dw_pcie_ops.host_deinit() callback (Serge Semin)

- Drop enum dw_pcie_as_type in favor of PCIE_ATU_TYPE_MEM/IO (Serge Semin)

- Drop enum dw_pcie_region_type in favor of PCIE_ATU_REGION_DIR_IB/OB
  (Serge Semin)

- Simplify in/outbound iATU setup methods and reduce duplicated code (Serge
  Semin)

- Detect iATU region size from hardware (Serge Semin)

- Validate iATU outbound mappings against hardware constraints (Serge
  Semin)

- Check for errors in iATU setup (Serge Semin)

- Allocate a 32-bit DMA-able page to be MSI target instead of using a
  driver data structure that may not be addressable with 32-bit address
  (Will McVicker)

- Use the bitmap API to allocate bitmaps instead of open-coding it
  (Christophe JAILLET)

- Correct dw_pcie_free_msi() checking for when to remove IRQ handler and
  data (Dmitry Baryshkov)

- Split MSI init to new dw_pcie_msi_host_init() function (Dmitry Baryshkov)

- Convert struct pcie_port.msi_irq to an array so we can support more than
  32 MSI interrupts (Dmitry Baryshkov)

- Handle MSIs routed to multiple GIC interrupts for Qualcomm platforms with
  groups of 32 MSI vectors (Dmitry Baryshkov)

- Add additional MSI interrupts to qcom DT (Dmitry Baryshkov)

* pci/ctrl/dwc:
  dt-bindings: PCI: qcom: Support additional MSI vectors
  PCI: dwc: Handle MSIs routed to multiple GIC interrupts
  PCI: dwc: Convert struct pcie_port.msi_irq to an array
  PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
  PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
  PCI: dwc: Use the bitmap API to allocate bitmaps
  PCI: dwc: Fix MSI msi_msg DMA mapping
  PCI: dwc: Check iATU in/outbound range setup status
  PCI: dwc: Validate iATU outbound mappings against hardware constraints
  PCI: dwc: Add iATU regions size detection procedure
  PCI: dwc: Simplify in/outbound iATU setup methods
  PCI: dwc: Drop enum dw_pcie_region_type in favor of PCIE_ATU_REGION_DIR_IB/OB
  PCI: dwc: Drop enum dw_pcie_as_type in favor of PCIE_ATU_TYPE_MEM/IO
  PCI: dwc: Add dw_pcie_ops.host_deinit() callback
  PCI: tegra194: Drop manual DW PCIe controller version setup
  PCI: intel-gw: Drop manual DW PCIe controller version setup
  PCI: dwc: Add macros to compare Synopsys IP core versions
  PCI: dwc: Read DWC IP core version from register
  PCI: dwc: Use native DWC IP core version representation
  PCI: dwc: Detect iATU settings after getting "addr_space" resource
  PCI: dwc: Log link speed and width if it comes up
  PCI: dwc-plat: Drop dw_plat_pcie_of_match[] forward declaration
  PCI: dwc-plat: Drop unused regmap pointer
  PCI: dwc-plat: Simplify dw_plat_pcie_probe() return values
  PCI: dwc: Rename struct pcie_port to dw_pcie_rp
  PCI: dwc: Move io_cfg_atu_shared to struct pcie_port
  PCI: dwc: Add start_link/stop_link inlines
  PCI: dwc: Reuse local pointer to the resource data
  PCI: dwc: Organize local variable usage
  PCI: dwc: Convert dw_pcie_link_up() to use dw_pcie_readl_dbi()
  PCI: dwc: Simplify unrolled iATU detection
  PCI: dwc: Add newlines to log messages
  PCI: dwc: Add braces to multi-line if-else statements
  PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists
  PCI: dwc: Deallocate EPC memory on dw_pcie_ep_init() errors
  PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
  PCI: dwc: Disable outbound windows only for controllers using iATU
  PCI: dwc: Add unroll iATU space support to dw_pcie_disable_atu()
  PCI: dwc: Stop link on host_init errors and de-initialization

- Remove unnecessary forward declarations (Jim Quinlan)

- Prevent config space access when link is down (Jim Quinlan)

- Split post-link up initialization to brcm_pcie_start_link() (Jim Quinlan)

- Enable child bus device regulators described under Root Ports in DT (Jim
  Quinlan)

- Disable/enable regulators in suspend/resume (Jim Quinlan)

- Rename .map_bus() functions to end with 'map_bus' as they do in other
  drivers (Jim Quinlan)

* pci/ctrl/brcmstb:
  PCI: brcmstb: Rename .map_bus() functions to end with 'map_bus'
  PCI: brcmstb: Disable/enable regulators in suspend/resume
  PCI: brcmstb: Enable child bus device regulators from DT
  PCI: brcmstb: Split post-link up initialization to brcm_pcie_start_link()
  PCI: brcmstb: Prevent config space access when link is down
  PCI: brcmstb: Remove unnecessary forward declarations

- Add support for AER capability on emulated bridge (Pali Rohár)

- Add support for Slot capability on emulated bridge (Pali Rohár)

* pci/ctrl/aardvark:
  PCI: aardvark: Fix reporting Slot capabilities on emulated bridge
  PCI: aardvark: Add support for AER registers on emulated bridge

- Add ACS quirk for Broadcom BCM5750x multifunction NICs that isolate the
  functions but don't advertise an ACS capability (Pavan Chebbi)

* pci/virtualization:
  PCI: Add ACS quirk for Broadcom BCM5750x NICs

- Replace sparc pci_mmap_page_range() wrapper.  This still leaves a
  sparc-specific pci_mmap_resource_range(), but it's only one interface
  instead of two (Arnd Bergmann)

- Remove sparc-specific pci_mmap_resource_range() by implementing
  pci_iobar_pfn().  This removes the ability to map the entire PCI I/O
  space using /proc/bus/pci, but we believe that's already been broken
  since v2.6.28 (Arnd Bergmann)

* pci/resource:
  sparc: Use generic pci_mmap_resource_range()
  PCI: Remove pci_mmap_page_range() wrapper

- Convert documentation examples to generic power management (Bjorn
  Helgaas)

* pci/pm:
  PCI/doc: Convert examples to generic power management

- Recognize disconnected devices so we don't bother trying to set them to
  "frozen" or "normal" state (Christoph Hellwig)

- Clear PCI Status register during enumeration in case firmware left errors
  logged (Kai-Heng Feng)

- Configure ECRC for every device, including hot-added ones (Stefan Roese)

- Keep AER error reporting enabled for switches (Stefan Roese)

- Enable error reporting for all devices that support AER (Stefan Roese)

- Iterate over error counters instead of error strings to avoid printing
  junk in AER sysfs counters (Mohamed Khalfella)

* pci/err:
  PCI/AER: Iterate over error counters instead of error strings
  PCI/AER: Enable error reporting when AER is native
  PCI/portdrv: Don't disable AER reporting in get_port_device_capability()
  PCI/AER: Configure ECRC for every device
  PCI: Clear PCI_STATUS when setting up device
  PCI/ERR: Recognize disconnected devices in report_error_detected()

- Split out ARI "next function" handling from the traditional one (Niklas
  Schnelle)

- Move jailhouse "isolated function" (non-zero functions where function 0
  doesn't exist) handling to pci_scan_slot() to avoid duplicating
  multi-function scanning in pci_scan_child_bus_extend() (Niklas Schnelle)

- Extend "isolated function" probing to s390 (Niklas Schnelle).

- Allow s390 zPCI zbus without a function 0 (Niklas Schnelle)

* pci/enumeration:
  s390/pci: allow zPCI zbus without a function zero
  PCI: Extend isolated function probing to s390
  PCI: Move jailhouse's isolated function handling to pci_scan_slot()
  PCI: Split out next_ari_fn() from next_fn()
  PCI: Clean up pci_scan_slot()

- Don't stop an EPC when unbinding an EPF from it (Shunsuke Mie)

* pci/endpoint:
  PCI: endpoint: Don't stop controller when unbinding endpoint function

- Remove pcie_aspm_pm_state_change(), which overwrites ASPM config on power
  state changes (Kai-Heng Feng)

* pci/aspm:
  PCI/ASPM: Unexport pcie_aspm_support_enabled()
  PCI/ASPM: Remove pcie_aspm_pm_state_change()

Support more than Gen2 speed link mode, since i.MX8MP PCIe supports up to
Gen3 link speed.

Link: https://lore.kernel.org/r/1658287576-26908-1-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The PCIE_DBI_RO_WR_EN bit should be set when write some DBI registers.  To
make sure that the DBI registers are writable, set the PCIE_DBI_RO_WR_EN
properly when writing the DBI registers.

Link: https://lore.kernel.org/r/1652866528-13220-1-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Create imx6_pcie_stop_link() and imx6_pcie_host_exit() functions.
Encapsulate clocks, regulators disables and PHY uninitialization into
imx6_pcie_host_exit().

To keep suspend/resume symmetric as much as possible, invoke these two
new created functions in suspend callback.

To be symmetric with imx6_pcie_host_exit(), move imx6_pcie_clk_enable()
to imx6_pcie_host_init() from imx6_pcie_deassert_core_reset().

Link: https://lore.kernel.org/r/1657783869-19194-18-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Move the imx6_pcie_ltssm_disable() earlier and place it just behind the
imx6_pcie_ltssm_enable(), since it might not be only used by suspend
callback directly.

To be symmetric with imx6_pcie_ltssm_enable(), add the IMX6Q and IMX8MQ
switch cases in imx6_pcie_ltssm_disable().

Link: https://lore.kernel.org/r/1657783869-19194-17-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

imx6_pcie_clk_enable() enables clocks in the order:

  pcie_phy
  pcie_bus
  pcie
  imx6_pcie_enable_ref_clk

Change imx6_pcie_clk_disable() to disable them in the reverse order.

Link: https://lore.kernel.org/r/1657783869-19194-16-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Move the phy_power_on() to host_init from imx6_pcie_clk_enable().

Move the phy_init() to host_init from imx6_pcie_deassert_core_reset().

Refine the error handling in imx6_pcie_host_init() accordingly.

Link: https://lore.kernel.org/r/1657783869-19194-15-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

i.MX PCIe doesn't support hotplug. During resume, only start PCIe link
training when the link was up before system suspend to avoid the long
latency in the link training period.

Link: https://lore.kernel.org/r/1657783869-19194-14-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

If the PCIe link is down, return zero from imx6_pcie_start_link() so the
driver will probe successfully.

Link: https://lore.kernel.org/r/1657783869-19194-13-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Move regulator enable out of imx6_pcie_deassert_core_reset(), since the
regulator_enable() has nothing to do with imx6_pcie_deassert_core_reset().

Link: https://lore.kernel.org/r/1657783869-19194-12-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The driver should undo any enables it did itself. The regulator disable
shouldn't be basing decisions on regulator_is_enabled().

Move the regulator_disable to the suspend function, turn off regulator when
the system is in suspend mode.

Link: https://lore.kernel.org/r/1657783869-19194-11-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Call imx6_pcie_host_init() instead of duplicating codes in resume.  Note
that this also means we do MPLL setup again during resume, which we didn't
do before.

[bhelgaas: add MPLL setup note, pointed out by Lucas]
Link: https://lore.kernel.org/r/1657783869-19194-10-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

When disabling PCIe clocks, disable i.MX6QDL ref clock too.

Link: https://lore.kernel.org/r/1657783869-19194-9-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Since dw_pcie_host_init() checks for errors from ops->host_init(),
check for errors when enabling power regulators and clocks and return them.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/1657783869-19194-8-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Encapsulate the i.MX PCIe clock enable operations into one standalone
function, imx6_pcie_clk_enable().  No functional change intended.

[bhelgaas: split pure code moves into separate patches]
Link: https://lore.kernel.org/r/1657783869-19194-7-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

The PCIe ref clocks are specific to different variants.  The enables are
already split out into imx6_pcie_enable_ref_clk(), but the disables were
combined with the more generic bus/phy/pcie clock disables in
imx6_pcie_clk_disable().

Split out the variant-specific disables into imx6_pcie_disable_ref_clk() to
match imx6_pcie_enable_ref_clk().

No functional change intended.

Link: https://lore.kernel.org/r/1657783869-19194-6-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Move imx6_pcie_clk_disable() earlier to be near other clock-related
functions.  No functional change intended.

[bhelgaas: reorder patch so pure moves are earlier]
Link: https://lore.kernel.org/r/1657783869-19194-5-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

Move imx6_pcie_enable_ref_clk() earlier so it's not in the middle between
imx6_pcie_assert_core_reset() and imx6_pcie_deassert_core_reset().  No
functional change intended.

Link: https://lore.kernel.org/r/1657783869-19194-4-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Collect imx6_pcie_init_phy(), imx7d_pcie_wait_for_phy_pll_lock(), and
imx6_setup_phy_mpll() earlier with other PHY-related code.  No functional
change intended.

Link: https://lore.kernel.org/r/1657783869-19194-3-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Move imx6_pcie_grp_offset() and imx6_pcie_configure_type() earlier in the
file since they depend on nothing and are used by several other functions
that will be moved earlier.  No functional change intended.

Link: https://lore.kernel.org/r/1657783869-19194-2-git-send-email-hongxing.zhu@nxp.comSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Replace SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() with NOIRQ_SYSTEM_SLEEP_PM_OPS(),
which has the advantage that the compiler always sees the PM callbacks as
referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP"
or tagged with "__maybe_unused" to avoid "defined but not used" warnings.

See 1a3c7bb0 ("PM: core: Add new *_PM_OPS macros, deprecate old ones").
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>

The proper initialization for generic PHYs is to call first phy_init(),
then phy_power_on().

While touching this, remove the phy_reset() call. It is just a left-over
from the obsoleted Exynos5440 support and the current exynos-pcie PHY
driver doesn't even support this function. It is also rarely used by other
drivers.

Link: https://lore.kernel.org/r/20220628220409.26545-2-m.szyprowski@samsung.comReported-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

The exynos-pcie driver called phy_power_on() before phy_init() for some
historical reasons. However the generic PHY framework assumes that the
proper sequence is to call phy_init() first, then phy_power_on(). The
operations done by both functions should be considered as one action and as
such they are called by the exynos-pcie driver (without doing anything
between them). The initialization is just a sequence of register writes,
which cannot be altered without breaking the hardware operation.

To match the generic PHY framework requirement, simply move all register
writes to the phy_init()/phy_exit() and drop power_on()/power_off()
callbacks. This way the driver will also work with the old (incorrect)
PHY initialization call sequence.

Link: https://lore.kernel.org/r/20220628220409.26545-1-m.szyprowski@samsung.comReported-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-By: Vinod Koul <vkoul@kernel.org>

On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.

Link: https://lore.kernel.org/r/20220707134733.2436629-6-dmitry.baryshkov@linaro.orgSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

On some Qualcomm platforms each group of 32 MSI vectors is routed to a
separate GIC interrupt. Implement support for such configurations by
parsing "msi0" ... "msiX" interrupts and attaching them to the chained
handler.

Note that if DT doesn't list an array of MSI interrupts and uses a single
"msi" IRQ, the driver will limit the number of supported MSI vectors to 32.

Link: https://lore.kernel.org/r/20220707134733.2436629-5-dmitry.baryshkov@linaro.orgSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>