- 28 Dec, 2021 10 commits
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Tao Zhou authored
CP supports unmap queue with reset mode which only destroys specific queue without affecting others. Replacing whole gpu reset with reset queue mode for RAS poison consumption saves much time, and we can also fallback to gpu reset solution if reset queue fails. v2: Return directly if process is NULL; Reset queue solution is not applicable to SDMA, fallback to legacy way; Call kfd_unref_process after lookup process. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tao Zhou authored
The new interface unmaps queues with reset mode for the process consumes RAS poison, it's only for compute queue. v2: rename the function to reset_queues. Signed-off-by:
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Tao Zhou authored
So we can set reset mode for unmap operation, no functional change. Signed-off-by:
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Tao Zhou authored
Add a reset parameter for umc page retirement, let user decide whether call gpu reset in umc page retirement. Signed-off-by:
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Victor Skvortsov authored
Expand RLCG interface for new GC read & write commands. New interface will only be used if the PF enables the flag in pf2vf msg. v2: Added a description for the scratch registers Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
David Nieto <david.nieto@amd.com> Signed-off-by:
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Victor Skvortsov authored
Driver needs to call get_xgmi_info() before ip_init to determine whether it needs to handle a pending hive reset. Signed-off-by:
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Victor Skvortsov authored
Modify GC register access from MMIO to RLCG if the indirect flag is set Signed-off-by:
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Victor Skvortsov authored
Modify GC register access from MMIO to RLCG if the indirect flag is set v2: Replaced ternary operator with if-else for better readability Signed-off-by:
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Victor Skvortsov authored
Add helper macros to change register access from direct to indirect. Signed-off-by:
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Bokun Zhang authored
Recently, there is security policy update under SRIOV. We need to filter the registers that hit the violation and move the code to the host driver side so that the guest driver can execute correctly. Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Reviewed-by:
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- 16 Dec, 2021 12 commits
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Alex Deucher authored
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c:744:35-36: WARNING comparing pointer to 0. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Some old registers leftover from pre-silicon. No longer relevant on real hardware. Remove. Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Victor Skvortsov authored
We want to be able to call virt data exchange conditionally after gmc sw init to reserve bad pages as early as possible. Since this is a conditional call, we will need to call it again unconditionally later in the init sequence. Refactor the data exchange function so it can be called multiple times without re-initializing the work item. v2: Cleaned up the code. Kept the original call to init_exchange_data() inside early init to initialize the work item, afterwards call exchange_data() when needed. Signed-off-by:
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Changcheng Deng authored
Use max() and min() in order to make code cleaner. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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chen gong authored
Play a video on the raven (or PCO, raven2) platform, and then do the S3 test. When resume, the following error will be reported: amdgpu 0000:02:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring vcn_dec test failed (-110) [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block <vcn_v1_0> failed -110 amdgpu 0000:02:00.0: amdgpu: amdgpu_device_ip_resume failed (-110). PM: dpm_run_callback(): pci_pm_resume+0x0/0x90 returns -110 [why] When playing the video: The power state flag of the vcn block is set to POWER_STATE_ON. When doing suspend: There is no change to the power state flag of the vcn block, it is still POWER_STATE_ON. When doing resume: Need to open the power gate of the vcn block and set the power state flag of the VCN block to POWER_STATE_ON. But at this time, the power state flag of the vcn block is already POWER_STATE_ON. The power status flag check in the "8f2cdef drm/amd/pm: avoid duplicate powergate/ungate setting" patch will return the amdgpu_dpm_set_powergating_by_smu function directly. As a result, the gate of the power was not opened, causing the subsequent ring test to fail. [how] In the suspend function of the vcn block, explicitly change the power state flag of the vcn block to POWER_STATE_OFF. BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1828Signed-off-by:
chen gong <curry.gong@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Lijo Lazar authored
Fix the message argument. 0: Allow power down 1: Disallow power down Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Mario Limonciello authored
This is still needed for thoes in case the firmware fails to load then the message is the only way to tell what firmware was on them Suggested-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Philip Yang authored
Add svm_range_bo_unref_async to schedule work to wait for svm_bo eviction work done and then free svm_bo. __do_munmap put_page is atomic context, call svm_range_bo_unref_async to avoid warning invalid wait context. Other non atomic context call svm_range_bo_unref. Signed-off-by:
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Huang Rui authored
The job embedded fence donesn't initialize the flags at dma_fence_init(). Then we will go a wrong way in amdgpu_fence_get_timeline_name callback and trigger a null pointer panic once we enabled the trace event here. So introduce new amdgpu_fence object to indicate the job embedded fence. [ 156.131790] BUG: kernel NULL pointer dereference, address: 00000000000002a0 [ 156.131804] #PF: supervisor read access in kernel mode [ 156.131811] #PF: error_code(0x0000) - not-present page [ 156.131817] PGD 0 P4D 0 [ 156.131824] Oops: 0000 [#1] PREEMPT SMP PTI [ 156.131832] CPU: 6 PID: 1404 Comm: sdma0 Tainted: G OE 5.16.0-rc1-custom #1 [ 156.131842] Hardware name: Gigabyte Technology Co., Ltd. Z170XP-SLI/Z170XP-SLI-CF, BIOS F20 11/04/2016 [ 156.131848] RIP: 0010:strlen+0x0/0x20 [ 156.131859] Code: 89 c0 c3 0f 1f 80 00 00 00 00 48 01 fe eb 0f 0f b6 07 38 d0 74 10 48 83 c7 01 84 c0 74 05 48 39 f7 75 ec 31 c0 c3 48 89 f8 c3 <80> 3f 00 74 10 48 89 f8 48 83 c0 01 80 38 00 75 f7 48 29 f8 c3 31 [ 156.131872] RSP: 0018:ffff9bd0018dbcf8 EFLAGS: 00010206 [ 156.131880] RAX: 00000000000002a0 RBX: ffff8d0305ef01b0 RCX: 000000000000000b [ 156.131888] RDX: ffff8d03772ab924 RSI: ffff8d0305ef01b0 RDI: 00000000000002a0 [ 156.131895] RBP: ffff9bd0018dbd60 R08: ffff8d03002094d0 R09: 0000000000000000 [ 156.131901] R10: 000000000000005e R11: 0000000000000065 R12: ffff8d03002094d0 [ 156.131907] R13: 000000000000001f R14: 0000000000070018 R15: 0000000000000007 [ 156.131914] FS: 0000000000000000(0000) GS:ffff8d062ed80000(0000) knlGS:0000000000000000 [ 156.131923] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 156.131929] CR2: 00000000000002a0 CR3: 000000001120a005 CR4: 00000000003706e0 [ 156.131937] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 156.131942] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 156.131949] Call Trace: [ 156.131953] <TASK> [ 156.131957] ? trace_event_raw_event_dma_fence+0xcc/0x200 [ 156.131973] ? ring_buffer_unlock_commit+0x23/0x130 [ 156.131982] dma_fence_init+0x92/0xb0 [ 156.131993] amdgpu_fence_emit+0x10d/0x2b0 [amdgpu] [ 156.132302] amdgpu_ib_schedule+0x2f9/0x580 [amdgpu] [ 156.132586] amdgpu_job_run+0xed/0x220 [amdgpu] v2: fix mismatch warning between the prototype and function name (Ray, kernel test robot) Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Prike Liang authored
In the s0ix entry need retain gfx in the gfxoff state,so here need't set gfx cgpg in the S0ix suspend-resume process. Moreover move the S0ix check into SMU12 can simplify the code condition check. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Mario Limonciello authored
Since this variable was made available by the previous commit, use it to make function access cleaner. Suggested-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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- 14 Dec, 2021 18 commits
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Xiang wangx authored
Delete the redundant word 'we'. Reviewed-by:
Xiang wangx <wangxiang@cdjrlc.com> Signed-off-by:
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Yann Dirson authored
Signed-off-by:
Yann Dirson <ydirson@free.fr> Signed-off-by:
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Yann Dirson authored
Those are not today pulled by the sphinx doc, but better be ready. Signed-off-by:
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Yann Dirson authored
This is Alex' description from the "Looking for clarifications around gfx/kcq/kiq" thread, edited to fit as ReST. Original text: https://www.spinics.net/lists/amd-gfx/msg71383.htmlOriginally-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Yann Dirson authored
This describes in broad lines the how an AMD GPU is organized, in terms of hardware blocks. This is Alex' description from the "gpu block diagram" thread, edited to fit as ReST. Original text: https://www.spinics.net/lists/amd-gfx/msg71543.htmlOriginally-by:
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Lang Yu authored
Memory is allocated for gpu_metrics_table in renoir_init_smc_tables(), but not freed in int smu_v12_0_fini_smc_tables(). Free it! Fixes: 95868b85 ("drm/amd/powerplay: add Renoir support for gpu metrics export") Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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Jingwen Chen authored
[Why] gmc bo will be pinned during loading amdgpu and reset in SRIOV while only unpinned in unload amdgpu [How] add amdgpu_in_reset and sriov judgement to skip pin bo v2: fix wrong judgement Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
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Jingwen Chen authored
[Why] psp tmr bo will be pinned during loading amdgpu and reset in SRIOV while only unpinned in unload amdgpu [How] add amdgpu_in_reset and sriov judgement to skip pin bo v2: fix wrong judgement Signed-off-by:
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Lijo Lazar authored
Power states are not valid for arcturus and aldebaran, no need to allocate memory. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Evan Quan authored
Pair the operations did in GMC ->hw_init and ->hw_fini. That can help to maintain correct cached state for GMC and avoid unintention gate operation dropping due to wrong cached state. BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1828Signed-off-by:
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Guchun Chen authored
Updated for consistency when accessing drm_device from amdgpu driver. Signed-off-by:
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Evan Quan authored
As the smu_context will be invisible from outside(of power). Also, the smu_debug_mask can be shared around all power code instead of some specific framework(swSMU) only. Signed-off-by:
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Victor Skvortsov authored
Host initiated VF FLR may fail if someone else is already holding a read_lock. Change from down_write_trylock to down_write to guarantee the reset goes through. Signed-off-by:
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Aric Cyr authored
Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Martin Leung authored
why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us of dc state change how: added dal3 interface for KMD added pathway to query smu for this softmax added blank before clock change to override underflow added logic to change clk based on pstatesupport and softmax added logic in prepare/optimize_bw to conform while changing clocks Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Eric Bernstein authored
[Why] For ODM + MPO window on one half of ODM, only 3 pipes should be allocated and scaling parameters adjusted to handle this case [How] Fix pipe allocation when MPO viewport is only on one side of ODM split, and modify scaling paramters. Added diags test cases for ODM + windows MPO, where MPO window is on right half, left half, and both halves or ODM. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] If the firmware wasn't reset by PSP or HW and is currently running then the firmware will hang or perform underfined behavior when we modify its firmware state underneath it. [How] Reset DMCUB before setting up cache windows and performing HW init. Reviewed-by:
Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Anthony Koo authored
Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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