- 13 Sep, 2022 7 commits
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Sandeep Maheswaram authored
Add device tree bindings for SNPS phy tuning parameters. Signed-off-by:
Sandeep Maheswaram <quic_c_sanm@quicinc.com> Signed-off-by:
Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1662480933-12326-2-git-send-email-quic_kriskura@quicinc.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Johan Hovold authored
Drop the obsolete and misleading dual-lane comments which gave the impression that only combo PHYs have a second lane. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220906074550.4383-4-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The driver function prefix has gotten unnecessarily long and hurts readability. Shorten "qcom_qmp_phy_" to "qmp_" (which likely stands for "Qualcomm Multi PHY" or similar anyway). Signed-off-by:
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Dmitry Baryshkov authored
Drop unused if (table) conditions, since the function qcom_qmp_phy_pcie_configure_lane() has this check anyway. Signed-off-by:
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Johan Hovold authored
At least the "qcom,sc8280xp-qmp-usb43dp-phy" binding requires a power domain to be specified. Fixes: aa27597e ("dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys") Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220902080705.12050-3-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
At least the "sc8280xp-qmp-usb3-uni-phy" binding requires a power domain to be specified. Fixes: aa27597e ("dt-bindings: phy: qcom,qmp: Add compatible for SC8280XP USB phys") Signed-off-by:
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Horatiu Vultur authored
The serdes driver contains also a mux to decide which interface type to use. Currently the driver supports GMII/SGMII/QSGMII and partially RGMII. As it doesn't support all the other RGMII interfaces like RGMII_TXID/RXID/ID and it could run only at 1G. Therefore extend this for all the other speeds(10/100) and also allow the other interfaces. Signed-off-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20220901121455.245103-1-horatiu.vultur@microchip.comSigned-off-by:
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- 04 Sep, 2022 4 commits
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Peter Geis authored
The otg sync state patch reuses the ret variable, but fails to set it to zero after use. This leads to a situation when the otg port is in peripheral mode where the otg phy aborts halfway through setup. It also fails to account for a failure to register the extcon notifier. Fix this by using our own variable and skipping otg sync in case of failure. Fixes: 8dc60f8d ("phy: rockchip-inno-usb2: Sync initial otg state") Reported-by:
Markus Reichl <m.reichl@fivetechno.de> Reported-by:
Michael Riesch <michael.riesch@wolfvision.net> Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Tested-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220902184543.1234835-1-pgwipeout@gmail.comSigned-off-by:
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Heiner Kallweit authored
Simplify the code by using devm_clk_get_enabled(). Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/9308a2a3-e828-bd9d-ab83-a68376aab5c3@gmail.comSigned-off-by:
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Shawn Lin authored
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add data-lanes property for splitting pcie-lanes across controllers. The data-lanes is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Suggested-by:
Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.deSigned-off-by:
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Frank Wunderlich authored
Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by:
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- 02 Sep, 2022 6 commits
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Michael Riesch authored
This adds support for variant found in Rockchip RK356x SoCs. Note that only the basic operating mode is supported, in which all four CSI lines are controlled by the Rockchip ISP. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220720091527.1270365-3-michael.riesch@wolfvision.netSigned-off-by:
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Michael Riesch authored
The driver for the Innosilicon MIPI CSI DPHY is compatible with the variant in the Rockchip RK356x SoCs. Add the compatible string to the binding. Signed-off-by:
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Krzysztof Kozlowski authored
Emails to Pratyush Yadav bounce ("550 Invalid recipient"), so update to match one in commit 92714596 ("MAINTAINERS: Use my kernel.org email"). Signed-off-by:Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20220816132131.75591-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Bjorn Andersson authored
When the platform was booted with the involved clocks enabled the clk_set_rate() of the link and pixel clocks will perculate to the children, which will fail to update because the PHY driver has just shut down the PLL. Postpone the clock rate updates until the PLL is back online to avoid reconfiguring the clocks while the PLL is not ticking. Fixes: f199223c ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220805154432.546740-1-bjorn.andersson@linaro.orgSigned-off-by:
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Vincent Shih authored
Add bindings doc for Sunplus USB2 PHY driver Reviewed-by:
Vincent Shih <vincent.sunplus@gmail.com> Link: https://lore.kernel.org/r/1658717052-26142-3-git-send-email-vincent.sunplus@gmail.comSigned-off-by:
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Vincent Shih authored
Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by:
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- 30 Aug, 2022 23 commits
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Johan Hovold authored
The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by:
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Johan Hovold authored
The lane reset is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the reset name. Update driver to support the new binding where the "lane" reset name has been deprecated by instead requesting the reset by index. Reviewed-by:
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Johan Hovold authored
The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by:
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Johan Hovold authored
The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by:
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Johan Hovold authored
Drop the unused lane reset pointer which isn't used by any combo PHY. Reviewed-by:
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Johan Hovold authored
The pipe clock is defined in the "lane" node so there's no need to keep adding a redundant lane-number suffix to the clock name. Update driver to support the new binding where the pipe clock name has been deprecated by instead requesting the clock by index. Reviewed-by:
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Johan Hovold authored
Deprecate the USB PHY node 'clock-names' property which specified that the PIPE clock name should have a bogus "lane" suffix. Reviewed-by:
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Johan Hovold authored
The QMP PHY wrapper node is not a clock provider so drop the bogus '#clock-cells' property that was added when converting to DT schema. Fixes: 59351049 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY") Reviewed-by:
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Johan Hovold authored
The "qcom,sc7180-qmp-usb3-phy" compatible is apparently used to describe a combo PHY where only the USB part is used. Specifically, only a single reset is used. Fixes: 4ad7d7ee ("dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180") Fixes: 94c34600 ("dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to qcom,qmp-phy.yaml") Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have a bogus "lane" suffix. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the USB PHY binding in a separate file. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
Add the missing optional power-domains property used by the SM8150 UFS QMP PHY to the binding. Fixes: fe75b0c4 ("arm64: dts: qcom: sm8150: Add ufs power-domain entries") Reviewed-by:
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Johan Hovold authored
Add the missing "qref" clock used by the SM8450 UFS QMP PHY to the binding. Note that the "qref" clock was added to sm8450.dtsi by commit 07fa917a ("arm64: dts: qcom: sm8450: add ufs nodes") but the binding was never updated to match. Fixes: e04121ba ("dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the UFS PHY binding in a separate file. Add an example node based on a cleaned up version of sc8280xp.dtsi. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have a bogus "lane" suffix. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the PCIe PHY binding in a separate file. Add an example node based on a cleaned up version of sm8250.dtsi. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'reset-names' property which specified that the reset name should have an unnecessary "lane" suffix. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have an unnecessary "lane" suffix. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child nodes which were ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the odd-bird msm8996-qmp-pcie-phy which is the only QMP PHY that uses separate "per-lane" nodes. Add an example node based on a cleaned up version of msm8996.dtsi. Reviewed-by:
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