- 16 Jul, 2020 7 commits
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Lee Jones authored
>From ill formatted kerneldoc, to incomplete *and* incorrect struct headers, through to formatting issues and missing attribute descriptions. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/sirf/pinctrl-atlas7.c:197: warning: Function parameter or member 'id' not described in 'atlas7_pad_config' drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'func' not described in 'atlas7_pad_status' drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'pull' not described in 'atlas7_pad_status' drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'dstr' not described in 'atlas7_pad_status' drivers/pinctrl/sirf/pinctrl-atlas7.c:221: warning: Function parameter or member 'reserved' not described in 'atlas7_pad_status' drivers/pinctrl/sirf/pinctrl-atlas7.c:359: warning: Cannot understand * @dev: a pointer back to containing device on line 359 - I thought it was a doc line drivers/pinctrl/sirf/pinctrl-atlas7.c:4794: warning: Function parameter or member 'pad_type' not described in 'atlas7_pull_info' drivers/pinctrl/sirf/pinctrl-atlas7.c:4917: warning: Function parameter or member 'reserved' not described in 'atlas7_ds_info' drivers/pinctrl/sirf/pinctrl-atlas7.c:5617: warning: Function parameter or member 'a7gc' not described in 'atlas7_gpio_to_bank' drivers/pinctrl/sirf/pinctrl-atlas7.c:5617: warning: Function parameter or member 'gpio' not described in 'atlas7_gpio_to_bank' Signed-off-by:
Lee Jones <lee.jones@linaro.org> Cc: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20200713144930.1034632-3-lee.jones@linaro.orgSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Lee Jones authored
Fixes the following W=1 kernel build warning(s): drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'clk' not described in 'owl_pinctrl' drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'irq_chip' not described in 'owl_pinctrl' drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'num_irq' not described in 'owl_pinctrl' drivers/pinctrl/actions/pinctrl-owl.c:52: warning: Function parameter or member 'irq' not described in 'owl_pinctrl' Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: "Andreas Färber" <afaerber@suse.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: David Liu <liuwei@actions-semi.com> Link: https://lore.kernel.org/r/20200713144930.1034632-2-lee.jones@linaro.orgSigned-off-by:
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Brian Norris authored
We've added drive-open-drain support, so note it in the DT binding. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200703080646.23233-2-computersforpeace@gmail.comSigned-off-by:
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Jaiganesh Narayanan authored
[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based WiFi APs. ] Signed-off-by:
Jaiganesh Narayanan <njaigane@codeaurora.org> Signed-off-by:
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Andrew Jeffery authored
The default pinmux configuration for Y23 is to route a heartbeat to drive a LED. Previous revisions of the AST2600 datasheet did not include a description of this function. Fixes: 2eda1cde ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200701030756.2834657-1-joel@jms.id.auSigned-off-by:
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Andrew Jeffery authored
We need to iterate over each pin in a group for a function and disable higher priority mux configurations on the pin before finally muxing the relevant function's signal. With the current debug output it is hard to track what register output is relevant to which operation, so break up the actions in the debug output by providing some more context. Before: [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341 [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 After: [ 5.298053] Muxing pin 37 for GPIO [ 5.298294] Disabling signal NRI4 for NRI4 [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4 [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.299694] Disabling signal RMII4RXD1 for RMII4 [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.300396] Enabling signal GPIOE5 for GPIOE5 [ 5.300687] Muxed pin 37 as GPIOE5 Signed-off-by: -
Drew Fustini authored
Modify omap_gpio_set_config() to handle pin config bias flags by calling gpiochip_generic_config(). The pin group for the gpio line must have the corresponding pinconf properties: PIN_CONFIG_BIAS_PULL_UP requires "pinctrl-single,bias-pullup" PIN_CONFIG_BIAS_PULL_DOWN requires "pinctrl-single,bias-pulldown" This is necessary for pcs_pinconf_set() to find the requested bias parameter in the PIN_MAP_TYPE_CONFIGS_GROUP pinctrl map. Signed-off-by:
Drew Fustini <drew@beagleboard.org> Acked-by:
Grygorii Strashko <grygorii.strashko@ti.com> Acked-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20200715213738.1640030-1-drew@beagleboard.orgSigned-off-by:
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- 11 Jul, 2020 2 commits
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Kathiravan T authored
set target proc as APPS to route the gpio interrupts to APPS Co-developed-by:
Rajkumar Ayyasamy <arajkuma@codeaurora.org> Signed-off-by:
Kathiravan T <kathirav@codeaurora.org> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1594107588-17055-1-git-send-email-kathirav@codeaurora.orgSigned-off-by:
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Mark Tomlinson authored
Rather than always using handle_simple_irq() as the gpio_irq_chip handler, set a more appropriate handler based on the IRQ trigger type requested. This is important for level triggered interrupts which need to be masked during handling. Also, fix the interrupt acknowledge so that it clears only one interrupt instead of all interrupts which are currently active. Finally there is no need to clear the interrupt during the interrupt handler, since the edge-triggered handler will do that for us. Signed-off-by:
Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> Link: https://lore.kernel.org/r/20200703011830.15655-1-mark.tomlinson@alliedtelesis.co.nzSigned-off-by:
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- 07 Jul, 2020 11 commits
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Furquan Shaikh authored
This change drops the override in `amd_gpio_irq_set_type()` that ignores the IRQ trigger type settings from the caller. The device driver (caller) is in a better position to identify the right trigger type for the device based on the usage as well as the information exposed by the BIOS. There are instances where the device driver might want to configure the trigger type differently in different modes. An example of this is gpio-keys driver which configures IRQ type as trigger on both edges (to identify assert and deassert events) when in S0 and reconfigures the trigger type using the information provided by the BIOS when going into suspend to ensure that the wake happens on the required edge. This override in `amd_gpio_irq_set_type()` prevents the caller from being able to reconfigure trigger type once it is set either based on ACPI information or the type used by the first caller for IRQ on a given GPIO line. Without this change, pen-insert gpio key (used by garaged stylus on a Chromebook) works fine in S0 (i.e. insert and eject events are correctly identified), however, BIOS configuration for wake on only pen eject i.e. only-rising edge or only-falling edge is not honored. With this change, it was verified that pen-insert gpio key behavior is correct in both S0 and for wakeup from S3. Signed-off-by:
Furquan Shaikh <furquan@google.com> Signed-off-by: Shyam Sundar S K<Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20200626211026.513520-1-furquan@google.comSigned-off-by:
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Paul Cercueil authored
The PAT1 register contains information about the IRQ type (edge/level) for input GPIOs with IRQ enabled, and the direction for non-IRQ GPIOs. So it makes sense to read it only if the GPIO has no interrupt configured, otherwise input GPIOs configured for level IRQs are misdetected as output GPIOs. Fixes: ebd66514 ("pinctrl: ingenic: Implement .get_direction for GPIO chips") Reported-by:
João Henrique <johnnyonflame@hotmail.com> Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200622214548.265417-2-paul@crapouillou.netSigned-off-by:
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Paul Cercueil authored
Ingenic SoCs don't natively support registering an interrupt for both rising and falling edges. This has to be emulated in software. Until now, this was emulated by switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING according to the level of the GPIO. While this worked most of the time, when used with GPIOs that need debouncing, some events would be lost. For instance, between the time a falling-edge interrupt happens and the interrupt handler configures the hardware for rising-edge, the level of the pin may have already risen, and the rising-edge event is lost. To address that issue, instead of switching back and forth between IRQ_TYPE_EDGE_RISING and IRQ_TYPE_EDGE_FALLING, we now switch back and forth between IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH. Since we always switch in the interrupt handler, they actually permit to detect level changes. In the example above, if the pin level rises before switching the IRQ type from IRQ_TYPE_LEVEL_LOW to IRQ_TYPE_LEVEL_HIGH, a new interrupt will raise as soon as the handler exits, and the rising-edge event will be properly detected. Fixes: e72394e2 ("pinctrl: ingenic: Merge GPIO functionality") Reported-by:
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Paul Cercueil authored
Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml. In the process, some compatible strings now require a fallback, as the corresponding SoCs are pin-compatible with their fallback variant. Signed-off-by:
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Konrad Dybcio authored
Signed-off-by:
Konrad Dybcio <konradybcio@gmail.com> Reviewed-by:
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Konrad Dybcio authored
Add support for pm660(l) SPMI GPIOs. The PMICs feature 13 and 12 GPIOs respectively, though with a lot of holes inbetween. Signed-off-by:
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Lars Povlsen authored
This add support for Sparx5 pinctrl, using the ocelot drives as basis. It adds pinconfig support as well, as supported by the platform. Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200615133242.24911-6-lars.povlsen@microchip.comSigned-off-by:
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Hyeonki Hong authored
If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two or more registers. However, when register and bit were calculated, the first register defined in the bank was used, and the bit was calculated based on the first pin. This causes problems in setting the driving strength. The following method was used to solve this problem: A bit is calculated first using predefined strides. Then, If the bit is 32 or more, the register is changed by the quotient of the bit divided by 32. And the bit is set to the remainder. Signed-off-by:
Hyeonki Hong <hhk7734@gmail.com> Link: https://lore.kernel.org/r/20200618025916.GA19368@home-desktopSigned-off-by:
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Drew Fustini authored
Use the correct the function name in the documentation for "pcs_parse_one_pinctrl_entry()". "smux_parse_one_pinctrl_entry()" appears to be an artifact from the development of a prior patch series ("simple pinmux driver") which transformed into pinctrl-single. Fixes: 8b8b091b ("pinctrl: Add one-register-per-pin type device tree based pinctrl driver") Signed-off-by: -
Drew Fustini authored
Increase #pinctrl-cells to 2 so that mux and conf be kept separate. This requires the AM33XX_PADCONF macro in omap.h to also be modified to keep pin conf and pin mux values separate. Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Link: https://lore.kernel.org/r/20200701013320.130441-3-drew@beagleboard.orgSigned-off-by:
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Drew Fustini authored
If "pinctrl-single,pins" has 3 arguments (offset, conf, mux), then pcs_parse_one_pinctrl_entry() does an OR operation on conf and mux to get the value to store in the register. Signed-off-by:
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- 06 Jul, 2020 10 commits
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8DXL pinctrl driver as module. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/1592979844-18833-10-git-send-email-Anson.Huang@nxp.comSigned-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8QM pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8QXP pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8MP pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8MQ pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8MN pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Change configuration to "tristate", add module device table, author, description and license to support building i.MX8MM pinctrl driver as module. Signed-off-by:
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Anson Huang authored
Export necessary APIs to support i.MX8 SCU SoCs pinctrl driver to be built as module. Signed-off-by:
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Anson Huang authored
Export necessary APIs to support i.MX8 SoCs pinctrl driver to be built as module. Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.9 - Add RPC (HyperFlash and Octal-SPI Flash) pin groups on R-Car V3H and V3M.
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- 22 Jun, 2020 2 commits
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Sergei Shtylyov authored
Add the RPC pins/groups/functions to the R8A77970 PFC driver. They can be used if an Octal-SPI flash or HyperFlash is connected. Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/3982785f-4fca-96f9-2b6a-a0d1828cb0ad@cogentembedded.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sergei Shtylyov authored
Add the RPC pins/groups/functions to the R8A77980 PFC driver. They can be used if an Octal-SPI flash or HyperFlash is connected. Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by:
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- 20 Jun, 2020 8 commits
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Linus Walleij authored
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Andy Shevchenko authored
Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200615150545.87964-6-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by:
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Andy Shevchenko authored
Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by:
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Andy Shevchenko authored
Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Gregory Clement <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20200615150545.87964-3-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
Introduce for_each_requested_gpio_in_range() macro which helps to iterate over requested GPIO in a range. There are already potential users of it, which are going to be converted by the following patches. For most of them for_each_requested_gpio() shortcut has been added. Signed-off-by:
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Alexandre Torgue authored
Adds the possibility to configure a single pin through the gpiolib (i.e: to set PULL_UP/PULL_DOWN config). Mutex behavior is slightly changed to avoid a deadlock when pin_config_set is called (in this case pctldev->mutex is already taken). Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Link: https://lore.kernel.org/r/20200615125951.28008-3-alexandre.torgue@st.comSigned-off-by:
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Alexandre Torgue authored
".pin_config_set" or ".pin_config_group_set" can be called with a configuration not supported (i.e. PIN_CONFIG_PERSIST_STATE). In this case, it is more suitable to return -ENOTSUPP instead of -EINVAL. Signed-off-by:
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