- 07 May, 2013 1 commit
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Ben Widawsky authored
This reverts commit 03752f5b. This revert requires a bit of explanation on how I understand things work. Internally the architects/designers decide how the stolen encoding works. We put it in a doc. BIOS writers take these docs and implement it. Driver writers read the doc too, and read the value left by the BIOS writers, and then we make magic. The failing here is that in the docs we had[1] contained two different definitions for this register for Gen7. (We have both a PCI register, and an MMIO, and each of these were different). At the time [2] of 03752f5b, we asked the architects what the correct value should be; but that doesn't match the reality (BIOS) unfortunately. So on all machines I can get my hands on, this revert is the right thing to do. I've also worked with the product group to confirm that they agree this revert is what we should do. People using HW made my "people" who both write their own BIOS, and have access to our docs (Apple?). Investigations are still ongoing about whether we need to add a list of machines needing special handling, but this patch should be the right thing for pretty much everyone. [1] The docs are still wrong on this one. Now instead of two registers with two definitions, we have one register with BOTH definitions, progress? [2] The open source PRMs have the "wrong" definitions in chapter Volume 1 part6, section 1.1.12. This digging was inspired by Paulo. Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Augment the patch saying that it's still a bit unclear whether there are any machines out there with "wrong" firmware and whether we need to add a list to handle them specially.] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 04 May, 2013 2 commits
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Imre Deak authored
According to BSpec the link training sequence for eDP on HSW port-A should be as follows: 1. link training: clock recovery 2. link training: equalization 3. link training: set idle transmission mode 4. display pipe enable 5. link training: disable (set normal mode) Contrary to this at the moment we don't do step 3. and we do step 5. before step 4. Fix this by setting idle transmission mode for eDP at the end of intel_dp_complete_link_train and adding a new intel_dp_stop_link_training function to disable link training. With these changes we'll end up with the following functions corresponding to the above steps: intel_dp_start_link_train -> step 1. intel_dp_complete_link_train -> step 2., step 3. intel_dp_stop_link_train -> step 5. For port-A we'll call intel_dp_stop_link_train only after enabling the pipe, for everything else we'll call it right after intel_dp_complete_link_train to preserve the current behavior. Tested on HSW/HSW-ULT. In v2: - Due to a HW issue we must set idle transmission mode for port-A too before enabling the pipe. Thanks for Arthur Runyan for explaining this. - Update the patch subject to make it clear that it's an eDP fix, DP is not affected. v3: - rename intel_dp_link_train() to intel_dp_set_link_train(), use 'val' instead 'l' as var name. (Paulo) Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by:
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Daniel Vetter authored
This reverts commit 57c21963. It's an ugly hack for a Haswell SDV platform where the vbt doesn't seem to fully agree with the panel. Since it seems to cause issues on real eDP platform let's just kill this hack again. Reported-and-tested-by:
Josh Boyer <jwboyer@gmail.com> References: https://lkml.org/lkml/2013/5/3/467 Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by:
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- 02 May, 2013 1 commit
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Daniel Vetter authored
Since we know that locking is broken in that case and it's more important to not flood the dmesg with random gunk. Cc: Dave Airlie <airlied@gmail.com> Cc: Borislav Petkov <bp@alien8.de> References: http://lkml.kernel.org/r/20130502000206.GH15623@pd.tnic Cc: stable@vger.kernel.org Reported-and-tested-by:
Borislav Petkov <bp@suse.de> Signed-off-by:
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- 01 May, 2013 1 commit
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Ville Syrjälä authored
Fix the incorrect enabled pipes mask for pipe C in the WM calculations. Additionally, in an effort to make the code easier to understand, populate the mask with 1 << PIPE_[ABC] instead of raw numbers. v2: Use 1 << PIPE_[ABC] (ickle/danvet) v3: Pass PIPE_[ABC] to g4x_compute_wm0() (ickle) Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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- 30 Apr, 2013 2 commits
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Daniel Vetter authored
In commit 9e8944ab Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Nov 15 11:32:17 2012 +0000 drm: Introduce an iterator over holes in the drm_mm range manager helpers and iterators for hole handling have been introduced with some debug BUG_ONs sprinkled over. Unfortunately this broke the mm dumper which unconditionally tried to compute the size of the very first hole. While at it unify the code a bit with the hole dumping in the loop. v2: Extract a hole dump helper. Reported-by:
Christopher Harvey <charvey@matrox.com> Cc: Christopher Harvey <charvey@matrox.com> Cc: Dave Airlie <airlied@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Chris Wilson authored
As we recompute the remaining timeout after waiting, there is a potential for that timeout to be less than zero and so need sanitizing. The timeout is always returned to userspace and validated, so we should always perform the sanitation. v2 [vsyrjala]: Only normalize the timespec if it's invalid v3: Add a comment to clarify the situation and remove the now useless WARN_ON() (ickle) Cc: Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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- 27 Apr, 2013 1 commit
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Zhang, Xiong Y authored
When ppgtt is enabled, dev_priv->gtt.total has excluded the gtt space occupied by ppgtt table in i915_gem_init_global_gtt() function. So the calculation of first_pd_entry_in_global_pt doesn't need to subtract I915_PPGTT_PD_ENTRIES again. Or else PPGTT directory table will be destroyed by global gtt allocation. This regression has been introduced in commit a54c0c27 Author: Ben Widawsky <ben@bwidawsk.net> Date: Thu Jan 24 14:45:00 2013 -0800 drm/i915: remove intel_gtt structure The breakage is pretty subtile since the old gtt_total_entries included the pde range, whereas the new on did not. Cc: stable@vger.kernel.org Signed-off-by: Xiong Zhang<xiong.y.zhang@intel.com> [danvet: Add regression citation and cc: stable. Thanks to Chris for correcting my wrong guess about which commit broke things.] Signed-off-by:
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- 24 Apr, 2013 1 commit
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Ben Widawsky authored
This reverts commit fec46b5e. The latest version of our PM programming doc (which is WAY better than previous versions, and thanks for that) says something along the lines of, "On Haswell overclocking is no long achieved via mailbox registers." Which I misinterpreted as, the driver must done something different than it did on IVB, and SNB. It appears I jumped the gun, and that's all false. We've gotten some clarification, and it appears at least *reading* the overclocking information works in exactly the same manner. Cc: kim.l.saw-chu@intel.com Signed-off-by:
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- 23 Apr, 2013 2 commits
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Ville Syrjälä authored
The BIOS uses power of two values for the data/link N value. Follow suit to make the Zotac DP to dual-HDMI dongle work. v2: Clean up the magic numbers and defines Change the N clamping to be a bit easier on the eye Rename intel_reduce_ratio to intel_reduce_m_n_ratio Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402Signed-off-by: -
Daniel Vetter authored
Automatic color range selection was added in commit 55bc60db Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Thu Jan 17 16:31:29 2013 +0200 drm/i915: Add "Automatic" mode for the "Broadcast RGB" property but that removed the check to avoid a full modeset if the value is unchanged. Unfortunately X sets all properties with their current value at start-up, resulting in some ugly flickering which shouldn't be there. v2: Change old_range from bool to uint32_t, spotted by Ville. v3: Actually git add everything ;-) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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- 19 Apr, 2013 1 commit
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David Müller (ELSOFT AG) authored
As discussed in this thread http://lists.freedesktop.org/archives/dri-devel/2013-April/037411.html GMBUS based DVO transmitter detection seems to be unreliable which could result in an unusable DVO port. The attached patch fixes this by falling back to bit banging mode for the time DVO transmitter detection is in progress. Signed-off-by:
David Müller <d.mueller@elsoft.ch> Tested-by:
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- 18 Apr, 2013 28 commits
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Daniel Vetter authored
Oops. This regression has been introduced in commit 5d2d38dd Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:45:01 2013 +0100 drm/i915: clean up pipe bpp confusion Reported-by:
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Daniel Vetter authored
For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in ->disable and other modeset callbacks. In the future we need to add hw state readout&check support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. v2: Preserve the cpu_transcoder value when overwriting crtc->config. Reported by Paulo. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by:
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Paulo Zanoni authored
Bits 30 and 24:0 are PBC, so don't zero them. Some of the other bits are being zeroed, but I couldn't find a reason for this, so leave them as they are for now to avoid regressions. Signed-off-by:
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Paulo Zanoni authored
Check the VBT to see if the machine has inverted FDI RX polarity on CPT. Based on this bit, set the appropriate bit on the TRANS_CHICKEN2 registers. This should fix some machines that were showing black screens on all outputs. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60029Signed-off-by:
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Egbert Eich authored
We disable hoptplug detection when we encounter a hotplug event storm. Still hotplug detection is required on some outputs (like Display Port). The interrupt storm may be only temporary (on certain Dell Laptops for instance it happens at certain charging states of the system). Thus we enable it after a certain grace period (2 minutes). Should the interrupt storm persist it will be detected immediately and it will be disabled again. v2: Reordered drm_i915_private: moved hotplug_reenable_timer to hpd state tracker. v3: Clarified loop start value, Removed superfluous test for Ivybridge and Haswell, Restructured loop to avoid deep nesting (all suggested by Ville Syrjälä) v4: Fixed two bugs pointed out by Jani Nikula. Signed-off-by:Egbert Eich <eich@suse.de> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Egbert Eich authored
This patch disables hotplug interrupts if an 'interrupt storm' has been detected. Noise on the interrupt line renders the hotplug interrupt useless: each hotplug event causes the devices to be rescanned which will will only increase the system load. Thus disable the hotplug interrupts and fall back to periodic device polling. v2: Fixed cleanup typo. v3: Fixed format issues, clarified a variable name, changed pr_warn() to DRM_INFO() as suggested by Jani Nikula <jani.nikula@linux.intel.com>. Signed-off-by: -
Egbert Eich authored
To disable previously enabled HPD IRQs we need to reset them and set the enabled ones individually. Signed-off-by:
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Egbert Eich authored
When an encoder is shared on several connectors there is only one hotplug line, thus this line needs to be shared among these connectors. If HPD detect only works reliably on a subset of those connectors, we want to poll the others. Thus we need to make sure that storm detection doesn't mess up the settings for those connectors. Therefore we store the settings in the intel_connector struct and restore them from there. If nothing is set but the encoder has a hpd_pin set we assume this connector is hotplug capable. On init/reset we make sure the polled state of the connectors is (re)set to the default value, the HPD interrupts are marked enabled. Signed-off-by:
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Egbert Eich authored
Add a hotplug IRQ storm detection (triggered when a hotplug interrupt fires more than 5 times / sec). Rationale: Despite of the many attempts to fix the problem with noisy hotplug interrupt lines we are still seeing systems which have issues: Once cause of noise seems to be bad routing of the hotplug line on the board: cross talk from other signals seems to cause erronous hotplug interrupts. This has been documented as an erratum for the the i945GM chipset and thus hotplug support was disabled for this chipset model but others seem to have this problem, too. We have seen this issue on a G35 motherboard for example: Even different motherboards of the same model seem to behave differently: while some only see only around 10-100 interrupts/s others seem to see 5k or more. We've also observed a dependency on the selected video mode. Also on certain laptops interrupt noise seems to occur duing battery charging when the battery is at a certain charge levels. Thus we add a simple algorithm here that detects an 'interrupt storm' condition. v2: Fixed comment. v3: Reordered drm_i915_private: moved hpd state tracking to hotplug work stuff. v4: Followed by Jesse Barnes to use a time_..() macro. v5: Fixed coding style as suggested by Jani Nikula. Signed-off-by:
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Paulo Zanoni authored
Signed-off-by:
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Paulo Zanoni authored
We may have DDI_BUF_CTL(PORT_A) configured with 2 lanes and still not have CRT, so just check for !IS_ULT. This problem happened on a real machine and resulted in a very ugly dmesg. Cc: stable@vger.kernel.org Signed-off-by:
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Paulo Zanoni authored
We have the exact same comment inside intel_init_display. This is a leftover from when we moved a lot of code from intel_display.c to intel_pm.c. Signed-off-by:
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Ben Widawsky authored
Caused by me with v2 of commit 219f4fdb Author: Ben Widawsky <ben@bwidawsk.net> Date: Fri Mar 15 11:17:54 2013 -0700 drm/i915: Introduce GEN7_FEATURES for device info I don't have a VLV to test it with, Jesse, Ken, can one of you test? Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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Chris Wilson authored
Haswell introduces a separate frequency domain for the ring (uncore). So where we used to increase the CPU (IA) clock with GPU busyness, we now need to scale the ring frequency directly instead. As the ring limits our memory bandwidth, it is vital for performance that when the GPU is busy, we increase the frequency of the ring to increase the available memory bandwidth. v2: Fix the algorithm to actually use the scaled gpu frequency for the ring. v3: s/max_ring_freq/min_ring_freq/ as that is what it is Signed-off-by:
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Mika Kuoppala authored
commit 647416f9 Author: Kees Cook <keescook@chromium.org> Date: Sun Mar 10 14:10:06 2013 -0700 drm/i915: use simple attribute in debugfs routines made i915_next_seqno debugfs entry to crop it's output if returned value was large enough. Using simple_attr will limit the output to 24 bytes. Fix is to strip out preamples on all simple attributes that have one. v2: Fix all simple attributes (Daniel Vetter) Cc: Kees Cook <keescook@chromium.org> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Acked-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Daniel Vetter authored
The recent rework of the pfit handling didn't take into account that the panel fitter is fixed to pipe B: commit 24a1f16d Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Fri Feb 8 16:35:37 2013 +0200 drm/i915: disable shared panel fitter for pipe Fix this up by properly computing the pipe the pfit is on. Also extract the logic into its own function, add a debug assert to check that the pipe is off (mostly just documentation) and add some debug output. If pipe A was disabled after pipe B was set up, the panel fitter will be disabled. Now most userspace doesn't do modesets in this order, which is why I couldn't ever reproduce this and why it took me so long to figure out. We really need hw state readout and check support for the pannel fitter ... Reported-by:
Hans de Bruin <jmdebruin@xmsnet.nl> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Hans de Bruin <jmdebruin@xmsnet.nl> References: http://permalink.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/19049Reviewed-by:
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Daniel Vetter authored
Yet again our current confusion between doing the modeset globally, but only having the new parameters for one crtc at a time. So that intel_set_mode essentially already does a global modeset: intel_modeset_affected_pipes compares the current state with where we want to go to (which is carefully set up by intel_crtc_set_config) and then goes through the modeset sequence for any crtc which needs updating. Now the issue is that the actual interface with the remaining code still only works on one crtc, and so we only pass in one fb and one mode. In intel_set_mode we also only compute one intel_crtc_config (which should be the one for the crtc we're doing a modeset on). The reason for that mismatch is twofold: - We want to eventually do all modeset as global state changes, so it's just infrastructure prep. - But even the old semantics can change more than one crtc when you e.g. move a connector from crtc A to crtc B, then both crtc A and B need to be updated. Usually that means one pipe is disabled and the other enabled. This is also the reason why the hack doesn't touch the disable_pipes mask. Now hilarity ensued in our kms config restore paths when we actually try to do a modeset on all crtcs: If the first crtc should be off and the second should be on, then the call on the first crtc will notice that the 2nd one should be switched on and so tries to compute the pipe_config. But due to a lack of passed-in fb (crtc 1 should be off after all) it only results in tears. This case is ridiculously easy to hit on gen2/3 where the lvds output is restricted to pipe B. Note that before the pipe_config bpp rework gen2/3 didn't care really about the fb->depth, so this is a regression brought to light with commit 4e53c2e0 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Mar 27 00:44:58 2013 +0100 drm/i915: precompute pipe bpp before touching the hw But apparently Ajax also managed to blow up pch platforms, probably with some randomized configs, and pch platforms trip up over the lack of an fb even in the old code. So this actually goes back to the first introduction of the new modeset restore code in commit 45e2b5f6 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Nov 23 18:16:34 2012 +0100 drm/i915: force restore on lid open Fix this mess by now by justing shunting all the cool new global modeset logic in intel_modeset_affected_pipes. v2: Improve commit message and clean up all the comments in intel_modeset_affected_pipes - since the introduction of the modeset restore code they've been a bit outdated. Bugzill: https://bugzilla.redhat.com/show_bug.cgi?id=917725 Cc: stable@vger.kernel.org References: http://www.mail-archive.com/stable@vger.kernel.org/msg38084.htmlTested-by:
Richard Cochran <richardcochran@gmail.com> Reviewed-by:
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Jani Nikula authored
Backlight cleanup in the eDP connector destroy callback caused the backlight device to be removed on some systems that first initialized LVDS and then attempted to initialize eDP. Prevent multiple backlight initializations, and ensure backlight cleanup is only done once by moving it to modeset cleanup. A small wrinkle is the introduced asymmetry in backlight setup/cleanup. This could be solved by adding refcounting, but it seems overkill considering that there should only ever be one backlight device. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=55701Signed-off-by:
Peter Verthez <peter.verthez@skynet.be> Cc: stable@vger.kernel.org Signed-off-by:
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Paulo Zanoni authored
This solves some "unclaimed register" messages when booting the machine with eDP attached. V2: Rebase and add the comment requested by Daniel. Signed-off-by:
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Paulo Zanoni authored
It returns true if we've requested to turn the power well on and it's really on. It also returns true for all the previous gens. For now there's just one caller, but I'm going to add more. Signed-off-by:
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Daniel Vetter authored
It will be only consistent once we've restored all the crtcs. Since a bunch of other callers also want to just restore a single crtc, add a boolean to disable checking only where it doesn't make sense. Note that intel_modeset_setup_hw_state already has a call to intel_modeset_check_state at the end, so we don't reduce the amount of checking. v2: Try harder not to create a big patch (Chris). v3: Even smaller (still Chris). Also fix a trailing space. References: https://lkml.org/lkml/2013/3/16/60 Cc: Tomas Melin <tomas.melin@iki.fi> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Reviewed-by:
Tomas Melin <tomas.melin@iki.fi> Tested-by:
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Ville Syrjälä authored
Increase the number of fence registers to 32 on IVB/HSW. VLV however only has 16 fence registers according to the docs. Increasing the number of fences was attempted before [1], but there was some uncertainty about the maximum CPU fence number for FBC. Since then BSpec has been updated to state that there are in fact 32 fence registers, and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits, and the CPU fence number field in the ILK_DPFC_CONTROL register must be zero. So now it all makes sense. [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html v2: Include some background information based on the previous attempt Signed-off-by:
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Mika Kuoppala authored
commit 4f9b2fe0441d4bdf5666a306156b5d6755de2584 Author: Ben Widawsky <ben@bwidawsk.net> Date: Fri Apr 5 14:29:22 2013 -0700 drm/i915: Better overclock support changed the sysfs read semantics for 'gt_max_freq_mhz'. By always returning overclock max instead of stored value. Fix this by returning the stored value. Separate sysfs entry should be considered for overclocking max freq. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63415 Cc: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: -
Ben Widawsky authored
Looks like a some remnant from a rebase. Signed-off-by:
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Ville Syrjälä authored
BSpec contains several scattered notes which state that the maximum fence stride was increased to 256KB on IVB. Testing on real hardware agrees. Signed-off-by:
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Ville Syrjälä authored
Our checks for an invalid fence stride forgot to guard against zero stride on gen4+. Fix it. v2: Avoid duplicated code (danvet) Signed-off-by:
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Ville Syrjälä authored
IVB and HSW use different encodings for the PPGTT cacheability bits in the GAM_ECOCHK register. Signed-off-by:
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Ville Syrjälä authored
According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as well. Configure it accordingly. Signed-off-by:
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