request_irq() is preferred over setup_irq(). Invocations of setup_irq()
occur after memory allocators are ready.

Per tglx[1], setup_irq() existed in olden days when allocators were not
ready by the time early interrupts were initialized.

Hence replace setup_irq() by request_irq().

[1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos

Link: https://lore.kernel.org/r/20200327124451.4298-1-afzal.mohd.ma@gmail.comSigned-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.7-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

cpuidle: tegra: Changes for v5.7-rc1

These changes unify CPU idle support for Tegra20, Tegra30 and Tegra114.

* tag 'tegra-for-5.7-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  cpuidle: tegra: Disable CC6 state if LP2 unavailable
  cpuidle: tegra: Squash Tegra114 driver into the common driver
  cpuidle: tegra: Squash Tegra30 driver into the common driver
  cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle

Link: https://lore.kernel.org/r/20200313165848.2915133-9-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

arm64: soc: ZynqMP SoC changes for v5.7

- Change firmware dependency to be able to disable it

* tag 'zynqmp-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx:
  arm64: zynqmp: Make zynqmp_firmware driver optional
  include: linux: firmware: Correct config dependency of zynqmp_eemi_ops

Link: https://lore.kernel.org/r/ecef6de5-8318-9f88-db8c-7c33fe44901f@monstr.euSigned-off-by: Arnd Bergmann <arnd@arndb.de>

ARM: Xilinx Zynq SoC patches for v5.7

- Use proper clock header in soc code

* tag 'zynq-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Replace <linux/clk-provider.h> by <linux/of_clk.h>

Link: https://lore.kernel.org/r/005af9f0-85b5-7bac-2d99-5bb3857debb3@monstr.euSigned-off-by: Arnd Bergmann <arnd@arndb.de>

AT91 SoC for 5.7

 - Rework PM to support sam9x60

* tag 'at91-5.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: pm: add quirk for sam9x60's ulp1
  ARM: at91: pm: add plla disable/enable support for sam9x60
  clk: at91: move sam9x60's PLL register offsets to PMC header
  ARM: at91: pm: s/sfr/sfrbu in pm_suspend.S
  ARM: at91: pm: add pmc_version member to at91_pm_data
  ARM: at91: pm: add macros for plla disable/enable
  ARM: at91: pm: revert do not disable/enable PLLA for ULP modes
  ARM: at91: pm: use proper master clock register offset
  ARM: at91: Drop unneeded select of COMMON_CLK

Link: https://lore.kernel.org/r/20200322090116.GA208895@piout.netSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/soc

pmic wrapper:
- add support for MT6779 SoC

cmdq-helper:
- set knows_txdone in mailbox client

* tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: pwrap: add support for MT6359 PMIC
  soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs
  dt-bindings: pwrap: mediatek: add pwrap support for MT6779
  soc: mediatek: knows_txdone needs to be set in Mediatek CMDQ helper

Link: https://lore.kernel.org/r/61165e91-f211-ad37-a81c-cbf3ff69fa1b@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'imx-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc

i.MX SoC changes for 5.7:

 - A number of cleanups from Anson Huang to remove unneeded includes,
   drop unnecessary newlines and base check etc.
 - Apply Cortex-A9 specific errata only to Cortex-A9 based i.MX SoCs
   and avoid impacting Cortex-A7 based designs.

* tag 'imx-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: Drop unnecessary src_base check
  ARM: imx: Remove unnecessary blank lines
  ARM: imx: Add missing of_node_put()
  ARM: imx: Remove unused include of linux/of.h on mach-imx6sl.c
  ARM: imx: Remove unused includes on mach-imx6q.c
  ARM: imx: Remove unused include of linux/irqchip/arm-gic.h
  ARM: imx: limit errata selection to Cortex-A9 based designs

Link: https://lore.kernel.org/r/20200318051918.32579-2-shawnguo@kernel.orgSigned-off-by: Arnd Bergmann <arnd@arndb.de>

mvebu arm for 5.6 (part 1)

Various cleanup:

On Orion5x:
- Drop unneeded select of PCI_DOMAINS_GENERIC
- Remove unneeded variable ret
- Replace setup_irq() by request_irq()

On Dove: Mark dove_io_desc as __maybe_unused

* tag 'mvebu-arm-5.7-1' of git://git.infradead.org/linux-mvebu:
  arm: mach-dove: Mark dove_io_desc as __maybe_unused
  ARM: orion: replace setup_irq() by request_irq()
  ARM: orion5x: ts78xx: Remove unneeded variable ret
  ARM: orion5x: Drop unneeded select of PCI_DOMAINS_GENERIC

Link: https://lore.kernel.org/r/87eetux7um.fsf@FE-laptopSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.7-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

ARM: tegra: Core changes for v5.7-rc1

These patches a preparatory work to move the CPU idle drivers into
drivers/cpuidle.

* tag 'tegra-for-5.7-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: cpuidle: Remove unnecessary memory barrier
  ARM: tegra: cpuidle: Make abort_flag atomic
  ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2
  ARM: tegra: Make outer_disable() open-coded
  ARM: tegra: Rename some of the newly exposed PM functions
  ARM: tegra: Expose PM functions required for new cpuidle driver
  ARM: tegra: Propagate error from tegra_idle_lp2_last()
  ARM: tegra: Change tegra_set_cpu_in_lp2() type to void
  ARM: tegra: Remove pen-locking from cpuidle-tegra20
  ARM: tegra: Add tegra_pm_park_secondary_cpu()
  ARM: tegra: Compile sleep-tegra20/30.S unconditionally

Link: https://lore.kernel.org/r/20200313165848.2915133-5-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

soc/tegra: Changes for v5.7-rc1

These changes implement various clocks that are controlled by the PMC
and add support for configuring the voltage level of some pins (needed
for example to support high-speed modes on the SD/MMC interfaces).

* tag 'tegra-for-5.7-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Cleanup whitespace usage
  soc/tegra: pmc: Add pins for Tegra194
  soc/tegra: Add support for 32 kHz blink clock
  soc/tegra: Add Tegra PMC clocks registration into PMC driver
  dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding
  dt-bindings: phy: tegra-xusb: Add usb-role-switch
  dt-bindings: phy: tegra: Add Tegra194 support
  dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
  dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
  dt-bindings: tegra: Convert Tegra PMC bindings to YAML
  dt-bindings: clock: tegra: Add IDs for OSC clocks

Link: https://lore.kernel.org/r/20200313165848.2915133-3-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'stm32-soc-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/soc

STM32 SoC updates for v5.7, round 1

Highlights:
----------

 - Add early console support for all STM32 SoCs: F4/F7/H7/MP1

* tag 'stm32-soc-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: debug: stm32: add UART early console support for STM32MP1
  ARM: debug: stm32: add UART early console support for STM32H7
  ARM: debug: stm32: add UART early console configuration for STM32F7
  ARM: debug: stm32: add UART early console configuration for STM32F4

Link: https://lore.kernel.org/r/4e427e37-99c9-239a-f3f8-a3bf50eb1eb2@st.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'sunxi-core-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/soc

Allwinner Core Changes for v5.7

Just one change for our mach code for including the correct clk header.

* tag 'sunxi-core-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: sunxi: Replace <linux/clk-provider.h> by <linux/of_clk.h>

Link: https://lore.kernel.org/r/20200313055342.GA19760@wens.csie.orgSigned-off-by: Arnd Bergmann <arnd@arndb.de>

This pull request contains Broadcom ARM64 SoCs changes for 5.7, please
pull the following:

- Geert drops the non-existent HAVE_ARM_ARCH_TIMER symbol select for
  ARCH_BCM2835

* tag 'arm-soc/for-5.7/soc-arm64' of https://github.com/Broadcom/stblinux:
  arm64: bcm2835: Drop select of nonexistent HAVE_ARM_ARCH_TIMER

Link: https://lore.kernel.org/r/20200311212012.9418-4-f.fainelli@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

This pull request contains Broadcom ARM-based SoCs changes for 5.7,
please pull the following:

- Geert drops redundant selects for Broadcom SoCs which are already
  implied by ARCH_MULTI_V6_V7

* tag 'arm-soc/for-5.7/soc' of https://github.com/Broadcom/stblinux:
  ARM: bcm: Drop unneeded select of PCI_DOMAINS_GENERIC, HAVE_SMP, TIMER_OF

Link: https://lore.kernel.org/r/20200311212012.9418-3-f.fainelli@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'omap-for-v5.7/pm33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

PM changes for am335x and am437x for v5.7 merge window

A series of changes from Dave Gerlach to enable basic cpuidle support
for am335x and am437x based on generic cpuidle-arm driver.

* tag 'omap-for-v5.7/pm33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: omap2plus_defconfig: Add CONFIG_ARM_CPUIDLE
  soc: ti: pm33xx: Add base cpuidle support
  ARM: OMAP2+: pm33xx-core: Extend platform_data ops for cpuidle
  ARM: OMAP2+: pm33xx-core: Add cpuidle_ops for am335x/am437x
  dt-bindings: arm: cpu: Add TI AM335x and AM437x enable method

Link: https://lore.kernel.org/r/pull-1583511417-919838@atomide.com-2Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'omap-for-v5.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

SoC changes for omaps for v5.7 merge window

A change to improve the warning output for device tree data
mismatch as compared to legacy platform data for ti-sysc
related interconnect target modules.

And change omap1 to request_irq() instead of setup_irq().

* tag 'omap-for-v5.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP: replace setup_irq() by request_irq()
  ARM: OMAP2+: Improve handling of ti-sysc related sysc_fields

Link: https://lore.kernel.org/r/pull-1583511417-919838@atomide.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'renesas-arm-soc-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc

Renesas ARM SoC updates for v5.7

  - Enable ARM global timer on Cortex-A9 MPCore SoCs,
  - A minor cleanup.

* tag 'renesas-arm-soc-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: shmobile: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  ARM: shmobile: Enable ARM_GLOBAL_TIMER on Cortex-A9 MPCore SoCs

Link: https://lore.kernel.org/r/20200226110221.19288-3-geert+renesas@glider.beSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Without this, we get the warnings below when CONFIG_MMU is disabled:

linux/arch/arm/mach-dove/common.c:51:24: warning: ‘dove_io_desc’ defined
but not used [-Wunused-variable]
static struct map_desc dove_io_desc[] __initdata = {
                       ^~~~~~~~~~~~

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

request_irq() is preferred over setup_irq(). Invocations of setup_irq()
occur after memory allocators are ready.

Per tglx[1], setup_irq() existed in olden days when allocators were not
ready by the time early interrupts were initialized.

Hence replace setup_irq() by request_irq().

[1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanosSigned-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Add support of early console for STM32MP1. Default UART instance is UART4,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

Add support of early console for STM32H7. Default UART instance is USART1,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

Early console is hardcoded on USART1 in current implementation.
With this patch, default UART instance is USART1, but other UART instances
can be configured by setting physical and virtual base addresses in
menuconfig.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

Early console is hardcoded on USART1 in current implementation.
With this patch, default UART instance is USART1, but other UART instances
can be configured by setting physical and virtual base addresses in
menuconfig.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

LP2 suspending could be unavailable, for example if it is disabled in a
device-tree. CC6 cpuidle state won't work in that case.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra20/30/114/124 SoCs have common idling states, thus there is no much
point in having separate drivers for a similar hardware. This patch moves
Tegra114/124 arch/ drivers into the common driver without any functional
changes. The CC6 state is kept disabled on Tegra114/124 because the core
Tegra PM code needs some more work in order to support that state.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra20 and Terga30 SoCs have common C1 and CC6 idling states and thus
share the same code paths, there is no point in having separate drivers
for a similar hardware. This patch merely moves functionality of the old
driver into the new, although the CC6 state is kept disabled for now since
old driver had a rudimentary support for this state (allowing to enter
into CC6 only when secondary CPUs are put offline), while new driver can
provide a full-featured support. The new feature will be enabled by
another patch.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The driver's code is refactored in a way that will make it easy to
support Tegra30/114/124 SoCs by this unified driver later on. The
current functionality is equal to the old Tegra20 driver, only the
code's structure changed a tad. This is also a proper platform driver
now.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

There is no good justification for smp_rmb() after returning from LP2
because there are no memory operations that require SMP synchronization.
Thus remove the confusing barrier.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Replace memory accessors with atomic API just to make code consistent
with the abort_barrier. The new variant may be even more correct now
since atomic_read() will prevent compiler from generating wrong things
like carrying abort_flag value in a register instead of re-fetching it
from memory.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

It is possible that something may go wrong with the secondary CPU, in
that case it is much nicer to get a dump of the flow-controller state
before hanging machine.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The outer_disable() of Tegra's suspend code is open-coded now since
that helper produces spurious warning message about secondary CPUs being
online when CPU enters into LP2 from cpuidle. The secondaries are actually
halted by the cpuidle driver on entering into LP2 idle-state, but the
online status is not touched by the cpuidle. This fixes a storm of
warnings once LP2 idling state is enabled on Tegra30. The outer_disable()
helper has sanity checks for interrupts and secondary CPUs being disabled
and we are pretty confident about the interrupts state during of CPU
idling / system suspend. The rail-off status check is added in this patch
as equivalent for the "num_online_cpus() > 1".
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Rename some of the recently exposed PM functions, prefixing them with
"tegra_pm_" in order to make the naming of the PM functions consistent.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/
directory and it will require all these exposed Tegra PM-core functions.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: fixup missing include rename]
Signed-off-by: Thierry Reding <treding@nvidia.com>

Avoid using a mixture of tabs and spaces within tables to make them
easier to read and more consistently formatted.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Extend the Tegra194 IO pad table with additional information such as pin
names and 1.8/3.3 V settings to allow a table of voltage control pins to
generated from it. This is similar to what's done for older chips and is
needed to support high-speed modes for SDHCI where switching the pins to
1.8V or 3.3V is necessary.
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra PMC has blink control to output 32 kHz clock out to Tegra blink
pin. Blink pad DPD state and enable controls are part of Tegra PMC
register space.

Currently Tegra clock driver registers blink control by passing PMC
address and register offset to clk_register_gate which performs direct
PMC access during clk_ops and with this when PMC is in secure mode, any
access from non-secure world does not go through.

This patch adds blink control registration to the Tegra PMC driver using
PMC specific clock gate operations that use tegra_pmc_readl() and
tegra_pmc_writel() to support both secure mode and non-secure
mode PMC register access.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.

With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.

This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.

clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add device-tree binding documentation for the XUSB device mode controller
present on Tegra210 and Tegra186 SoC. This controller supports the USB 3.0
specification.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>