- 24 Apr, 2018 12 commits
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Lin Huang authored
AUX errors are caused by many different reasons. We may not know what happened in aux channel on failure, so let's reset aux channel if some errors occurred. Cc: 征增 王 <wzz@rock-chips.com> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
Lin Huang <hl@rock-chips.com> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
Thierry Escande <thierry.escande@collabora.com> Reviewed-by:
Andrzej Hajda <a.hajda@samsung.com> Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by:
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zain wang authored
There are some different bits between Rockchip and Exynos in register "AUX_PD". This patch fixes the incorrect operations about it. Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
zain wang <wzz@rock-chips.com> Signed-off-by:
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Lin Huang authored
We need to check the dpcd write/read return value to see whether the write/read was successful Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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zain wang authored
Enhanced mode is required by the eDP 1.2 specification, and not doing it early could result in a period of time where we have a link transmitting idle packets without it. Since there is no reason to disable it, we just enable it at the beginning of link training and then keep it on all the time. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
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Lin Huang authored
There was a 1ms delay to detect the hpd signal, which is too short to detect a short pulse. This patch extends this delay to 100ms. Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: 征增 王 <wzz@rock-chips.com> Signed-off-by:
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Lin Huang authored
When panel is shut down, we should make sure edp can be disabled to avoid undefined behavior. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
Following the correct power up sequence: dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00 Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker must first detect that the HPD signal is asserted high by the Downstream Device before establishing a link with it. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
When we enable bridge failed, we have to retry it, otherwise we would get the abnormal display. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
Panel would reset its setting when it powers down. It would forget the last succeeded link training setting. So we can't use the last successful link training setting to do fast link training. Let's reset fast_train_enable in analogix_dp_bridge_disable(); Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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Lin Huang authored
We should check AUX_EN bit to confirm the AUX CH operation is completed. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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Lin Huang authored
We need to enable video before analogix_dp_is_video_stream_on(), so we can get the right video stream status. We needed to increase the delay in the timeout loop because there is random "Timeout of video streamclk ok" message happen when debug edp panel, this time do not define in the spec. Cc: 征增 王 <wzz@rock-chips.com> Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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- 23 Apr, 2018 7 commits
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Stefan Schake authored
Now that we set the OLED* registers to do CTM, it's helpful to have them in the register dump. Signed-off-by:
Stefan Schake <stschake@gmail.com> Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
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Stefan Schake authored
The hardware has a single block for applying a CTM prior to gamma lut. It can be fed with pixels from one of our CRTC at a time and uses a matrix with S0.9 scalars. Use private atomic state to reject attempts from userland to apply CTM for more than one CRTC at a time and reject matrices with scalars that we can't approximate without integer bits. Signed-off-by:
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Stefan Schake authored
The HVS supports mixing fixed alpha with per-pixel alpha or setting a fixed plane alpha in case there is no per-pixel information. This allows us to support the generic DRM plane alpha property. Signed-off-by:
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Wolfram Sang authored
We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Boris Brezillon authored
Document the bindings used for the Cadence DSI bridge. Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180421070846.10330-2-boris.brezillon@bootlin.com
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Boris Brezillon authored
Add a driver for Cadence DPI -> DSI bridge. This driver only support a subset of Cadence DSI bridge capabilities. This driver has been tested/debugged in a simulated environment which explains why some of the features are missing. Here is a non-exhaustive list of missing features: * burst mode * DPHY init/configuration steps * support for additional input interfaces (SDI input) DSI commands and non-burst video mode have been tested. Signed-off-by:
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Fabio Estevam authored
platform_driver does not need to set the owner field, as this will be populated by the driver core. Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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- 20 Apr, 2018 2 commits
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Jacopo Mondi authored
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel output converter. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by:
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Jacopo Mondi authored
Document Thine THC63LVD1024 LVDS decoder device tree bindings. Signed-off-by:
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- 19 Apr, 2018 4 commits
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Philippe CORNU authored
Add SPDX identifiers to the Synopsys DesignWare MIPI DSI host controller driver. Signed-off-by:
Philippe Cornu <philippe.cornu@st.com> Acked-by:
Philippe Ombredanne <pombredanne@nexB.com> Reviewed-by:
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Philippe CORNU authored
Fix the warning "warn: variable dereferenced before check 'crtc' (see line 390)" by removing unnecessary checks as ltdc_crtc_update_clut() is only called from ltdc_crtc_atomic_flush() where crtc and crtc->state are not NULL. Many thanks to Dan Carpenter for the bug report https://lists.freedesktop.org/archives/dri-devel/2018-February/166918.htmlSigned-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
yannick fertre <yannick.fertre@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180410135312.3553-1-philippe.cornu@st.com
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Philippe CORNU authored
This patch adds the user update information in frames-per-second into the drm debugfs plane state. Signed-off-by:
Vincent Abriou <vincent.abriou@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180407213503.30932-1-philippe.cornu@st.com
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Philippe CORNU authored
enable/disable_vblank() functions at drm_driver level are deprecated. Move them to the ltdc drm_crtc_funcs structure. Signed-off-by:
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- 18 Apr, 2018 2 commits
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Oleksandr Andrushchenko authored
It turns out this was only needed to paper over a bug in the CMA helpers, which was addressed in commit 998fb1a0 Author: Liviu Dudau <Liviu.Dudau@arm.com> Date: Fri Nov 10 13:33:10 2017 +0000 drm: gem_cma_helper.c: Allow importing of contiguous scatterlists with nents > 1 Without this the following pipeline didn't work: domU: 1. xen-front allocates a non-contig buffer 2. creates grants out of it dom0: 3. converts the grants into a dma-buf. Since they're non-contig, the scatter-list is huge. 4. imports it into rcar-du, which requires dma-contig memory for scanout. -> On this given platform there's an IOMMU, so in theory this should work. But in practice this failed, because of the huge number of sg entries, even though the IOMMU driver mapped it all into a dma-contig range. With a guest-contig buffer allocated in step 1, this problem doesn't exist. But there's technically no reason to require guest-contig memory for xen buffer sharing using grants. Given all that, the xen-front cma support is not needed and should be removed. Signed-off-by:
Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Suggested-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
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Boris Brezillon authored
->atomic_async_update() requires that drivers update the plane->state object before returning. Make sure at least common properties have been updated. Cc: Gustavo Padovan <gustavo@padovan.org> Signed-off-by:
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- 17 Apr, 2018 5 commits
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Gustavo Padovan authored
Add support for async updates of cursors by using the new atomic interface for that. Basically what this commit does is do what vc4_update_plane() did but through atomic. v7: Place the drm_atomic_set_fb_for_plane() call after the new FB has been applied to the HW to avoid possible use-after-free issues v6: add missing drm_atomic_set_fb_for_plane() in vc4_plane_atomic_async_update() (Boris Brezillon) v5: add missing call to vc4_plane_atomic_check() (Eric Anholt) v4: add drm_atomic_helper_async() commit (Eric Anholt) v3: move size checks back to drivers (Ville Syrjälä) v2: move fb setting to core and use new state (Eric Anholt) Signed-off-by:Gustavo Padovan <gustavo.padovan@collabora.com> Reviewed-by:
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Stefan Schake authored
We need to access the channel for configuring our CTM hardware. Signed-off-by:
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Stefan Schake authored
We are an atomic driver so the gamma LUT should also be exposed as a CRTC property through the DRM atomic color management. This will also take care of the legacy path for us. Signed-off-by:
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Eric Anholt authored
At least the RGBA expand field we should have been setting, because we aren't expanding correctly for 565 -> 8888. Other registers are ones that may be interesting for various projects that have been discussed. Signed-off-by:
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John Keeping authored
We have seen a case of a bad reference count for vblanks with the Rockchip VOP: ------------[ cut here ]------------ WARNING: CPU: 1 PID: 383 at drivers/gpu/drm/drm_irq.c:1198 drm_vblank_put+0x40/0xcc Modules linked in: brcmfmac brcmutil CPU: 1 PID: 383 Comm: kworker/u8:2 Not tainted 4.9.75-rt60 #1 Hardware name: Rockchip (Device Tree) Workqueue: events_unbound flip_worker Backtrace: [<c010b7b0>] (dump_backtrace) from [<c010ba4c>] (show_stack+0x18/0x1c) r7:c0b1b13c r6:600b0013 r5:00000000 r4:c0b1b13c [<c010ba34>] (show_stack) from [<c032d248>] (dump_stack+0x78/0x94) [<c032d1d0>] (dump_stack) from [<c011e6e8>] (__warn+0xe4/0x104) r7:00000009 r6:c03cf26c r5:00000000 r4:00000000 [<c011e604>] (__warn) from [<c011e7c0>] (warn_slowpath_null+0x28/0x30) r9:eeb443a0 r8:eeb443c8 r7:ee8a5ec0 r6:ee8a5ec0 r5:edb47f00 r4:ee096200 [<c011e798>] (warn_slowpath_null) from [<c03cf26c>] (drm_vblank_put+0x40/0xcc) [<c03cf22c>] (drm_vblank_put) from [<c03cf310>] (drm_crtc_vblank_put+0x18/0x1c) r5:edb47f00 r4:ee3c8a80 [<c03cf2f8>] (drm_crtc_vblank_put) from [<c03ef9b4>] (vop_fb_unref_worker+0x18/0x24) [<c03ef99c>] (vop_fb_unref_worker) from [<c03df194>] (flip_worker+0x98/0xb4) r5:edb47f00 r4:eeb443a8 [<c03df0fc>] (flip_worker) from [<c0134808>] (process_one_work+0x1a8/0x2fc) r9:00000000 r8:ee807d00 r7:00000000 r6:ee809c00 r5:eeb443a8 r4:edfe5f80 [<c0134660>] (process_one_work) from [<c01358ec>] (worker_thread+0x2ac/0x458) r10:00000088 r9:edfe5f98 r8:ee809c2c r7:c0b04100 r6:ee809c00 r5:ee809c00 r4:edfe5f80 [<c0135640>] (worker_thread) from [<c013a0bc>] (kthread+0xfc/0x10c) r10:00000000 r9:00000000 r8:c0135640 r7:edfe5f80 r6:00000000 r5:edf0e240 r4:ee8a4000 r3:ed194e00 [<c0139fc0>] (kthread) from [<c0107cb8>] (ret_from_fork+0x14/0x3c) r8:00000000 r7:00000000 r6:00000000 r5:c0139fc0 r4:edf0e240 ---[ end trace 0000000000000002 ]--- It seems that this is caused by unfortunate timing between vop_crtc_atomic_flush() and vop_handle_vblank() given the following ordering: atomic_flush handle_vblank ------------ ------------- drm_flip_work_queue set_bit if (test_and_clear_bit(...)) drm_flip_work_commit drm_vblank_get This results in vop_fb_unref_worker (called as flip work) decrementing the vblank refcount before it has been incremented. Signed-off-by:
John Keeping <john@metanate.com> Reviewed-by:
Sandy huang <hjc@rock-chips.com> Signed-off-by:
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- 16 Apr, 2018 5 commits
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Maxime Ripard authored
Now that we moved the rcar-du DRM driver has been switched to the generic alpha property, remove the former property documentation from the deprecated CSV file. Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/04be5e2256aa8d33d9521a68a10f0b73a24f8040.1523432341.git-series.maxime.ripard@bootlin.com
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Maxime Ripard authored
Our backend supports a per-plane alpha property. Support it through our new helper. Acked-by:
Chen-Yu Tsai <wens@csie.org> Reviewed-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
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Maxime Ripard authored
Now that we have support for per-plane alpha in the core, let's use it. Acked-by:
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Maxime Ripard authored
Now that we have support for per-plane alpha in the core, let's use it. Acked-by:
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Maxime Ripard authored
Some drivers duplicate the logic to create a property to store a per-plane alpha. This is especially useful if we ever want to support extra protocols for Wayland like: https://lists.freedesktop.org/archives/wayland-devel/2017-August/034741.html Let's create a helper in order to move that to the core. Acked-by:
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- 11 Apr, 2018 3 commits
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Maxime Ripard authored
The DSI controller needs a particular interface (CPU aka 8080) with some modifications from the TCON in order to run. Make sure the TCON is able to provide it when we are using the DSI output. Reviewed-by:
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Maxime Ripard authored
Most of the Allwinner SoCs since the A31 share the same MIPI-DSI controller. While that controller is mostly undocumented, the code is out there and has been cleaned up in order to be integrated into DRM. However, there's still some dark areas that are a bit unclear about how the block exactly operates. Reviewed-by:
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Maxime Ripard authored
The Allwinner SoCs usually come with a DSI encoder. Add a binding for it. Reviewed-by:
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