- 24 May, 2019 40 commits
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Slava Abramov authored
v1: replace casting to unsigned long with div64_ul Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Slava Abramov <slava.abramov@amd.com> Tested-by:
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Chengming Gui authored
add pm_enabled to control the dpm off/on. v2: Directly return 0 to replace return ret and merge some check code. Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
This fixes the warning below error: ‘feature_mask’ may be used uninitialized in this function [-Werror=maybe-uninitialized] *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^ (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK)); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reviewed-by:Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a DRM_ERROR error message. Fix this. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
If RAS or XGMI are enabled, you have to use mode1 reset rather than BACO. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Paul Hsieh authored
[Why] When disable driver, OS will set backlight optimization then do stop device. But this flag will cause driver to enable ABM when driver disabled. [How] Send ABM disable command before destroy ABM construct Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Jun Lei authored
move the update of otg instance outside of hw programming logic, since this is sw state, it should always be updated and should never be optimized away. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] The bit for flip addr is being set causing the determination for FAST vs MEDIUM to always return MEDIUM when plane info is provided as a surface update. This causes extreme stuttering for the typical atomic update path on Linux. [How] Don't use update_flags->raw for determining FAST vs MEDIUM. It's too fragile to changes like this. Explicitly specify the update type per update flag instead. It's not as clever as checking the bits itself but at least it's correct. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Eryk Brol <Eryk.Brol@amd.com> Signed-off-by:
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Joshua Aberback authored
Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Aric Cyr authored
DPRX should send the VCP extended colorimetry packet if the sink supports DPCD rev1.4 and reports the extended colorimetry bit. Signed-off-by:
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Wesley Chalmers authored
[WHY] DCN code should make as few references to DCE as possible [HOW] Copy DCE110 implementation of find_first_free_match_stream_enc_for_link into DCN10 Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] From DCE110 onward, we have the ability to assign DIG BE and FE separately for any display connector type; before, we could only do this for DP. Signed-off-by:
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Charlene Liu authored
[Why] 1. No real HPD plug in/out but HPD happens, the driver notifies OS connection changed. 2. No display in target. When HPD goes low to high, the driver should regard as HPD and enter setmode flow. [How] In this case, even stream didn't change but still retrain. Signed-off-by:
Chiawen Huang <chiawen.huang@amd.com> Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected by the prefetching requirements on all pipes, so the position might change when we do memory request control on another pipe, so we need to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP. [How] - refactor VTG_CONTROL programming into a new function "set_vtg_params" - call it after calling "program_global_sync" - make sure it's called after because it relies on the cached dlg params Signed-off-by: -
Dmytro Laktyushkin authored
* add plane state null checks * add and set update surface flags Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Vitaly Prosyak authored
[Why & How] Reuse existent code path and in order to do that apply de gamma in 1D blender LUT and re use MPC OGAM. Follow up is required. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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SivapiriyanKumarasamy authored
[Why] The DPMS state of a display should not impact whether we want to enable fast boot. Currently fast boot is not enabled when resuming from S4 because of this. [How] Remove check for DPMS state when determining if fast boot can be applied. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Many IGT tests require CRC capture in order to confirm that the output is visually correct. These skip on dce120 because configure_crc and get_crc aren't set. [How] Hook up is_tg_enabled, configure_crc and get_crc functions on dce120's timing generator. The logic should be the same as DCE and DCN with some minor register naming differences. Signed-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Charlene Liu authored
add these parameters for future use Signed-off-by:
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Evan Quan authored
Support hotspot and memory temperature retrieval on sw smu routine. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Support realtime uclk activity report. Signed-off-by:
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Evan Quan authored
Request too frequently may get corrupt data. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
Support ppfeatures sysfs interface on Vega20 sw smu routine. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Evan Quan authored
smu_get_clk_info_from_vbios() was called repeatedly. It seems a merge error. Signed-off-by:
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Evan Quan authored
There is already sw smu check on IP block adding. Signed-off-by:
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Harry Wentland authored
[WHY] These were only needed for bringup. They're not needed anymore. Signed-off-by:
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Harry Wentland authored
[WHY] Some early Raven boards had a bad SBIOS that doesn't play nicely with the DMCU FW. We thought the issues were fixed by ignoring errors on DMCU load but that doesn't seem to be the case. We've still seen reports of users unable to boot their systems at all. [HOW] Disable DMCU load on Raven 1. Only load it for Raven 2 and Picasso. v2: Fix ifdef (Alex) Signed-off-by:
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Harry Wentland authored
[WHY] We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1. Signed-off-by:
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Ori Messinger authored
Firmware versions can be found as separate sysfs files at: /sys/class/drm/cardX/device/fw_version (where X is the card number) The firmware versions are displayed in hexadecimal. v2: Moved sysfs files to subfolder Signed-off-by:
Ori Messinger <ori.messinger@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Leo Liu authored
It should be attached to VCN 1.0 Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
Since this is VCN specific and only used by VCN Signed-off-by:
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Tiecheng Zhou authored
it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by:
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Monk Liu authored
only report once per TMO job and the timer would be restarted upon the job finished if it's just slow. Suggested-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Christian König authored
As far as we know this was never used by userspace and so should be removed. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Evan Quan authored
Update Vega10 ACG Avfs GB parameters. Signed-off-by:
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Evan Quan authored
On OD reset, the clock tables in SMU need to be reset to default. Signed-off-by:
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Evan Quan authored
Update Vega10 top performance level power state accordingly on OD. Signed-off-by:
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Evan Quan authored
No need to enable or disable AVFS if it's already in wanted state. Signed-off-by:
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