- 31 Oct, 2023 7 commits
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Suraj Kandpal authored
Rename hdcp 1.4 enablement function from _intel_hdcp_enable to intel_hdcp1_enable to better represent what version of hdcp is being enabled Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231026121139.987437-2-suraj.kandpal@intel.com
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Ville Syrjälä authored
We are asked to reprogram PEG_BAND_GAP_DATA prior to enabling hotplug detection on the g45 HDMI/DP ports. Currently we do said reprogamming from the DP/HDMI connector initialization functions. That code should be mostly platform agnostic so clearly not the best place for this. Move the workaround to the place where we actually enable HPD detection. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231012124033.26983-1-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
We have a bit of duplicated code around the DPLL disabling. Extract that to a new function, and for symmetry also do the same for the enable direction. Signed-off-by:
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Ville Syrjälä authored
The extra DPLL power domain is currently handled in three places: - combo_pll_enable() - combo_pll_disable() - readout_dpll_hw_state() First two of those are low level PLL funcs, but the third is a higher level thing. So the current situation is rather inconsistent. Unify this by moving the PLL enable/disable up one level. This also means the extra power domain could be trivially be used by other platforms as well. Signed-off-by:
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Ville Syrjälä authored
Just include the JSL/EHL DPLL4 extra power domain in the dpll_info struct. This way the same approach could be used by other platforms as well (should the need arise), and we don't have to sprinkle platform checks all over the place. Note that I'm perhaps slightly abusing things here as power_domain==0 (which is actually POWER_DOMAIN_DISPLAY_CORE) now indicates that no extra power domain is needed. I suppose using POWER_DOMAIN_INVALID would be more correct, but then we'd have to sprinkle that to all the other DPLLs. Signed-off-by:
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Ville Syrjälä authored
Use named initializers when populating the DPLL info. This is just more convenient and less error prone as we no longer have to keep the initializers in a specific order. Signed-off-by:
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Ville Syrjälä authored
Apparently some BDW machines (eg. HP Pavilion 15-ab) shipped with a VBT inherited from some earlier HSW model. On HSW the HDMI level shift value could go up to 11, whereas on BDW the maximum value is 9. The DDI code does clamp the bogus value, but it does so with a WARN which we don't really want. To avoid that let's just sanitize the bogus VBT HDMI level shift value ahead of time for all BDW machines. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9461Signed-off-by:
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- 30 Oct, 2023 3 commits
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Jani Nikula authored
Keep the display build lists together. v2: Rebase Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Signed-off-by:
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Jani Nikula authored
Unify the line continuations and indents, and sort the build lists. Reviewed-by:
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Chaitanya Kumar Borah authored
eDP specification supports HBR3 link rate since v1.4a. Moreover, C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. Cc: <stable@vger.kernel.org> BSpec: 70073 74224 Signed-off-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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- 29 Oct, 2023 4 commits
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Lucas De Marchi authored
As done with the hw readout, properly abstract the C10/C20 phy details inside intel_cx0_phy.c. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231018222831.4132968-3-lucas.demarchi@intel.com
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Lucas De Marchi authored
intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking it to the rest of the driver. Start abstracting this by exporting a single PLL hw readout that handles the differences between C20 and C10 internally to that compilation unit. Signed-off-by:
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Lucas De Marchi authored
With MTL adding PICA between the port and the real phy, the path add for DG2 stopped being followed and newer platforms are simply using the older path for TC phys. LNL is no different than MTL in this aspect, so just add it to the mess. In future the phy and port designation and deciding if it's TC should better be cleaned up. To make it just a bit better, also change intel_phy_is_snps() to show this is DG2-only. Signed-off-by:
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Lucas De Marchi authored
For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() accordingly. This reverts the change in commit e388ae97 ("drm/i915/display: Eliminate IS_METEORLAKE checks") that turned that into a display engine version check. The phy <-> port connection is very SoC-specific and not related to that version. IS_LUNARLAKE() is defined to 0 in i915 as it's expected that the (upcoming) xe driver is the one defining the platform, with i915 only driving the display side. Bspec: 70818 Reviewed-by:
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- 27 Oct, 2023 1 commit
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Jani Nikula authored
Move sprite_name() where its only user is, and convert it to a function, removing the implicit dev_priv usage. Signed-off-by:
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- 26 Oct, 2023 25 commits
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Mika Kahola authored
Every know and then we receive the following error when running for example IGT test kms_flip. [drm] *ERROR* PHY G Read 0d80 failed after 3 retries. [drm] *ERROR* PHY G Write 0d81 failed after 3 retries. Since the error is sporadic in nature, the patch proposes to reset the message bus after every successful or unsuccessful read or write operation. v2: Add FIXME's to indicate the experimental nature of this workaround (Rodrigo) v3: Dropping the additional delay as moving reset to *_read_once() and *_write_once() functions seem unnecessary delay Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231016125544.719963-1-mika.kahola@intel.com
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Vinod Govindapillai authored
Display device and display runtime info is exposed as part of i915_display_capabilities debugfs entry. Remove this information from i915_ capabilities as it is now reduntant. Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
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Jouni Högander authored
Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Acked-by:
Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231024124109.384973-24-jouni.hogander@intel.com
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Jouni Högander authored
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Jouni Högander authored
v2: Change device parameter permissions to 0400 Cc: Luca Coelho <luciano.coelho@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jouni Högander authored
Also make module parameter as non writable. Signed-off-by:
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
Move enable_ips module parameter under display and change it as boolean. v2: - Change enable_ip as boolean - Fix copy paste error (i915_param -> intel_display_param) Signed-off-by:
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Jouni Högander authored
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Jouni Högander authored
Move enable_sagv module parameter under display and change the parameter permissions to non-writblase (0400) v2: Change permissions to 0400 Signed-off-by:
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
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Jouni Högander authored
Move psr related module parameters under display. Also fix error in enable_psr2_sel_fetch module parameter descrtiption. It was saying disabled by default while it's vice versa. Also psr_safest_params was missing default value in description. This is now added. v2: - Fix enable_psr2_sel_fetch description. - Add default value into psr_safest_params description. Signed-off-by:
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Jouni Högander authored
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Jouni Högander authored
GPU error dump contained all module parameters. If we are moving display parameters to intel_display_params.[ch] they are not dumped into GPU error dump. This patch is adding moved display parameters back to GPU error dump. Display parameters are also included in i915_capabilities v2: Add parameters to i915_capabilities as well Signed-off-by:
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Jouni Högander authored
Currently all module parameters are handled by i915_param.c/h. This is a problem for display parameters when Xe driver is used. Add a mechanism to add parameters specific to the display. This is mainly copied from i915_[debugfs]_params.[ch]. Parameters are not yet moved. This is done by subsequent patches. v2: - Drop unused predefinition (dentry) - Clarify need for empty INTEL_DISPLAY_PARAMS_FOR_EACH in comment Signed-off-by:
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