1. 11 Feb, 2021 1 commit
  2. 08 Feb, 2021 5 commits
  3. 05 Feb, 2021 8 commits
  4. 04 Feb, 2021 4 commits
  5. 27 Jan, 2021 1 commit
  6. 26 Jan, 2021 1 commit
  7. 22 Jan, 2021 2 commits
  8. 21 Jan, 2021 4 commits
  9. 19 Jan, 2021 1 commit
  10. 15 Jan, 2021 2 commits
    • Mark Brown's avatar
      Merge series "Remove ARM platform efm32" from Uwe Kleine-König <u.kleine-koenig@pengutronix.de> · de634b89
      Mark Brown authored
      Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de>:
      
      From: Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de>
      
      Hello,
      
      there are no known active users of the efm32 platform. Given that the
      only machine that is supported has only 4 MiB of RAM its use is also
      quite limited.
      
      Back then it served as the platform to develop ARMv7-M support in Linux
      which was quite fun and still is a blissful memory.
      
      Still given that the code serves no purpose and this probably won't
      change anytime soon, remove all platform support.
      
      I'm unsure what to do with the device tree bindings. Should we delete
      them, too?
      
      Best regards
      Uwe
      
      Uwe Kleine-König (7):
        ARM: drop efm32 platform
        clk: Drop unused efm32gg driver
        clocksource: Drop unused efm32 timer code
        spi: Drop unused efm32 bus driver
        i2c: Drop unused efm32 bus driver
        tty: Drop unused efm32 serial driver
        MAINTAINERS: Remove deleted platform efm32
      
       MAINTAINERS                              |   7 -
       arch/arm/Kconfig                         |  10 +-
       arch/arm/Kconfig.debug                   |  17 -
       arch/arm/Makefile                        |   1 -
       arch/arm/boot/dts/Makefile               |   2 -
       arch/arm/boot/dts/efm32gg-dk3750.dts     |  88 ---
       arch/arm/boot/dts/efm32gg.dtsi           | 177 -----
       arch/arm/configs/efm32_defconfig         |  98 ---
       arch/arm/include/debug/efm32.S           |  45 --
       arch/arm/mach-efm32/Makefile             |   2 -
       arch/arm/mach-efm32/Makefile.boot        |   4 -
       arch/arm/mach-efm32/dtmachine.c          |  16 -
       arch/arm/mm/Kconfig                      |   1 -
       drivers/clk/Makefile                     |   1 -
       drivers/clk/clk-efm32gg.c                |  84 ---
       drivers/clocksource/Kconfig              |   9 -
       drivers/clocksource/Makefile             |   1 -
       drivers/clocksource/timer-efm32.c        | 278 --------
       drivers/i2c/busses/Kconfig               |   7 -
       drivers/i2c/busses/Makefile              |   1 -
       drivers/i2c/busses/i2c-efm32.c           | 469 -------------
       drivers/spi/Kconfig                      |   7 -
       drivers/spi/Makefile                     |   1 -
       drivers/spi/spi-efm32.c                  | 462 ------------
       drivers/tty/serial/Kconfig               |  13 -
       drivers/tty/serial/Makefile              |   1 -
       drivers/tty/serial/efm32-uart.c          | 852 -----------------------
       include/linux/platform_data/efm32-spi.h  |  15 -
       include/linux/platform_data/efm32-uart.h |  19 -
       include/uapi/linux/serial_core.h         |   3 -
       30 files changed, 1 insertion(+), 2690 deletions(-)
       delete mode 100644 arch/arm/boot/dts/efm32gg-dk3750.dts
       delete mode 100644 arch/arm/boot/dts/efm32gg.dtsi
       delete mode 100644 arch/arm/configs/efm32_defconfig
       delete mode 100644 arch/arm/include/debug/efm32.S
       delete mode 100644 arch/arm/mach-efm32/Makefile
       delete mode 100644 arch/arm/mach-efm32/Makefile.boot
       delete mode 100644 arch/arm/mach-efm32/dtmachine.c
       delete mode 100644 drivers/clk/clk-efm32gg.c
       delete mode 100644 drivers/clocksource/timer-efm32.c
       delete mode 100644 drivers/i2c/busses/i2c-efm32.c
       delete mode 100644 drivers/spi/spi-efm32.c
       delete mode 100644 drivers/tty/serial/efm32-uart.c
       delete mode 100644 include/linux/platform_data/efm32-spi.h
       delete mode 100644 include/linux/platform_data/efm32-uart.h
      
      base-commit: 5c8fe583
      --
      2.29.2
      
      _______________________________________________
      linux-arm-kernel mailing list
      linux-arm-kernel@lists.infradead.org
      http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
      de634b89
    • Uwe Kleine-König's avatar
      spi: Drop unused efm32 bus driver · 0ba882ae
      Uwe Kleine-König authored
      Support for this machine was just removed, so drop the now unused spi
      bus driver, too.
      Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Link: https://lore.kernel.org/r/20210114151630.128830-5-u.kleine-koenig@pengutronix.deSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      0ba882ae
  11. 14 Jan, 2021 4 commits
  12. 13 Jan, 2021 7 commits
    • Mark Brown's avatar
      Merge v5.11-rc3 · e4aad999
      Mark Brown authored
      e4aad999
    • Richard Fitzgerald's avatar
      spi: bcm2835: Set controller max_speed_hz · c6892892
      Richard Fitzgerald authored
      Set the struct spi_controller max_speed_hz. This is based on the
      reported source clock frequency during probe. The maximum bus clock
      is half the source clock (as per the code in bcm2835_spi_transfer_one).
      Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
      Link: https://lore.kernel.org/r/20210107164825.21919-1-rf@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      c6892892
    • Mark Brown's avatar
      Merge series "spi: sh-msiof: Advertize bit rate limits and actual speed" from... · 72366b3c
      Mark Brown authored
      Merge series "spi: sh-msiof: Advertize bit rate limits and actual speed" from Geert Uytterhoeven <geert+renesas@glider.be>:
      
      	Hi Mark,
      
      This patch series makes the Renesas MSIOF SPI driver fill in actual
      transfer speeds and controller limits, so the SPI core can take them
      into account.
      
      This has been tested on R-Car Gen2 and Gen3.
      Thanks!
      
      Geert Uytterhoeven (2):
        spi: sh-msiof: Fill in spi_transfer.effective_speed_hz
        spi: sh-msiof: Fill in controller speed limits
      
       drivers/spi/spi-sh-msiof.c | 14 +++++++++++---
       1 file changed, 11 insertions(+), 3 deletions(-)
      
      --
      2.25.1
      
      Gr{oetje,eeting}s,
      
      						Geert
      
      --
      Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
      
      In personal conversations with technical people, I call myself a hacker. But
      when I'm talking to journalists I just say "programmer" or something like that.
      							    -- Linus Torvalds
      72366b3c
    • Mark Brown's avatar
      Merge series "spi: cadence-quadspi: Add QSPI controller support for Intel LGM... · 10f48a12
      Mark Brown authored
      Merge series "spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC" from "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>:
      
      Add QSPI controller support for Intel LGM SoC.
      
      Patches to move move bindings over to
      "Documentation/devicetree/bindings/spi/" directory and also added compatible
      Support for Intel platform.
      
      dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
      (earlier patch mail thread and Ack-by)
      link: "https://lore.kernel.org/lkml/5d6d1b85.1c69fb81.96938.0315@mx.google.com/"
      
      Reference:
              https://lkml.org/lkml/2020/6/1/50
      ---
      v9:
        - Vignesh review comments address and update
        - Retain the patchv4 move the binding documentation from mtd to spi
          directory.
        - Add intel's compatible string over the legacy documentation
        - Remove unused variable, CQSPI_SUPPORTS_MULTI_CHIPSELECT macro and check
        - YAML convertion patch alone dropped
      v8:
        - As Mark suggested to add the dt-bindings documentation patches
          end of the series , so dropped.
      v7:
        - Rob's review comments address and fixed dt-schema warning
        - Pratyush review comments address and update
        - DAC bit reset to 0 and 1 (enable/disable)
        - tested QSI-NOR flash mx25l12805d on LGM soc, it's working after disable DAC
        - Linus suggested to use 'num-cs' prperty instead of 'num-chipselect'
      v6:
        - Rob's review comments update
        - add compatible string in properly aligned
        - remove cadence-qspi extra comaptible string in example
      v5:
        - Rob's review comments update
        - const with single compatible string kept
      v4:
        - Rob's review comments update
        - remove '|' no formatting to preserve
        - child node attributes follows under 'properties' under '@[0-9a-f]+$'.
      v3:
        - Pratyush review comments update
        - CQSPI_SUPPORTS_MULTI_CHIPSELECT macro used instead of cqspi->use_direct_mode
        - disable DAC support placed in end of controller_init
      v2:
        - Rob's review comments update for dt-bindings
        - add 'oneOf' for compatible selection
        - drop un-neccessary descriptions
        - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema
        - remove 'allOf' in not required place
        - add AdditionalProperties false
        - add minItems/maxItems for qspi reset attributes
      
      resend-v1:
        - As per Mark's suggestion , reorder the patch series 1-3 driver
          support patches, series 4-6 dt-bindings patches.
      v1:
        - initial version
      
      Ramuthevar Vadivel Murugan (5):
        spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
        spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
        spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
        spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
        dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
      
       .../bindings/{mtd => spi}/cadence-quadspi.txt      |  1 +
       drivers/spi/Kconfig                                |  2 +-
       drivers/spi/spi-cadence-quadspi.c                  | 24 ++++++++++++++++++----
       3 files changed, 22 insertions(+), 5 deletions(-)
       rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (97%)
      
      --
      2.11.0
      
      ______________________________________________________
      Linux MTD discussion mailing list
      http://lists.infradead.org/mailman/listinfo/linux-mtd/
      10f48a12
    • Marek Vasut's avatar
      spi: stm32: Simplify stm32h7_spi_prepare_fthlv() · 970e8eaa
      Marek Vasut authored
      Simplify stm32h7_spi_prepare_fthlv() function implementation,
      no functional change intended.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Alain Volmat <alain.volmat@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Amelie Delaunay <amelie.delaunay@st.com>
      Cc: Antonio Borneo <antonio.borneo@st.com>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
      Cc: Roman Guskov <rguskov@dh-electronics.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-stm32@st-md-mailman.stormreply.com
      To: linux-spi@vger.kernel.org
      Link: https://lore.kernel.org/r/20210104123114.261596-1-marex@denx.deSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      970e8eaa
    • Stephen Boyd's avatar
      spi: spi-qcom-qspi: Use irq trigger flags from firmware · eaecba87
      Stephen Boyd authored
      We don't need to force this to be trigger high here, as the firmware
      properly configures the irq flags already. Drop it to save a line.
      
      Cc: Douglas Anderson <dianders@chromium.org>
      Cc: Rajendra Nayak <rnayak@codeaurora.org>
      Cc: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
      Cc: Akash Asthana <akashast@codeaurora.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
      Link: https://lore.kernel.org/r/20210112001301.687628-1-swboyd@chromium.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      eaecba87
    • Yicong Yang's avatar
      spi: hisi-sfc-v3xx: extend version checking compatibility · 566c6120
      Yicong Yang authored
      Currently we use concrete version to determine the max_cmd_dword.
      New entries should be added for compatible hardwares of new version
      or on new platform, otherwise the device will use 16 dwords instead
      of 64 even if it supports, which will degrade the performance.
      This will decrease the compatibility and the maintainability.
      
      Drop the switch-case statement of the version checking. Only version
      less than 0x351 supports maximum 16 command dwords.
      Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
      Acked-by: default avatarJohn Garry <john.garry@huawei.com>
      Link: https://lore.kernel.org/r/1610526716-14882-1-git-send-email-yangyicong@hisilicon.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      566c6120