- 26 Jul, 2022 7 commits
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Mario Limonciello authored
The output is currently split across two lines making it more difficult to parse unless the newlines are removed between pins or it's read in by a parser like Libreoffice Calc or Google docs. To make it easier to follow to the naked eye in a terminal window: * drop the newline in the middle of pin definitions * shorten all output using unicode characters * align all pipe delimitters * output the same phrase even for disabled functions (but with a ∅ character) Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20220722220810.28894-2-mario.limonciello@amd.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Mario Limonciello authored
Currently the debugfs output for pinctrl-amd puts the first line combined with "GPIO bank". This makes it a little harder to process as the file needs to be manually corrected for the mistake. Change this to be a new line character instead. Signed-off-by:
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Slark Xiao authored
Replace 'the the' with 'the' in the comment. Signed-off-by:
Slark Xiao <slark_xiao@163.com> Link: https://lore.kernel.org/r/20220722092419.77052-1-slark_xiao@163.comSigned-off-by:
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Rob Herring authored
The correct property name for the reset binding is 'resets', not 'reset'. Assuming actual users are correct, this error didn't show up due to missing 'additionalProperties: false'. Fix the name and add missing 'additionalProperties'. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220719214955.1875020-1-robh@kernel.orgSigned-off-by:
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Xin Gao authored
Missing a blank line after declarations. Signed-off-by:
Xin Gao <gaoxin@cdjrlc.com> Link: https://lore.kernel.org/r/20220719182647.9038-1-gaoxin@cdjrlc.comSigned-off-by:
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Konrad Dybcio authored
Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.orgSigned-off-by:
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Konrad Dybcio authored
Document the TLMM driver for SM6375. Signed-off-by:
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- 18 Jul, 2022 18 commits
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AngeloGioacchino Del Regno authored
The property mediatek,drive-strength-adv was deprecated: change the example for i2c0-pins to use drive-strength-microamp. Fixes: b6d9af2c6b69 ("dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp") Signed-off-by:AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by:
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Linus Walleij authored
This reverts commit 7542766e. It was noted during follow-up that the approach is incorrect. Signed-off-by:
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Fabio Estevam authored
Pass MODULE_DEVICE_TABLE() so that module autoloading can work. This also aligns with the other i.MX8 pinctrl drivers. Signed-off-by:
Fabio Estevam <festevam@denx.de> Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220712115154.2348971-1-festevam@denx.deSigned-off-by:
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Samuel Holland authored
This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Samuel Holland <samuel@sholland.org> Reviewed-by:
Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.orgSigned-off-by:
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Samuel Holland authored
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. In order to support multiple register layouts, some of the layout parameters need to be set based on the pinctrl variant. This requires passing the pinctrl struct pointer to the register/offset calculation functions. Reviewed-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by:
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Samuel Holland authored
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. As a first step to support this, combine the register and offset calculation functions, and refactor the math to depend on one constant for field widths instead of three. This minimizes the code size impact of making some of the factors dynamic. While rewriting these functions, move them to the implementation file, since that is the only file where they are used. And make the comment more generic, without mentioning specific offsets/sizes. The callers are updated to expect a shifted mask, and to use consistent terminology (reg/shift/mask/val). Reviewed-by:
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Samuel Holland authored
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Reviewed-by:
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Samuel Holland authored
H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383f ("pinctrl: sunxi: Support I/O bias voltage setting on H6") Reviewed-by:
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Samuel Holland authored
D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by:
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Robert Marko authored
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. Signed-off-by:
Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.comSigned-off-by:
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Robert Marko authored
Document the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12. Signed-off-by:
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Dominik Kobinski authored
Add support for pm8226 SPMI GPIOs. The PMIC features 8 GPIOs, with no holes inbetween. Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Suggested-by:
Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Signed-off-by:
Dominik Kobinski <dominikkobinski314@gmail.com> Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.comSigned-off-by:
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Andy Shevchenko authored
Instead of open coding, use device_match_of_node() helper. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Add the 'gpio-line-names' property to mt8195-pinctrl, as this will be used in devicetrees to describe pin names. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220630110453.186526-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
As was already done for MT8192 in commit b52e6953 ("dt-bindings: pinctrl: mt8192: Add drive-strength-microamp"), replace the custom mediatek,drive-strength-adv property with the standardized pinconf 'drive-strength-microamp' one. Similarly to the mt8192 counterpart, there's no user of property 'mediatek,drive-strength-adv', hence removing it is safe. Fixes: 69c3d58d ("dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property") Signed-off-by:
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AngeloGioacchino Del Regno authored
When this property was introduced, it contained underscores, but the actual code wants dashes. Change it from mediatek,rsel_resistance_in_si_unit to mediatek,rsel-resistance-in-si-unit. Fixes: 91e7edce ("dt-bindings: pinctrl: mt8195: change pull up/down description") Signed-off-by:
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Claudiu Beznea authored
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.comSigned-off-by:
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Claudiu Beznea authored
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead. Signed-off-by:
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- 11 Jul, 2022 5 commits
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Andre Przywara authored
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage for GPIO port I. Extend the range of supply port names to include vcc-pi-supply to cover that. Signed-off-by:
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Andre Przywara authored
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an interrupt (it features only two pins). However the binding requires at least naming one upstream interrupt, plus the #interrupt-cells and interrupt-controller properties. Drop the unconditional requirement for the interrupt properties, and make them dependent on being not this particular pinctrl device. Signed-off-by:
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Stephan Gerhold authored
Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.cSigned-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by:
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Stephan Gerhold authored
Document the "qcom,msm8909-tlmm" compatible for the TLMM/pin control block in the MSM8909 SoC, together with the allowed GPIOs and functions. Signed-off-by:
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Jianlong Huang authored
The pinctrl dt_node_to_map method may be called in parallel which leads us to call pinconf_generic_add_group and pinconf_generic_add_function in parallel. This is not supported though and leads to errors, so add a mutex to serialize these calls. Signed-off-by:
Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by:
Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220627085333.1774396-1-emil.renner.berthing@canonical.comSigned-off-by:
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- 09 Jul, 2022 6 commits
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.20 (take two) - Add support for the RZ/V2M and R-Car V4H SoCs, - Miscellaneous fixes and improvements.
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Basavaraj Natikar authored
Remove contact information. Signed-off-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20220613064127.220416-4-Basavaraj.Natikar@amd.comSigned-off-by:
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Basavaraj Natikar authored
Saving/restoring interrupt and wake status bits across suspend can cause the suspend to fail if an IRQ is serviced across the suspend cycle. Signed-off-by:
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Basavaraj Natikar authored
Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by:
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.20-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.20-1 * Update MAINTAINERS to set the Intel pin control status to Supported * Switch Intel pin control drivers to use struct pingroup The following is an automated git shortlog grouped by driver: baytrail: - Switch to to embedded struct pingroup cherryview: - Switch to to embedded struct pingroup intel: - Add Intel Meteor Lake pin controller support - Drop no more used members of struct intel_pingroup - Switch to to embedded struct pingroup - Embed struct pingroup into struct intel_pingroup lynxpoint: - Switch to to embedded struct pingroup MAINTAINERS: - Update Intel pin control to Supported Merge branch 'ib-v5.20-amd-pinctrl': - Merge branch 'ib-v5.20-amd-pinctrl' merrifield: - Switch to to embedded struct pingroup
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Robert Marko authored
Commit 6c846d02 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. Following this change the following warning is now observed for the SPMI PMIC pinctrl driver: gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by:
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- 05 Jul, 2022 4 commits
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Kuninori Morimoto authored
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Kuninori Morimoto authored
TSN0 needs MODSEL4 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by:
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Kuninori Morimoto authored
This patch adds missing ERROROUTC_A settings. Current existing ERROROUTC should be _B, this patch tidies it up. Signed-off-by:
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Kuninori Morimoto authored
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed. This patch adds missing PWM settings, and tidies these up. According to Document, GP3_14 Function4 is PWM2_A, but we can't select it at P1SR3[27:24]. This patch just ignore it for now. Signed-off-by:
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