- 24 Mar, 2021 40 commits
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Mark Yacoub authored
To initialize the framebuffer, call drm_gem_fb_init_with_funcs which verifies that the BO size can fit the FB size by calculating the minimum expected size of each plane. The bug was caught using igt-gpu-tools test: kms_addfb_basic.too-high and kms_addfb_basic.bo-too-small Tested on ChromeOS Zork by turning on the display and running a YT video. === Changes from v1 === 1. Added new line under declarations. 2. Use C style comment. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by:
Mark Yacoub <markyacoub@chromium.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Zhang Yunkai authored
'dce110_resource.h' included in 'dcn21_resource.c' is duplicated. 'hw_gpio.h' included in 'hw_factory_dce110.c' is duplicated. Signed-off-by:
Zhang Yunkai <zhang.yunkai@zte.com.cn> Signed-off-by:
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Zhang Yunkai authored
'drm/drm_hdcp.h' included in 'amdgpu_dm.c' is duplicated. It is also included in the 79th line. Signed-off-by:
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Jia-Ju Bai authored
When bitmap_empty() or feature->feature_num triggers an error, no error return code of smu_v11_0_set_allowed_mask() is assigned. To fix this bug, ret is assigned with -EINVAL as error return code. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reported-by:
TOTE Robot <oslab@tsinghua.edu.cn> Signed-off-by:
Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by:
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Joshua Aberback authored
[Why] The registers for the address of the cursor are aligned to 2KB, so all cursor surfaces also need to be aligned to 2KB. Currently, the provided cursor cache surface is not aligned, so we need a workaround until alignment is enforced by the surface provider. [How] - round up surface address to nearest multiple of 2048 - current policy is to provide a much bigger cache size than necessary,so this operation is safe Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Sung Lee authored
[WHY & HOW] Using values provided by DF for latency may cause hangs in multi display configurations. Revert change to previous value. Tested-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Haonan Wang <Haonan.Wang2@amd.com> Acked-by:
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Aric Cyr authored
DC version 3.2.126 brings improvements in multiple areas. In summary, we highlight: - DMUB fixes - Firmware relase 0.0.55 - Expanded dmub_cmd documentation - Enhancements in DCN30 Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Jake Wang authored
[Why] Panel control always programs instance 0. With multi eDP we need to support multiple instances. [How] Use link index to set different instances for panel control. Refactored LVTMA control to support multiple instances. Tested-by:
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Anthony Koo authored
Add comments to better describe the function of different cmds and parameters in the dmub interface Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] Driver get wrap around dmub trace data due to read pointer being increased incorrectly when there are multiple interrupt queues with very short interval [How] Check read/write pointer before copying data from ring buffer Tested-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] - Wrong scope for ifdef - Missing struct description [How] Move ifdef and add comment Tested-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] If interval of two interrupt from dmub outbox0 is too short, some event might be skipped [How] Compare read pointer and write pointer until all the event entry is processed Tested-by:
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Qingqing Zhuo authored
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests [How] Enable pflip interrupt upon pipe enablement Tested-by:
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Yongqiang Sun authored
[Why & How] Reference to read pointer which is incorrect. Change to reference to write pointer. Tested-by:
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Yongqiang Sun authored
[Why & How] Fix linux compile error Tested-by:
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Martin Leung authored
[why] In some boot configurations we need to retrieve the currently UEFI-set dppclk, but there was a typo in the calculation [how] Fix typo to make dpp_clk calculate off dpp_clk divider instead of disp_clk Tested-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Martin Leung authored
[Why] On baco-enabled systems running virtual dal, can get set power state when hw is not initialized [How] Skip DC hw part of setPowerState when hw not available Tested-by:
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Dillon Varone authored
[Why & How] Ported logic from dcn21 for reading in pipe fusing to dcn30. Supported configurations are 1 and 6 pipes. Invalid fusing will revert to 1 pipe being enabled. Tested-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
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Lijo Lazar authored
Some configurations don't have FB BAR enabled. Avoid reading ROM image from FB BAR region in such cases. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
To maintain consistency with legacy usage, remove min/max clock overload of pp_dpm_sclk node. Signed-off-by:
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Lijo Lazar authored
Use pp_od_clk_voltage node to enable performance determinism and GFX clock min/max range for aldebaran. This is to avoid overload of pp_dpm_sclk and maintain consistency in user lib interfaces. Ex: To enable perf determinism at 900MHz max gfx clock 1) echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 1 900 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Ex: To enable min 500MHz/max 900MHz gfx clocks 1) echo manual > "/sys/bus/pci/devices/.../power_dpm_force_performance_level" 2) echo s 0 500 > "/sys/bus/pci/devices/.../pp_od_clk_voltage" 3) echo s 1 900 > "/sys/bus/pci/devices/.../pp_od_clk_voltage” 4) echo c > "/sys/bus/pci/devices/.../pp_od_clk_voltage” Signed-off-by:
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Shashank Sharma authored
This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter flag, during object creation of an imported DMA buffer. In absence of this flag: 1. Function amdgpu_display_supported_domains() doesn't add AMDGPU_GEM_DOMAIN_GTT as supported domain. 2. Due to which, Function amdgpu_display_user_framebuffer_create() refuses to create framebuffer for imported DMA buffers. 3. Due to which, AddFB() IOCTL fails. 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due to which DDX driver doesn't allow flips (goes to blitting) 6. Due to which setting Freesync/VRR property fails for PRIME buffers. So, this patch finally enables Freesync with PRIME buffer offloading. v2 (chk): instead of just checking the flag we copy it over if the exporter is an amdgpu device as well. Signed-off-by:Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Shashank Sharma authored
Variable 'bp' seems to be unused residue from previous logic, and is not required anymore. Cc: Koenig Christian <christian.koenig@amd.com> Cc: Deucher Alexander <alexander.deucher@amd.com> Signed-off-by:
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Aurabindo Pillai authored
This temporarily reverts freesync video patches since it causes regression with eDP displays. This patch is a squashed revert of the following patches: 6f59f229 ("drm/amd/display: Skip modeset for front porch change") d10cd527 ("drm/amd/display: Add freesync video modes based on preferred modes") 0eb1af2e ("drm/amd/display: Add module parameter for freesync video mode") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Anson Jacob <anson.jacob@amd.com> Signed-off-by:
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Anson Jacob authored
If get_num_sdma_queues or get_num_xgmi_sdma_queues is 0, we end up doing a shift operation where the number of bits shifted equals number of bits in the operand. This behaviour is undefined. Set num_sdma_queues or num_xgmi_sdma_queues to ULLONG_MAX, if the count is >= number of bits in the operand. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1472Reported-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
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Oak Zeng authored
Aldebaran uses more than 4M runtime TMR. The current hard coded 4M TMR is not big enough for Aldebaran. Increase it to 8M. v2: Only do 8M size for ALDEBARAN (Hawking) Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Eric Huang authored
The flag is only applied on fine-grained memory. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Eric Huang authored
Page tables in vram mapping to cpu is changed from uncached to cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/ PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop page table data out of CPU cache. Signed-off-by:
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Eric Huang authored
New A+A HW supports cached vram mapped to cpu. Signed-off-by:
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Dennis Li authored
When connected to a host via xGMI, system fatal errors may trigger warm reset, driver has no change to query edc status before reset. Therefore in this case, driver should harvest previous error loging registers during boot, instead of only resetting them. v2: 1. IP's ras_manager object is created when its ras feature is enabled, so change to query edc status after amdgpu_ras_late_init called 2. change to enable watchdog timer after finishing gfx edc init Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reivewed-by:
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Felix Kuehling authored
This is needed for best machine learning performance. XNACK can still be enabled per-process if needed. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Tested-by:
Alex Sierra <alex.sierra@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reivewed-by:
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Kenneth Feng authored
Export new data in the metrics table for gfx and memory utilization counter, and each hbm temperature as well. v2: change the metrics table version to v1.1 v3: fix the coding style v4: rebase against latest kernel Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Kevin Wang authored
add PSP RAP L0 check when RAP TA is loaded. Signed-off-by:
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Kevin Wang authored
RAP TA is an optional firmware. if it doesn’t exist, the driver should bypass psp_rap_invoke() function. 1. bypass psp_rap_invoke() when RAP TA is not loaded. 2. add new parameter (status) to query RAP TA status. (the status value is different with psp_ta_invoke(), 3. fix the 'rap_status' MThread critical problem. (used without lock) Signed-off-by:
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Kevin Wang authored
add aldebaran serial number support. (serial number from metrics table) Signed-off-by:
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Felix Kuehling authored
When there is no graphics support, KFD can use more of the VMIDs. Graphics VMIDs are only used for video decoding/encoding and post processing. With two VCE engines, there is no reason to reserve more than 2 VMIDs for that. Signed-off-by:
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Dennis Li authored
SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and then trigger a system fatal error event. v2: 1. change *query_timeout_status to *query_sq_timeout_status. 2. move query_sq_timeout_status into amdgpu_ras_do_recovery. 3. add module parameters to enable/disable fatal error event and modify the watchdog timer. v3: 1. remove unused parameters of *enable_watchdog_timer Signed-off-by:
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Dennis Li authored
The bank number of both VML2 and ATCL2 are changed to 8, so refine related codes to avoid defining long name arrays. Signed-off-by:
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Dennis Li authored
add edc counter/status reset and query functions for gfx block of aldebaran. v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly. Signed-off-by:
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