- 07 Aug, 2021 23 commits
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Dmitry Baryshkov authored
Add three helper functions to be used by display drivers for setting up encoders. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210717124016.316020-3-dmitry.baryshkov@linaro.orgReviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
We are preparing to support two independent DSI hosts in the DSI/DPU code. To remove possible confusion (as both configurations can be referenced as dual DSI) let's rename old "dual DSI" (two DSI hosts driving single device, with clocks being locked) to "bonded DSI". Signed-off-by:
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Abhinav Kumar authored
During board bringups its useful to have a DSI test pattern generator to isolate a DPU vs a DSI issue and focus on the relevant hardware block. To facilitate this, add an API which triggers the DSI controller test pattern. The expected output is a rectangular checkered pattern. This has been validated on a single DSI video mode panel by calling it right after drm_panel_enable() which is also the ideal location to use this as the DSI host and the panel have been initialized by then. Further validation on dual DSI and command mode panel is pending. If there are any fix ups needed for those, it shall be applied on top of this change. Changes in v2: - generate the new dsi.xml.h and update the bitfield names Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Abhinav Kumar authored
Update the DSI controller header XML file to add registers and bitfields to support rectangular checkered pattern generator. Signed-off-by:
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Rajeev Nandan authored
Add support for v2.5.0 DSI block in the SC7280 SoC. Signed-off-by:
Rajeev Nandan <rajeevny@codeaurora.org> Reviewed-by:
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Rajeev Nandan authored
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with different enable|disable regulator loads. Signed-off-by:
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Rajeev Nandan authored
The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver. Signed-off-by:
Rob Herring <robh+dt@kernel.org> Reviewed-by:
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Dmitry Baryshkov authored
Instead of fetching shared timing through an extra function call, get them directly from msm_dsi_phy_enable. Signed-off-by:
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Dmitry Baryshkov authored
Use of_device_get_match-data() instead of of_match_node(). Signed-off-by:
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Stephen Boyd authored
Add some missing newlines to the various DRM printks in this file. Noticed while looking at logs. While we're here unbreak quoted strings so grepping them is easier. Signed-off-by:
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David Heidelberg authored
msm_atomic is doing vblank get/put's already, currently there no need to duplicate the effort in MDP4 Fix warning: ... WARNING: CPU: 3 PID: 79 at drivers/gpu/drm/drm_vblank.c:1194 drm_vblank_put+0x1cc/0x1d4 ... and multiple vblank time-outs: ... msm 5100000.mdp: vblank time out, crtc=1 ... Tested on Nexus 7 2013 (deb), LTS 5.10.50. Introduced by: 119ecb7f ("drm/msm/mdp4: request vblank during modeset") Signed-off-by:
David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20210715060925.7880-1-david@ixit.czSigned-off-by:
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David Heidelberg authored
Fixes if condition, which never worked inside mdp4_kms_init, since HW detection has been done later in mdp4_hw_init. Fixes: eb2b47bb ("drm/msm/mdp4: only use lut_clk on mdp4.2+") Signed-off-by:
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David Heidelberg authored
Inspired by MDP5 code. Also use DRM_DEV_INFO for MDP version as MDP5 does. Cosmetic change: uint32_t -> u32 - checkpatch suggestion. Signed-off-by:
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Wei Li authored
When it fail to create crtc_event kthread, it just jump to err_msm_uninit, while the 'ret' is not updated. So assign the return code before that. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Li <liwei391@huawei.com> Reviewed-by:
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Dmitry Baryshkov authored
None of supported devies uses "gdsc" regulator for DSI. GDSC support is now implemented as a power domain. Drop old code and config handling gdsc regulator requesting and enabling. Signed-off-by:
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Jonathan Marek authored
Add the required changes to support 7nm pll/phy in CPHY mode. This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable the CPHY mode. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Reviewed-by:
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Jonathan Marek authored
Document a new phy-type property which will be used to determine whether the phy should operate in D-PHY or C-PHY mode. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.caAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Jonathan Marek authored
These got lost when going from .txt to .yaml bindings, add them back. Signed-off-by:
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Baokun Li authored
Using list_move_tail() instead of list_del() + list_add_tail() in msm_gem.c. Reported-by:
Baokun Li <libaokun1@huawei.com> Link: https://lore.kernel.org/r/20210609072838.1369371-1-libaokun1@huawei.comReviewed-by:
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Douglas Anderson authored
Let's use the newly-added nvmem_cell_read_variable_le_u32() to future proof ourselves a little bit. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210521134516.v2.1.Id496c6fea0cb92ff6ea8ef1faf5d468eb09465e3@changeidReviewed-by:
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Rob Clark authored
On a5xx and a6xx devices that are using CP_WHERE_AM_I to update a ringbuffer read-ptr shadow value, periodically emit a CP_WHERE_AM_I every 32 commands, so that a later submit waiting for ringbuffer space to become available sees partial progress, rather than not seeing rptr advance at all until the GPU gets to the end of the submit that it is currently chewing on. Signed-off-by:
Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210428193654.1498482-3-robdclark@gmail.comSigned-off-by:
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Thomas Zimmermann authored
Moving the driver-specific mmap code into a GEM object function allows for using DRM helpers for various mmap callbacks. The respective msm functions are being removed. The file_operations structure fops is now being created by the helper macro DEFINE_DRM_GEM_FOPS(). v2: * rebase onto latest upstream * remove declaration of msm_gem_mmap_obj() from msm_fbdev.c Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20210706084753.8194-1-tzimmermann@suse.de [squash in missing VM_DONTEXPAND flag] Signed-off-by:
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Bjorn Andersson authored
This patch adds a Adreno 680 entry to the gpulist. Signed-off-by:
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- 31 Jul, 2021 3 commits
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Akhil P Oommen authored
This patch adds support for the gpu found in the Snapdragon 7c Gen 3 compute platform. This gpu is similar to the exisiting a660 gpu with minor delta in the programing sequence. As the Adreno GPUs are moving away from a numeric chipid based naming scheme to a string, it was decided to use 0x06030500 as the chip id of this gpu to communicate to the userspace driver. Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.3.I610377db0934b6b7deda532ec2bf786a02c38c01@changeidSigned-off-by:
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Akhil P Oommen authored
Use rev instead of revn to identify the SKU. This is in preparation to the introduction of 7c3 gpu which won't have a revn. Signed-off-by:
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Akhil P Oommen authored
Add the missing scache_cntl0 register programing which is required for a660 gpu. Signed-off-by:
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- 28 Jul, 2021 14 commits
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Rob Clark authored
Mark all the bos in the submit as active, before pinning, to prevent evicting a buffer in the same submit to make room for a buffer earlier in the table. Signed-off-by:
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Rob Clark authored
The drm/scheduler provides additional prioritization on top of that provided by however many number of ringbuffers (each with their own priority level) is supported on a given generation. Expose the additional levels of priority to userspace and map the userspace priority back to ring (first level of priority) and schedular priority (additional priority levels within the ring). Signed-off-by:
Christian König <christian.koenig@amd.com> Link: https://lore.kernel.org/r/20210728010632.2633470-13-robdclark@gmail.comSigned-off-by:
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Rob Clark authored
It is sufficient to serialize on the submit queue now. Signed-off-by:
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Rob Clark authored
This was only used to detect userspace including the same bo multiple times in a submit. But ww_mutex can already tell us this. When we drop struct_mutex around the submit ioctl, we'd otherwise need to lock the bo before adding it to the bo_list. But since ww_mutex can already tell us this, it is simpler just to remove the bo_list. Signed-off-by:
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Rob Clark authored
For existing adrenos, there is one or more ringbuffer, depending on whether preemption is supported. When preemption is supported, each ringbuffer has it's own priority. A submitqueue (which maps to a gl context or vk queue in userspace) is mapped to a specific ring- buffer at creation time, based on the submitqueue's priority. Each ringbuffer has it's own drm_gpu_scheduler. Each submitqueue maps to a drm_sched_entity. And each submit maps to a drm_sched_job. Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/4Signed-off-by:
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Rob Clark authored
In the next patch, we start having more than a single potential failure reason. Signed-off-by:
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Rob Clark authored
Previously the (non-fd) fence returned from submit ioctl was a raw seqno, which is scoped to the ring. But from UABI standpoint, the ioctls related to seqno fences all specify a submitqueue. We can take advantage of that to replace the seqno fences with a cyclic idr handle. This is in preperation for moving to drm scheduler, at which point the submit ioctl will return after queuing the submit job to the scheduler, but before the submit is written into the ring (and therefore before a ring seqno has been assigned). Which means we need to replace the dma_fence that userspace may need to wait on with a scheduler fence. Signed-off-by:
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Rob Clark authored
Move all the locked/active/pinned state handling to msm_gem_submit.c. In particular, for drm/scheduler, we'll need to do all this before pushing the submit job to the scheduler. But while we're at it we can get rid of the dupicate pin and refcnt. Signed-off-by:
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Rob Clark authored
No need for this to be split in two parts. Signed-off-by:
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Rob Clark authored
Now that no one is using it, remove it. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://lore.kernel.org/r/20210728010632.2633470-5-robdclark@gmail.comSigned-off-by:
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Rob Clark authored
No idea why we were still using this. It certainly hasn't been needed for some time. So drop the pointless twin codepaths. Signed-off-by:
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Rob Clark authored
If we don't have a gpu, there is no need to create a submitqueue, which lets us simplify the error handling and submitqueue creation. Signed-off-by:
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Rob Clark authored
Fix a couple incorrect or misspelt comments, and add submitqueue doc comment. Signed-off-by:
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Rob Clark authored
This adds a few things to try and make frequency scaling better match the workload: 1) Longer polling interval to avoid whip-lashing between too-high and too-low frequencies in certain workloads, like mobile games which throttle themselves to 30fps. Previously our polling interval was short enough to let things ramp down to minimum freq in the "off" frame, but long enough to not react quickly enough when rendering started on the next frame, leading to uneven frame times. (Ie. rather than a consistent 33ms it would alternate between 16/33/48ms.) 2) Awareness of when the GPU is active vs idle. Since we know when the GPU is active vs idle, we can clamp the frequency down to the minimum while it is idle. (If it is idle for long enough, then the autosuspend delay will eventually kick in and power down the GPU.) Since devfreq has no knowledge of powered-but-idle, this takes a small bit of trickery to maintain a "fake" frequency while idle. This, combined with the longer polling period allows devfreq to arrive at a reasonable "active" frequency, while still clamping to minimum freq when idle to reduce power draw. 3) Boost. Because simple_ondemand needs to see a certain threshold of busyness to ramp up, we could end up needing multiple polling cycles before it reacts appropriately on interactive workloads (ex. scrolling a web page after reading for some time), on top of the already lengthened polling interval, when we see a idle to active transition after a period of idle time we boost the frequency that we return to. Signed-off-by:
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