- 24 May, 2019 40 commits
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Evan Quan authored
Update Vega10 top performance level power state accordingly on OD. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
No need to enable or disable AVFS if it's already in wanted state. Signed-off-by:
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Evan Quan authored
With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS will be disabled. However, the buggy code makes this actually not working as expected. - V2: clear all OD flags excpet DPMTABLE_OD_UPDATE_VDDC Signed-off-by:
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Evan Quan authored
This may affects the Vega10 MCLK OD functionality. Signed-off-by:
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Leo Liu authored
To replace checking ring type and make them generic Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Leo Liu authored
There is no user fence support for VCN Signed-off-by:
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Leo Liu authored
There is no user fence support for VCE Signed-off-by:
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Leo Liu authored
There is no user fence support for UVD Signed-off-by:
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Leo Liu authored
So we can generalize the no user fence supported engine Signed-off-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Tested-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
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xinhui pan authored
suspend/resume will change ras state behind us. Let driver get notified. Signed-off-by:
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xinhui pan authored
add ras suspend function. rename ras_post_init to amdgpu_ras_resume. Signed-off-by:
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xinhui pan authored
add badpages node. it will output badpages list in format gpu pfn : gpu page size : flags example 0x00000000 : 0x00001000 : R 0x00000001 : 0x00001000 : R 0x00000002 : 0x00001000 : R 0x00000003 : 0x00001000 : R 0x00000004 : 0x00001000 : R 0x00000005 : 0x00001000 : R 0x00000006 : 0x00001000 : R 0x00000007 : 0x00001000 : P 0x00000008 : 0x00001000 : P 0x00000009 : 0x00001000 : P flags can be one of below characters R: reserved. P: pending for reserve. F: failed to reserve for some reasons. Signed-off-by:
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James Zhu authored
During S3 test, when system wake up and resume, ras interface is already allocated. Move workaround before ras jumps to resume step in gfx_v9_0_ecc_late_init, and make sure workaround applied during resume. Also remove unused mmGB_EDC_MODE clearing. Signed-off-by:
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Wang Hai authored
Fix the following sparse warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:483:21: warning: symbol 'dce120_clock_source_create' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:506:6: warning: symbol 'dce120_clock_source_destroy' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:513:6: warning: symbol 'dce120_hw_sequencer_create' was not declared. Should it be static? Fixes: b8fdfcc6 ("drm/amd/display: Add DCE12 core support") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wang Hai <wanghai26@huawei.com> Signed-off-by:
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Trigger Huang authored
Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC to program some registers if supported Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Reviewed-by:
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Trigger Huang authored
New feature for RLC, some registers can be programmed by RLC interface under SR-IOV VF: WREG32_SOC15_RLC_SHADOW: 1, for GRBM_GFX_CNTL, firstly the new register value should be be programmed to SCRATCH_REG2 1, for GRBM_GFX_INDEX, firstly the new register value should be be programmed to SCRATCH_REG3 WREG32_RLC: for registers supported to be programmed by RLC interface, the following sequence should be used: 1, write the value to SCRATCH_REG0 2, write reg | 0x80000000 to SCRATCH_REG1 3, write 0x1 to RLC_SPARE_INT to notify RLC 4, polling SCRATCH_REG1 to check if finished Signed-off-by:
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Trigger Huang authored
For Vega10 SR-IOV VF, skip setting some regs due to: 1, host will program them 2, avoid VF register programming violations Signed-off-by:
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Trigger Huang authored
Add VMR ring support for Vega10 SR-IOV VF if PSP supported Signed-off-by:
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Trigger Huang authored
call psp to program ih cntl in SR-IOV if supported Signed-off-by:
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Trigger Huang authored
Add implementation to program regs by PSP, currently the following IH registers are supported: IH_RB_CNTL IH_RB_CNTL_RING1 IH_RB_CNTL_RING2 Signed-off-by:
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Trigger Huang authored
Add new PSP command GFX_CMD_ID_PROG_REG definition Signed-off-by:
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Trigger Huang authored
In order to support new PSP feature that PSP may provide interface to program IH CNTL register, initialize PSP before IH under Vega10 SR-IOV VF Signed-off-by:
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Trigger Huang authored
Set different register access mode according to the features provided by firmware Signed-off-by:
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xinhui pan authored
ras need initialize proper state after late init Signed-off-by:
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xinhui pan authored
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by:
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xinhui pan authored
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by:
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xinhui pan authored
request a gpu reset if ras return EAGAIN. we will run late init again so it is ok to do nothing this time. Signed-off-by:
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xinhui pan authored
add another flag to allow IP do a gpu reset after device init. Signed-off-by:
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xinhui pan authored
Check ras TA error code and return EAGAIN. Issue ras enable/disable cmd without checking currect state. Looks like ras TA will handle current state == target state case. Now driver might need do a reset to satisfy ras TA. Signed-off-by:
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xinhui pan authored
Enable this now to reset the GPU on RAS errors. This reverts commit 138352e5. Signed-off-by:
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xinhui pan authored
ras need late init to initialize proper state. Signed-off-by:
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Jonathan Kim authored
v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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James Zhu authored
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by:
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James Zhu authored
Add EDC counter register to support gfx9 gpr EDC workaround to clear all EDC counters. Signed-off-by:
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Felix Kuehling authored
Need to reserve space for the shared eviction fence when initializing a KFD VM. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why] To send sdp message immediately from a single slot. [How] Modify the generic SDP message interface, and use GSP4 to send immediate sdp message. Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Roman Li authored
[Why] In fill_plane_buffer_attributes() we calculate chroma/luma assuming that the surface_pixel_format is always valid. If it's not the case, there's a risk of divide by zero error. [How] Check if format valid before calculating pixel format attributes Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
David Francis <David.Francis@amd.com> Acked-by:
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