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Commit 59fb659b authored by Paul Walmsley's avatar Paul Walmsley
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OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific files 

In preparation for adding OMAP4-specific PRCM accessor/mutator
functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific
files.  Most of what was in mach-omap2/{cm,prm}.{c,h} has now been
moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was
OMAP2xxx/3xxx-specific.

This process also requires the #includes in each of these files to be
changed to reference the new file name.  As part of doing so, add some
comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use
"sideways includes", to indicate that these users of the PRM/CM includes
should not be doing so.

Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this
patch.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Acked-by: default avatarOmar Ramirez Luna <omar.ramirez@ti.com>
Cc: Felipe Contreras <felipe.contreras@gmail.com>
Acked-by: default avatarFelipe Contreras <felipe.contreras@gmail.com>
Cc: Greg Kroah-Hartman <greg@kroah.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Reviewed-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Tested-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent cdb54c44
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Showing with 699 additions and 650 deletions
arch/arm/mach-omap2/Makefile
View file @ 59fb659b
......@@ -6,7 +6,7 @@
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
common.o gpio.o dma.o wd_timer.o
omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
omap-2-3-common = irq.o sdrc.o
hwmod-common = omap_hwmod.o \
omap_hwmod_common_data.o
clock-common = clock.o clock_common_data.o \
......@@ -72,9 +72,12 @@ endif
endif
# PRCM
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm.o
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm4xxx.o
obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
# will be removed once the OMAP4 part of the codebase is converted to
# use OMAP4-specific PRCM functions.
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cm4xxx.o
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
......
arch/arm/mach-omap2/clkt2xxx_apll.c
View file @ 59fb659b
......@@ -26,7 +26,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
......
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View file @ 59fb659b
......@@ -32,7 +32,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
......
arch/arm/mach-omap2/clkt2xxx_osc.c
View file @ 59fb659b
......@@ -27,7 +27,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
static int omap2_enable_osc_ck(struct clk *clk)
......
arch/arm/mach-omap2/clkt2xxx_sys.c
View file @ 59fb659b
......@@ -26,7 +26,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
void __iomem *prcm_clksrc_ctrl;
......
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View file @ 59fb659b
......@@ -40,7 +40,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
const struct prcm_config *curr_prcm_set;
......
arch/arm/mach-omap2/clkt_dpll.c
View file @ 59fb659b
......@@ -24,7 +24,6 @@
#include <plat/clock.h>
#include "clock.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
......
arch/arm/mach-omap2/clock.c
View file @ 59fb659b
......@@ -29,9 +29,7 @@
#include <plat/prcm.h>
#include "clock.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
......
arch/arm/mach-omap2/clock2420_data.c
View file @ 59fb659b
......@@ -22,8 +22,8 @@
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "prm.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
......
arch/arm/mach-omap2/clock2430.c
View file @ 59fb659b
......@@ -25,7 +25,7 @@
#include "clock.h"
#include "clock2xxx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
/**
......
arch/arm/mach-omap2/clock2430_data.c
View file @ 59fb659b
......@@ -22,8 +22,8 @@
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "prm.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
......
arch/arm/mach-omap2/clock34xx.c
View file @ 59fb659b
......@@ -25,7 +25,7 @@
#include "clock.h"
#include "clock34xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/**
......
arch/arm/mach-omap2/clock3517.c
View file @ 59fb659b
......@@ -25,7 +25,7 @@
#include "clock.h"
#include "clock3517.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/*
......
arch/arm/mach-omap2/clock3xxx.c
View file @ 59fb659b
......@@ -25,9 +25,9 @@
#include "clock.h"
#include "clock3xxx.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/*
......
arch/arm/mach-omap2/clock3xxx_data.c
View file @ 59fb659b
......@@ -28,9 +28,9 @@
#include "clock36xx.h"
#include "clock3517.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
......
arch/arm/mach-omap2/clock44xx_data.c
View file @ 59fb659b
......@@ -33,11 +33,15 @@
#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "cm-regbits-44xx.h"
#include "prm.h"
#include "prm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
#include "control.h"
/* OMAP4 modulemode control */
#define OMAP4430_MODULEMODE_HWCTRL 0
#define OMAP4430_MODULEMODE_SWCTRL 1
/* Root clocks */
static struct clk extalt_clkin_ck = {
......
arch/arm/mach-omap2/clockdomain.c
View file @ 59fb659b
......@@ -27,9 +27,10 @@
#include <linux/bitops.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include <plat/clock.h>
#include <plat/powerdomain.h>
......
arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
View file @ 59fb659b
......@@ -36,8 +36,8 @@
#include <linux/io.h>
#include <plat/clockdomain.h>
#include "cm.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
......
arch/arm/mach-omap2/clockdomains44xx_data.c
View file @ 59fb659b
......@@ -27,6 +27,8 @@
#include <linux/io.h>
#include <plat/clockdomain.h>
#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"
......
arch/arm/mach-omap2/cm-regbits-24xx.h
View file @ 59fb659b
......@@ -14,8 +14,6 @@
* published by the Free Software Foundation.
*/
#include "cm.h"
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
......
arch/arm/mach-omap2/cm-regbits-34xx.h
View file @ 59fb659b
......@@ -14,8 +14,6 @@
* published by the Free Software Foundation.
*/
#include "cm.h"
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
......
arch/arm/mach-omap2/cm-regbits-44xx.h
View file @ 59fb659b
......@@ -22,9 +22,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#include "cm.h"
/*
* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
* CM_TESLA_DYNAMICDEP
......
arch/arm/mach-omap2/cm.h
View file @ 59fb659b
#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
#define __ARCH_ASM_MACH_OMAP2_CM_H
/*
* OMAP2/3 Clock Management (CM) register definitions
* OMAP2+ Clock Management prototypes
*
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2009 Nokia Corporation
......@@ -13,133 +10,8 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "prcm-common.h"
#define OMAP2420_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
#include "cm44xx.h"
/*
* Architecture-specific global CM registers
* Use cm_{read,write}_reg() with these registers.
* These registers appear once per CM module.
*/
#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
/*
* Module specific CM registers from CM_BASE + domain offset
* Use cm_{read,write}_mod_reg() with these registers.
* These register offsets generally appear in more than one PRCM submodule.
*/
/* Common between 24xx and 34xx */
#define CM_FCLKEN 0x0000
#define CM_FCLKEN1 CM_FCLKEN
#define CM_CLKEN CM_FCLKEN
#define CM_ICLKEN 0x0010
#define CM_ICLKEN1 CM_ICLKEN
#define CM_ICLKEN2 0x0014
#define CM_ICLKEN3 0x0018
#define CM_IDLEST 0x0020
#define CM_IDLEST1 CM_IDLEST
#define CM_IDLEST2 0x0024
#define CM_AUTOIDLE 0x0030
#define CM_AUTOIDLE1 CM_AUTOIDLE
#define CM_AUTOIDLE2 0x0034
#define CM_AUTOIDLE3 0x0038
#define CM_CLKSEL 0x0040
#define CM_CLKSEL1 CM_CLKSEL
#define CM_CLKSEL2 0x0044
#define OMAP2_CM_CLKSTCTRL 0x0048
#define OMAP4_CM_CLKSTCTRL 0x0000
/* Architecture-specific registers */
#define OMAP24XX_CM_FCLKEN2 0x0004
#define OMAP24XX_CM_ICLKEN4 0x001c
#define OMAP24XX_CM_AUTOIDLE4 0x003c
#define OMAP2430_CM_IDLEST3 0x0028
#define OMAP3430_CM_CLKEN_PLL 0x0004
#define OMAP3430ES2_CM_CLKEN2 0x0004
#define OMAP3430ES2_CM_FCLKEN3 0x0008
#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
#define OMAP3430_CM_CLKSTST 0x004c
#define OMAP3430ES2_CM_CLKSEL4 0x004c
#define OMAP3430ES2_CM_CLKSEL5 0x0050
#define OMAP3430_CM_CLKSEL2_EMU 0x0050
#define OMAP3430_CM_CLKSEL3_EMU 0x0054
/* CM2.CEFUSE_CM2 register offsets */
/* OMAP4 modulemode control */
#define OMAP4430_MODULEMODE_HWCTRL 0
#define OMAP4430_MODULEMODE_SWCTRL 1
/* Clock management domain register get/set */
#ifndef __ASSEMBLER__
extern u32 cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
u8 idlest_shift);
extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return cm_rmw_mod_reg_bits(bits, bits, module, idx);
}
static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
#endif
/* CM register bits shared between 24XX and 3430 */
/* CM_CLKSEL_GFX */
#define OMAP_CLKSEL_GFX_SHIFT 0
#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
/* CM_ICLKEN_GFX */
#define OMAP_EN_GFX_SHIFT 0
#define OMAP_EN_GFX_MASK (1 << 0)
/* CM_IDLEST_GFX */
#define OMAP_ST_GFX_MASK (1 << 0)
/* CM_IDLEST indicator */
#define OMAP24XX_CM_IDLEST_VAL 0
#define OMAP34XX_CM_IDLEST_VAL 1
#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
#define __ARCH_ASM_MACH_OMAP2_CM_H
/*
* MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
......
arch/arm/mach-omap2/cm.c → arch/arm/mach-omap2/cm2xxx_3xxx.c
View file @ 59fb659b
......@@ -10,7 +10,6 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
......@@ -19,11 +18,10 @@
#include <linux/err.h>
#include <linux/io.h>
#include <asm/atomic.h>
#include <plat/common.h>
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
......@@ -31,6 +29,40 @@ static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};
u32 cm_read_mod_reg(s16 module, u16 idx)
{
return __raw_readl(cm_base + module + idx);
}
void cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__raw_writel(val, cm_base + module + idx);
}
/* Read-modify-write a register in a CM module. Caller must lock */
u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
u32 v;
v = cm_read_mod_reg(module, idx);
v &= ~mask;
v |= bits;
cm_write_mod_reg(v, module, idx);
return v;
}
u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return cm_rmw_mod_reg_bits(bits, bits, module, idx);
}
u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
/**
* omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
* @prcm_mod: PRCM module offset
......@@ -59,7 +91,6 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
else
BUG();
/* XXX should be OMAP2 CM */
omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
MAX_MODULE_READY_TIME, i);
......
arch/arm/mach-omap2/cm2xxx_3xxx.h 0 → 100644
View file @ 59fb659b
/*
* OMAP2/3 Clock Management (CM) register definitions
*
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* The CM hardware modules on the OMAP2/3 are quite similar to each
* other. The CM modules/instances on OMAP4 are quite different, so
* they are handled in a separate file.
*/
#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
#include "prcm-common.h"
#define OMAP2420_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
/*
* OMAP3-specific global CM registers
* Use cm_{read,write}_reg() with these registers.
* These registers appear once per CM module.
*/
#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
/*
* Module specific CM register offsets from CM_BASE + domain offset
* Use cm_{read,write}_mod_reg() with these registers.
* These register offsets generally appear in more than one PRCM submodule.
*/
/* Common between OMAP2 and OMAP3 */
#define CM_FCLKEN 0x0000
#define CM_FCLKEN1 CM_FCLKEN
#define CM_CLKEN CM_FCLKEN
#define CM_ICLKEN 0x0010
#define CM_ICLKEN1 CM_ICLKEN
#define CM_ICLKEN2 0x0014
#define CM_ICLKEN3 0x0018
#define CM_IDLEST 0x0020
#define CM_IDLEST1 CM_IDLEST
#define CM_IDLEST2 0x0024
#define CM_AUTOIDLE 0x0030
#define CM_AUTOIDLE1 CM_AUTOIDLE
#define CM_AUTOIDLE2 0x0034
#define CM_AUTOIDLE3 0x0038
#define CM_CLKSEL 0x0040
#define CM_CLKSEL1 CM_CLKSEL
#define CM_CLKSEL2 0x0044
#define OMAP2_CM_CLKSTCTRL 0x0048
/* OMAP2-specific register offsets */
#define OMAP24XX_CM_FCLKEN2 0x0004
#define OMAP24XX_CM_ICLKEN4 0x001c
#define OMAP24XX_CM_AUTOIDLE4 0x003c
#define OMAP2430_CM_IDLEST3 0x0028
/* OMAP3-specific register offsets */
#define OMAP3430_CM_CLKEN_PLL 0x0004
#define OMAP3430ES2_CM_CLKEN2 0x0004
#define OMAP3430ES2_CM_FCLKEN3 0x0008
#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
#define OMAP3430_CM_CLKSTST 0x004c
#define OMAP3430ES2_CM_CLKSEL4 0x004c
#define OMAP3430ES2_CM_CLKSEL5 0x0050
#define OMAP3430_CM_CLKSEL2_EMU 0x0050
#define OMAP3430_CM_CLKSEL3_EMU 0x0054
/* CM_IDLEST bit field values to indicate deasserted IdleReq */
#define OMAP24XX_CM_IDLEST_VAL 0
#define OMAP34XX_CM_IDLEST_VAL 1
/* Clock management domain register get/set */
#ifndef __ASSEMBLER__
extern u32 cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
u8 idlest_shift);
extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
#endif
/* CM register bits shared between 24XX and 3430 */
/* CM_CLKSEL_GFX */
#define OMAP_CLKSEL_GFX_SHIFT 0
#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
/* CM_ICLKEN_GFX */
#define OMAP_EN_GFX_SHIFT 0
#define OMAP_EN_GFX_MASK (1 << 0)
/* CM_IDLEST_GFX */
#define OMAP_ST_GFX_MASK (1 << 0)
#endif
arch/arm/mach-omap2/cm44xx.h
View file @ 59fb659b
......@@ -18,6 +18,7 @@
#include "prcm-common.h"
#include "cm.h"
#define OMAP4_CM_CLKSTCTRL 0x0000
......
arch/arm/mach-omap2/cm4xxx.c
View file @ 59fb659b
......@@ -23,7 +23,7 @@
#include <plat/common.h>
#include "cm.h"
#include "cm44xx.h"
#include "cm-regbits-44xx.h"
/**
......
arch/arm/mach-omap2/control.c
View file @ 59fb659b
......@@ -20,8 +20,8 @@
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"
......
arch/arm/mach-omap2/dpll3xxx.c
View file @ 59fb659b
......@@ -32,9 +32,7 @@
#include <asm/clkdev.h>
#include "clock.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
......
arch/arm/mach-omap2/dsp.c
View file @ 59fb659b
......@@ -11,9 +11,16 @@
* published by the Free Software Foundation.
*/
/*
* XXX The function pointers to the PRM/CM functions are incorrect and
* should be removed. No device driver should be changing PRM/CM bits
* directly; that's a layering violation -- those bits are the responsibility
* of the OMAP PM core code.
*/
#include <linux/platform_device.h>
#include "prm.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#ifdef CONFIG_BRIDGE_DVFS
#include <plat/omap-pm.h>
#endif
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ 59fb659b
......@@ -145,8 +145,9 @@
#include <plat/omap_hwmod.h>
#include <plat/prcm.h>
#include "cm.h"
#include "prm.h"
#include "cm2xxx_3xxx.h"
#include "cm44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
/* Maximum microseconds to wait for OMAP module to softreset */
......
arch/arm/mach-omap2/pm-debug.c
View file @ 59fb659b
......@@ -33,8 +33,8 @@
#include <plat/clockdomain.h>
#include <plat/dmtimer.h>
#include "prm.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#include "pm.h"
int omap2_pm_debug;
......
arch/arm/mach-omap2/pm24xx.c
View file @ 59fb659b
......@@ -42,9 +42,9 @@
#include <plat/dma.h>
#include <plat/board.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
......
arch/arm/mach-omap2/pm34xx.c
View file @ 59fb659b
......@@ -41,11 +41,11 @@
#include <asm/tlbflush.h>
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "sdrc.h"
#include "control.h"
......
arch/arm/mach-omap2/powerdomain.c
View file @ 59fb659b
......@@ -19,6 +19,9 @@
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/string.h>
#include "cm2xxx_3xxx.h"
#include "cm44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
#include <plat/cpu.h>
......
arch/arm/mach-omap2/powerdomain44xx.c
View file @ 59fb659b
......@@ -18,6 +18,7 @@
#include <plat/powerdomain.h>
#include <plat/prcm.h>
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
#include "powerdomains.h"
......
arch/arm/mach-omap2/powerdomains2xxx_data.c
View file @ 59fb659b
......@@ -19,10 +19,8 @@
#include "powerdomains.h"
#include "prcm-common.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
/* 24XX powerdomains and dependencies */
......
arch/arm/mach-omap2/powerdomains3xxx_data.c
View file @ 59fb659b
......@@ -19,9 +19,9 @@
#include "powerdomains.h"
#include "prcm-common.h"
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/*
......
arch/arm/mach-omap2/powerdomains44xx_data.c
View file @ 59fb659b
......@@ -26,7 +26,6 @@
#include "powerdomains.h"
#include "prcm-common.h"
#include "prm.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
......
arch/arm/mach-omap2/prcm-common.h
View file @ 59fb659b
......@@ -396,5 +396,11 @@
*/
#define MAX_MODULE_HARDRESET_WAIT 10000
# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void __iomem *cm_base;
extern void __iomem *cm2_base;
# endif
#endif
arch/arm/mach-omap2/prcm.c
View file @ 59fb659b
......@@ -29,16 +29,17 @@
#include "clock.h"
#include "clock2xxx.h"
#include "cm.h"
#include "prm.h"
#include "cm2xxx_3xxx.h"
#include "cm44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-44xx.h"
#include "control.h"
static void __iomem *prm_base;
static void __iomem *cm_base;
static void __iomem *cm2_base;
void __iomem *prm_base;
void __iomem *cm_base;
void __iomem *cm2_base;
#define MAX_MODULE_ENABLE_WAIT 100000
......@@ -158,56 +159,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
prcm_offs, OMAP4_RM_RSTCTRL);
}
static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
{
BUG_ON(!base);
return __raw_readl(base + module + reg);
}
static inline void __omap_prcm_write(u32 value, void __iomem *base,
s16 module, u16 reg)
{
BUG_ON(!base);
__raw_writel(value, base + module + reg);
}
/* Read a register in a PRM module */
u32 prm_read_mod_reg(s16 module, u16 idx)
{
return __omap_prcm_read(prm_base, module, idx);
}
/* Write into a register in a PRM module */
void prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__omap_prcm_write(val, prm_base, module, idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
u32 v;
v = prm_read_mod_reg(module, idx);
v &= ~mask;
v |= bits;
prm_write_mod_reg(v, module, idx);
return v;
}
/* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
u32 v;
v = prm_read_mod_reg(domain, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
/* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
{
......@@ -232,30 +183,6 @@ u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
return v;
}
/* Read a register in a CM module */
u32 cm_read_mod_reg(s16 module, u16 idx)
{
return __omap_prcm_read(cm_base, module, idx);
}
/* Write into a register in a CM module */
void cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__omap_prcm_write(val, cm_base, module, idx);
}
/* Read-modify-write a register in a CM module. Caller must lock */
u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
u32 v;
v = cm_read_mod_reg(module, idx);
v &= ~mask;
v |= bits;
cm_write_mod_reg(v, module, idx);
return v;
}
/**
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
......@@ -266,6 +193,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
*
* Returns 1 if the module indicated readiness in time, or 0 if it
* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
*
* XXX This function is deprecated. It should be removed once the
* hwmod conversion is complete.
*/
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
const char *name)
......
arch/arm/mach-omap2/prm-regbits-24xx.h
View file @ 59fb659b
......@@ -14,7 +14,7 @@
* published by the Free Software Foundation.
*/
#include "prm.h"
#include "prm2xxx_3xxx.h"
/* Bits shared between registers */
......
arch/arm/mach-omap2/prm-regbits-34xx.h
View file @ 59fb659b
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
/*
* OMAP3430 Power/Reset Management register bits
*
......@@ -13,8 +10,11 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
#include "prm.h"
#include "prm2xxx_3xxx.h"
/* Shared register bits */
......
arch/arm/mach-omap2/prm-regbits-44xx.h
View file @ 59fb659b
......@@ -22,8 +22,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
#include "prm.h"
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
......
arch/arm/mach-omap2/prm.h
View file @ 59fb659b
This diff is collapsed.
arch/arm/mach-omap2/prm2xxx_3xxx.c
View file @ 59fb659b
......@@ -12,18 +12,65 @@
*/
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <plat/common.h>
#include <plat/cpu.h>
#include <plat/prcm.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
u32 prm_read_mod_reg(s16 module, u16 idx)
{
return __raw_readl(prm_base + module + idx);
}
void prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
__raw_writel(val, prm_base + module + idx);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
u32 v;
v = prm_read_mod_reg(module, idx);
v &= ~mask;
v |= bits;
prm_write_mod_reg(v, module, idx);
return v;
}
/* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
u32 v;
v = prm_read_mod_reg(domain, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return prm_rmw_mod_reg_bits(bits, bits, module, idx);
}
u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
/**
* omap2_prm_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module
......
arch/arm/mach-omap2/prm2xxx_3xxx.h 0 → 100644
View file @ 59fb659b
This diff is collapsed.
arch/arm/mach-omap2/prm44xx.h
View file @ 59fb659b
......@@ -26,6 +26,7 @@
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#include "prcm-common.h"
#include "prm.h"
#define OMAP4430_PRM_BASE 0x4a306000
......
arch/arm/mach-omap2/sdrc.c
View file @ 59fb659b
......@@ -27,8 +27,6 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include "prm.h"
#include <plat/sdrc.h>
#include "sdrc.h"
......
arch/arm/mach-omap2/sdrc2xxx.c
View file @ 59fb659b
......@@ -28,7 +28,7 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "clock.h"
#include <plat/sdrc.h>
#include "sdrc.h"
......
arch/arm/mach-omap2/serial.c
View file @ 59fb659b
......@@ -40,9 +40,9 @@
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include "prm.h"
#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
......
arch/arm/mach-omap2/sleep34xx.S
View file @ 59fb659b
......@@ -27,8 +27,8 @@
#include <plat/sram.h>
#include <mach/io.h>
#include "cm.h"
#include "prm.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#include "sdrc.h"
#include "control.h"
......
arch/arm/mach-omap2/sram242x.S
View file @ 59fb659b
......@@ -27,8 +27,8 @@
#include <mach/io.h>
#include <mach/hardware.h>
#include "prm.h"
#include "cm.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "sdrc.h"
.text
......
arch/arm/mach-omap2/sram243x.S
View file @ 59fb659b
......@@ -27,8 +27,8 @@
#include <mach/io.h>
#include <mach/hardware.h>
#include "prm.h"
#include "cm.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "sdrc.h"
.text
......
arch/arm/mach-omap2/sram34xx.S
View file @ 59fb659b
......@@ -32,7 +32,7 @@
#include <mach/io.h>
#include "sdrc.h"
#include "cm.h"
#include "cm2xxx_3xxx.h"
.text
......
arch/arm/plat-omap/include/plat/common.h
View file @ 59fb659b
......@@ -27,6 +27,8 @@
#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
#define __ARCH_ARM_MACH_OMAP_COMMON_H
#include <linux/delay.h>
#include <plat/i2c.h>
struct sys_timer;
......
arch/arm/plat-omap/include/plat/prcm.h
View file @ 59fb659b
......@@ -34,15 +34,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
void omap3_prcm_save_context(void);
void omap3_prcm_restore_context(void);
u32 prm_read_mod_reg(s16 module, u16 idx);
void prm_write_mod_reg(u32 val, s16 module, u16 idx);
u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
u32 cm_read_mod_reg(s16 module, u16 idx);
void cm_write_mod_reg(u32 val, s16 module, u16 idx);
u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
#endif
......
arch/arm/plat-omap/mcbsp.c
View file @ 59fb659b
......@@ -28,6 +28,8 @@
#include <plat/dma.h>
#include <plat/mcbsp.h>
/* XXX These "sideways" includes are a sign that something is wrong */
#include "../mach-omap2/cm2xxx_3xxx.h"
#include "../mach-omap2/cm-regbits-34xx.h"
struct omap_mcbsp **mcbsp_ptr;
......
arch/arm/plat-omap/sram.c
View file @ 59fb659b
......@@ -33,9 +33,10 @@
#include "sram.h"
#include "fb.h"
/* XXX These "sideways" includes are a sign that something is wrong */
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
# include "../mach-omap2/prm.h"
# include "../mach-omap2/cm.h"
# include "../mach-omap2/prm2xxx_3xxx.h"
# include "../mach-omap2/sdrc.h"
#endif
......
drivers/staging/tidspbridge/core/_tiomap.h
View file @ 59fb659b
......@@ -21,6 +21,12 @@
#include <plat/powerdomain.h>
#include <plat/clockdomain.h>
/*
* XXX These mach-omap2/ includes are wrong and should be removed. No
* driver should read or write to PRM/CM registers directly; they
* should rely on OMAP core code to do this.
*/
#include <mach-omap2/cm2xxx_3xxx.h>
#include <mach-omap2/prm-regbits-34xx.h>
#include <mach-omap2/cm-regbits-34xx.h>
#include <dspbridge/devdefs.h>
......
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