1. 28 Nov, 2019 4 commits
  2. 27 Nov, 2019 1 commit
    • Charles Keepax's avatar
      spi: cadence: Correct handling of native chipselect · 61acd19f
      Charles Keepax authored
      To fix a regression on the Cadence SPI driver, this patch reverts
      commit 6046f540 ("spi: cadence: Fix default polarity of native
      chipselect").
      
      This patch was not the correct fix for the issue. The SPI framework
      calls the set_cs line with the logic level it desires on the chip select
      line, as such the old is_high handling was correct. However, this was
      broken by the fact that before commit 3e5ec1db ("spi: Fix SPI_CS_HIGH
      setting when using native and GPIO CS") all controllers that offered
      the use of a GPIO chip select had SPI_CS_HIGH applied, even for hardware
      chip selects. This caused the value passed into the driver to be inverted.
      Which unfortunately makes it look like a logical enable the chip select
      value.
      
      Since the core was corrected to not unconditionally apply SPI_CS_HIGH,
      the Cadence driver, whilst using the hardware chip select, will deselect
      the chip select every time we attempt to communicate with the device,
      which results in failed communications.
      
      Fixes: 3e5ec1db ("spi: Fix SPI_CS_HIGH setting when using native and GPIO CS")
      Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Link: https://lore.kernel.org/r/20191126164140.6240-1-ckeepax@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      61acd19f
  3. 25 Nov, 2019 1 commit
  4. 22 Nov, 2019 2 commits
  5. 20 Nov, 2019 1 commit
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  7. 15 Nov, 2019 10 commits
  8. 12 Nov, 2019 1 commit
  9. 11 Nov, 2019 3 commits
  10. 08 Nov, 2019 7 commits
  11. 07 Nov, 2019 2 commits
  12. 06 Nov, 2019 1 commit
  13. 31 Oct, 2019 1 commit
  14. 30 Oct, 2019 4 commits