- 10 Apr, 2017 33 commits
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Greg Kroah-Hartman authored
Merge tag 'phy-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.12 *) Add new PHY driver for Qualcomm's QMP PHY (used by PCIe, UFS and USB) *) Add new PHY driver for Qualcomm's QUSB2 PHY *) Add support for vbus regulator in rockchip-usb driver *) Add support for usb2-phy in rk3328 to rockchip-inno-usb2 driver *) Add support for a new version of PHY in phy-mt65xx-usb3 driver *) Add support for Allwinner A64 PHY to switch between MUSB and EHCI/OHCI *) Cleanups in Exynos driver and phy-mt65xx-usb3 driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Tobias Regnery authored
With CONFIG_NVMEM=m and CONFIG_PHY_QCOM_QUSB2=y we get a link error from calls to devm_nvmem_cell_get and nvmem_cell_read: drivers/built-in.o: In function `qusb2_phy_probe': binder.c:(.text+0x4750): undefined reference to `devm_nvmem_cell_get' drivers/built-in.o: In function `qusb2_phy_init': binder.c:(.text+0x489c): undefined reference to `nvmem_cell_read' Fix this by adding a Kconfig dependency to ensure we can only have this driver built in when the nvmem functions are also built in or we see the empty stub functions. We can still build this driver as a module when the nvmem core is build as module, too. Fixes: deffad633413 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Sjoerd Simons authored
On rockchip devices vbus is supplied by a separate power supply, often through a regulator. Add support for describing the the regulator in device-tree following the same convention as several other usb phy's. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Rafał Miłecki authored
So far all the PHY initialization was implemented using some totally magic values. There was some pattern there but it wasn't clear what is it about. Thanks to the patch submitted by Broadcom: [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC and the upstream "iproc-mdio" driver we now know there is a MDIO bus underneath with PHY(s) and their registers. It allows us to clean the driver a bit by making all these values less magical. The next step is switching to using a proper MDIO layer. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Vivek Gautam authored
Qualcomm SOCs have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Add a new driver, based on generic phy framework, for this phy controller. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Vivek Gautam authored
Qualcomm chipsets have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Adding dt binding information for the same. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Vivek Gautam authored
PHY transceiver driver for QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller present on Qualcomm chipsets. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Vivek Gautam authored
Qualcomm chipsets have QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller. Adding dt binding information for the same. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Meng Dongyang authored
Add usb2-phy config information in the data of match table for rk3328. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Meng Dongyang authored
Adds the device tree bindings description for usb2-phy grf of RK3328 platform. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Meng Dongyang authored
On some platform such as RK3328, the 480m clock may need to assign clock parent in dts in stead of clock driver. So this patch add property of assigned-clocks and assigned-clock-parents to assign parent for 480m clock. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
add a new compatible string for "mt2712", and move reference clock into each port node; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
There will be a problem if SS port is diasbled and HS port extracts 100uA from SS port, so disable extract 100uA from SS port in the case, when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port only works on LS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
There are some variations from mt2701 to mt2712: 1. banks shared by multiple ports are put back into each port, such as SPLLC and U2FREQ; 2. add a new bank MISC for u2port, and CHIP for u3port; 3. bank's offset in each port are also rearranged; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
each port has its own reference clock, the HighSpeed port is 48M, and the SuperSpeed port is usually 26M, put them into port node for flexibility, this can close clock if the port is not used. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
Currently usb3 port in fact includes two sub-ports, but it is not flexible for some cases, such as following one: usb3 port0 includes u2port0 and u3port0; usb2 port0 includes u2port1; If wants to support only HS, we can use u2port0 or u2port1, when select u2port0, u3port0 is not needed; If wants to support SS, we can compound u2port0 and u3port0, or u2port1 and u3port0, if select latter one, u2port0 is not needed. So it's more flexible to split usb3 port into two ones and also try best to save power by disabling unnecessary ports. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
Increase LFPS filter threshold to avoid some fake remote wakeup signal which cause U3 link fail and link to U2 only at about 0.01% probability. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Chunfeng Yun authored
The default value of RX detection stable time is 10us, and this margin is too big for some critical cases which cause U3 link fail and link to U2(probability is about 1%). So change it to 5us. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
Allwinner A64 SoC features a switchable PHY0 like the one in H3, which can switch between a MUSB controller and a pair of OHCI/EHCI controller. Enable PHY0 route auto switching for A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Yoshihiro Shimoda authored
This patch fixes an issue that this driver doesn't take care of the runtime PM. This code assumed that devm_phy_create() called pm_runtime_enable(dev), but it misunderstood the dev_phy_create()'s specification. This driver should call its own pm_runtime_enable() before dev_phy_create(). Fixes: f3b5a8d9 ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Colin Ian King authored
trivial fix to spelling mistake in dev_dbg message, also rejoin lines to clean up checkpatch warning Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Krzysztof Kozlowski authored
There is no need for separate defines for Exynos4 and Exynos5 phy enable bit and MIPI phy reset bits. In both cases there are the same so simplify it. This reduces number of defines and allows removal of one header file. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfdKishon Vijay Abraham I authored
Immutable branch between MFD and PHY due for the v4.12 merge window
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Krzysztof Kozlowski authored
Exynos4 MIPI phy registers are defined with macro calculating the offset for given phyN. Use the same method for Exynos5420 to be consistent. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Krzysztof Kozlowski authored
Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. This reduces number of defines. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Krzysztof Kozlowski authored
Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. Additionally MIPI PHY registers for Exynos5433 start from the same address as Exynos4 and Exynos5250 so re-use existing defines. This reduces number of defines and allows removal of one header file. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Martin Blumenstingl authored
The register offsets for REG_DBG_UART (and all following) were off by 0x4. This was not a problem yet because these registers are currently not used by the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both MUSB controller for peripheral and host support (the host support is slightly broken), and a pair of EHCI/OHCI controllers, which provide a better support for host mode. Add support for automatically switch the route of PHY0 according to the status of dr_mode and id det pin. Only H3 have this function enabled in this patch, as further SoCs will be tested later and then have it enabled. As H5 is reusing the PHY driver of H3, this function is also enabled. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. From the BSP source code, we know that the offset should be 0x10. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
It seems that all SoCs with the PHYCTL register offset as 0x10 need the PHYCTL register to be cleared before it's written. Change PHYCTL register clearing code to judge whether clearing is needed based on the PHYCTL offset. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Icenowy Zheng authored
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Krzysztof Kozlowski authored
The MFD-specific header will go away because it duplicates defines from exynos-regs-pmu.h. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Paul Gortmaker authored
The Kconfig currently controlling compilation of this code is: drivers/phy/Kconfig:config PHY_EXYNOS_PCIE drivers/phy/Kconfig: bool "Exynos PCIe PHY driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- 08 Apr, 2017 7 commits
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Yuyang Du authored
The commit 0775a9cb ("usbip: vhci extension: modifications to vhci driver") introduced multiple controllers, and nports as a sys file, and claimed to read the nports from it, but it didn't. In addition, the get_nports() has been so wrong that even with 8 port lines for instance, it gets 7 (I am guessing it is due to a '\n' mess). Nevertheless, we fix it by reading the nports attribute. Reviewed-by: Krzysztof Opasiak <k.opasiak@samsung.com> Signed-off-by: Yuyang Du <yuyang.du@intel.com> Acked-by: Shuah Khan <shuahkh@osg.samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Roger Quadros authored
As per [1] issue #4, "The periodic EP scheduler always tries to schedule the EPs that have large intervals (interval equal to or greater than 128 microframes) into different microframes. So it maintains an internal counter and increments for each large interval EP added. When the counter is greater than 128, the scheduler rejects the new EP. So when the hub re-enumerated 128 times, it triggers this condition." This results in Bandwidth error when devices with periodic endpoints (ISO/INT) having bInterval > 7 are plugged and unplugged several times on a TUSB73x0 XHCI host. Workaround this issue by limiting the bInterval to 7 (i.e. interval to 6) for High-speed or faster periodic endpoints. [1] - http://www.ti.com/lit/er/sllz076/sllz076.pdf Cc: stable <stable@vger.kernel.org> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lu Baolu authored
Replace 'TRB_FIELD_TO_TYPE(field3)' with 'type' to simplify code. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lu Baolu authored
xhci_decode_trb() treats a link trb in the same way as that for an event trb. This patch fixes this by decoding the link trb according to the spec. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lu Baolu authored
XHCI context changes have already been traced by the trace events. It's unnecessary to put the same message in kernel log. This patch removes the use of xhci_dbg_ctx(). Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lu Baolu authored
Every XHCI TRB has already been traced by the trb trace events. It is unnecessary to put the same message in kernel log. This patch removes xhci_debug_trb(). Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lu Baolu authored
XHCI ring changes have already been traced by the ring trace events. It's unnecessary to put the same messages in kernel log. This patch removes the debugging code for a ring. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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