Skip to content

O
ORS Hardware
Commit 6b3340d7 authored by Yuanxiang PAN's avatar Yuanxiang PAN
Browse files
Options

Small changement on Signal Track by Jean-Marc

parent c41ae3e9
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 330239 additions and 329626 deletions
hardOrsTypeC/Design Rule Check - OrsTypeC.drc 0 → 100644
View file @ 6b3340d7
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
Date : 04/05/2023
Time : 11:33:00
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:18
\ No newline at end of file
hardOrsTypeC/Design Rule Check - OrsTypeC.html 0 → 100644
View file @ 6b3340d7
This diff is collapsed.
hardOrsTypeC/ORS_TypeC_8Layers.OutJob
View file @ 6b3340d7
This diff is collapsed.
hardOrsTypeC/Ors.PrjPcbStructure
View file @ 6b3340d7
Record=TopLevelDocument|FileName=Ors_Top.SchDoc Record=TopLevelDocument|FileName=Ors_Top.SchDoc
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Supply_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Supply_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Prog.SchDoc|SymbolType=Normal|RawFileName=Ors_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator= |SchDesignator= |FileName=Ors_Prog.SchDoc|SymbolType=Normal|RawFileName=Ors_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=root|SchDesignator=root|FileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|SymbolType=Normal|RawFileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=root|SchDesignator=root|FileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|SymbolType=Normal|RawFileName=Ors_0.SchDoc; Ors_1.SchDoc; Ors_2.SchDoc; Ors_3.SchDoc; Ors_4.SchDoc; Ors_5.SchDoc; Ors_6.SchDoc; Ors_7.SchDoc; Ors_8.SchDoc; Ors_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=Ors_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=Ors_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=Ors_Supply_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=Ors_Supply_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=Ors_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=Ors_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=Ors_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=Ors_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hardOrsTypeC/OrsTypeC.PrjPcb
View file @ 6b3340d7
This diff is collapsed.
hardOrsTypeC/OrsTypeC.PrjPcbStructure
View file @ 6b3340d7
Record=TopLevelDocument|FileName=OrsTypeC_Top.SchDoc Record=TopLevelDocument|FileName=OrsTypeC_Top.SchDoc
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=OrsTypeC_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=OrsTypeC_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=OrsTypeC_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=OrsTypeC_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Supply_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Supply_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Prog.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeC_Prog.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=root|SchDesignator=root|FileName=OrsTypeC_0.SchDoc; OrsTypeC_1.SchDoc; OrsTypeC_2.SchDoc; OrsTypeC_3.SchDoc; OrsTypeC_4.SchDoc; OrsTypeC_5.SchDoc; OrsTypeC_6.SchDoc; OrsTypeC_7.SchDoc; OrsTypeC_8.SchDoc; OrsTypeC_9.SchDoc;|SymbolType=Normal|RawFileName=OrsTypeC_0.SchDoc; OrsTypeC_1.SchDoc; OrsTypeC_2.SchDoc; OrsTypeC_3.SchDoc; OrsTypeC_4.SchDoc; OrsTypeC_5.SchDoc; OrsTypeC_6.SchDoc; OrsTypeC_7.SchDoc; OrsTypeC_8.SchDoc; OrsTypeC_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=root|SchDesignator=root|FileName=OrsTypeC_0.SchDoc; OrsTypeC_1.SchDoc; OrsTypeC_2.SchDoc; OrsTypeC_3.SchDoc; OrsTypeC_4.SchDoc; OrsTypeC_5.SchDoc; OrsTypeC_6.SchDoc; OrsTypeC_7.SchDoc; OrsTypeC_8.SchDoc; OrsTypeC_9.SchDoc;|SymbolType=Normal|RawFileName=OrsTypeC_0.SchDoc; OrsTypeC_1.SchDoc; OrsTypeC_2.SchDoc; OrsTypeC_3.SchDoc; OrsTypeC_4.SchDoc; OrsTypeC_5.SchDoc; OrsTypeC_6.SchDoc; OrsTypeC_7.SchDoc; OrsTypeC_8.SchDoc; OrsTypeC_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=OrsTypeC_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=OrsTypeC_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=OrsTypeC_Supply_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeC_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=OrsTypeC_Supply_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeC_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hardOrsTypeC/Project Outputs for OrsTypeC/Design Rule Check - OrsTypeC.drc 0 → 100644
View file @ 6b3340d7
Protel Design System Design Rule Check
PCB File : V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
Date : 04/05/2023
Time : 11:40:04
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:02:18
\ No newline at end of file
hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files-macro.APR_LIB
View file @ 6b3340d7
This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files.EXTREP
View file @ 6b3340d7
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 5/3/2023 5:23:37 PM Gerber File Extension Report For: Gerber Files.GBR 04/05/2023 11:59:09
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
Layer Extension Layer Description Layer Extension Layer Description
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
.GTL TOP .GTL TOP
.G1 L2 .G1 L2
.G2 L3 .G2 L3
.G3 L4 .G3 L4
.G4 L5 .G4 L5
.G5 L6 .G5 L6
.G6 L7 .G6 L7
.GBL BOTTOM .GBL BOTTOM
.GTO Top Overlay .GTO Top Overlay
.GTP Top Paste .GTP Top Paste
.GTS Top Solder .GTS Top Solder
.GBS Bottom Solder .GBS Bottom Solder
.GBP Bottom Paste .GBP Bottom Paste
.GBO Bottom Overlay .GBO Bottom Overlay
.GM1 Mechanical 1 .GM1 Mechanical 1
.GM2 Mechanical 2 .GM2 Mechanical 2
.GM3 Mechanical 3 .GM3 Mechanical 3
.GM7 SOLE_EDGE-V4 .GM7 SOLE_EDGE-V4
.GM13 DIMENSION .GM13 DIMENSION
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
hardOrsTypeC/Project Outputs for OrsTypeC/Gerber/Gerber Files.RUL
View file @ 6b3340d7
DRC Rules Export File for PCB: Z:\ors-hardware\hardOrsTypeC\OrsTypeC.PcbDoc DRC Rules Export File for PCB: V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78 RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27 RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87 RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72 RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87 RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69 RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69 RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94 RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0 RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94 RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97 RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62 RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94 RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27 RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72 RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
hardOrsTypeC/Project Outputs for OrsTypeC/NC Drill/NC Drill Files-NonPlated.TXT
View file @ 6b3340d7
M48 M48
;Layer_Color=9474304 ;Layer_Color=9474304
;FILE_FORMAT=4:3 ;FILE_FORMAT=4:3
METRIC,TZ METRIC,TZ
;TYPE=NON_PLATED ;TYPE=NON_PLATED
T7F00S00C1.000 T7F00S00C1.000
% %
T07 T07
X325250Y204650 X325250Y204650
Y209350 Y209350
X242150Y269900 X242150Y269900
X325255Y255805 X325255Y255805
Y251105 Y251105
X325250Y243850 X325250Y243850
Y239150 Y239150
X242150Y279900 X242150Y279900
M30 M30
hardOrsTypeC/Project Outputs for OrsTypeC/NC Drill/NC Drill Files.DRR
View file @ 6b3340d7
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
NCDrill File Report For: OrsTypeC.PcbDoc 5/3/2023 5:23:47 PM NCDrill File Report For: OrsTypeC.PcbDoc 04/05/2023 11:59:23
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM Layer Pair : TOP to BOTTOM
ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT
ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel Tool Hole Size Hole Type Hole Count Plated Tool Travel
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2465 4593.09 mm (180.83 Inch) T1 0.2mm (7.874mil) Round 2464 4600.70 mm (181.13 Inch)
T2 0.25mm (9.842mil) Round 1798 4540.06 mm (178.74 Inch) T2 0.25mm (9.842mil) Round 1798 4540.06 mm (178.74 Inch)
T3 0.3mm (11.811mil) Round 224 929.30 mm (36.59 Inch) T3 0.3mm (11.811mil) Round 224 929.30 mm (36.59 Inch)
T4 0.5mm (19.685mil) Round 34 313.99 mm (12.36 Inch) T4 0.5mm (19.685mil) Round 34 313.99 mm (12.36 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch) T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch) T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch) T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
Totals 4550 11362.96 mm (447.36 Inch) Totals 4549 11370.57 mm (447.66 Inch)
Total Processing Time (hh:mm:ss) : 00:00:01 Total Processing Time (hh:mm:ss) : 00:00:02
hardOrsTypeC/Project Outputs for OrsTypeC/NC Drill/NC Drill Files.LDP
View file @ 6b3340d7
Layer Pairs Export File for PCB: Z:\ors-hardware\hardOrsTypeC\OrsTypeC.PcbDoc Layer Pairs Export File for PCB: V:\Work\Projets\RapidSpaceLocal\orsPanHardware\hardOrsTypeC\OrsTypeC.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
hardOrsTypeC/Project Outputs for OrsTypeC/Pick Place/Pick Place for OrsTypeC(TDDB39).txt
View file @ 6b3340d7
This source diff could not be displayed because it is too large. You can view the blob instead.
hardOrsTypeC/Project Outputs for OrsTypeC/Status Report.Txt 0 → 100644
View file @ 6b3340d7
Output: NC Drill Files
Type : NC Drill
From : PCB Document [OrsTypeC.PcbDoc]
Generated File[NC Drill Files-Plated.TXT]
Generated File[NC Drill Files-NonPlated.TXT]
Generated File[NC Drill Files.LDP]
Generated File[NC Drill Files.DRR]
Files Generated : 4
Documents Printed : 0
Finished Output Generation At 11:59:25 On 04/05/2023
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7