add support for lx2160a cex6 internal evaluation board

patches/linux-LSDK-21.08/0074-phy-lynx-28g-add-support-for-specifying-unmanaged-la.patch

+From 160ad4b60348b152b668700908541e51b62b803b Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 27 Aug 2023 14:55:49 +0200
+Subject: [PATCH] phy: lynx-28g: add support for specifying unmanaged lanes
+
+Some lanes migt be used for non-networking purposes such as PCI-Express.
+Add new device-tree property "fsl,unmanaged-lanes" for passing a bitmask
+of unmanaged lanes which the driver will not touch.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ .../devicetree/bindings/phy/fsl,lynx-28g.yaml |  6 ++++++
+ drivers/phy/freescale/phy-fsl-lynx-28g.c      | 19 ++++++++++++++++++-
+ 2 files changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
+index 4d91e2f4f247..71ff57927e32 100644
+--- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
++++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
+@@ -20,6 +20,12 @@ properties:
+   "#phy-cells":
+     const: 1
+ 
++  fsl,unmanaged-lanes:
++    $ref: /schemas/types.yaml#definitions/uint8
++    description: Select which lanes not to touch via bitmask: 0 = managed by driver, 1 = unmanaged.
++    minimum: 0
++    maximum: 255
++
+ required:
+   - compatible
+   - reg
+diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
+index 2152066f2dbc..7e088fa4efce 100644
+--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
++++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
+@@ -5,6 +5,7 @@
+ #include <linux/phy.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/property.h>
+ #include <linux/workqueue.h>
+ #include <linux/workqueue.h>
+ 
+@@ -644,7 +645,9 @@ static int lynx_28g_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct phy_provider *provider;
+ 	struct lynx_28g_priv *priv;
+-	int i;
++	struct fwnode_handle *fwnode;
++	int i, ret;
++	u32 unmanaged_lanes;
+ 
+ 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -655,12 +658,26 @@ static int lynx_28g_probe(struct platform_device *pdev)
+ 	if (IS_ERR(priv->base))
+ 		return PTR_ERR(priv->base);
+ 
++	fwnode = dev_fwnode(dev);
++	if (fwnode && is_of_node(fwnode)) {
++		ret = of_property_read_u32(to_of_node(fwnode), "fsl,unmanaged-lanes", &unmanaged_lanes);
++		if (ret) {
++			dev_info(dev, "failed to read fsl,unmanaged-lanes property: %d\n", ret);
++			return ret;
++		}
++	}
++
+ 	lynx_28g_pll_read_configuration(priv);
+ 
+ 	for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
+ 		struct lynx_28g_lane *lane = &priv->lane[i];
+ 		struct phy *phy;
+ 
++		if (unmanaged_lanes & (1 << i)) {
++			dev_err(dev, "unmanaged lane %d!\n", i);
++			continue;
++		}
++
+ 		memset(lane, 0, sizeof(*lane));
+ 
+ 		phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops);
+-- 
+2.35.3
+

patches/rcw-LSDK-21.08/0030-add-lx2160a-cex6-evb-configuration-3_3_2.patch

+From fd36f76e50577fbf3f4bb3bc6fce3ce2ad91b0ae Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 27 Aug 2023 13:19:59 +0200
+Subject: [PATCH] add lx2160a cex6 evb configuration 3_3_2
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ lx2160acex7/configs/lx2160acex6_evb.rcwi      | 20 +++++++++++++++++++
+ .../configs/lx2160acex6_evb_SD1_3.rcwi        | 18 +++++++++++++++++
+ .../configs/lx2160acex6_evb_SD2_3.rcwi        | 18 +++++++++++++++++
+ .../configs/lx2160acex6_evb_SD3_2.rcwi        | 18 +++++++++++++++++
+ 4 files changed, 74 insertions(+)
+ create mode 100644 lx2160acex7/configs/lx2160acex6_evb.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160acex6_evb.rcwi b/lx2160acex7/configs/lx2160acex6_evb.rcwi
+new file mode 100644
+index 0000000..9daf8fd
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160acex6_evb.rcwi
+@@ -0,0 +1,20 @@
++/* Configure Ethernet Controller 2 Pins as GPIOs */
++EC2_PMUX=1
++
++/* Configure IIC4 for i2c */
++IIC4_PMUX=0
++
++/* Configure IIC5 for spi */
++IIC5_PMUX=3
++
++/* Configure UART1 for uart-1 */
++UART1_SOUTSIN_PMUX=0
++
++/* Configure UART1 RTS/CTS for uart-3
++UART1_RTSCTS_PMUX=2
++
++/* Configure UART2 for uart-2 */
++UART2_SOUTSIN_PMUX=0
++
++/* Configure UART1 RTS/CTS for uart-4 */
++UART2_RTSCTS_PMUX=2
+diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
+new file mode 100644
+index 0000000..7f5f35f
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
+@@ -0,0 +1,18 @@
++/* Serdes 1 Protocol 3: 4x10Gbps + 1xPCI-e-x4 */
++SRDS_PRTCL_S1=3
++
++/* Enable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=0
++
++/* Don't use Serdes 1 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=0
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for pcie: Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM) for usxgmii: Bit 1 = 1
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
+new file mode 100644
+index 0000000..d5f2acb
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
+@@ -0,0 +1,18 @@
++/* Serdes 2 Protocol 3: 2xPCI-e-x4 */
++SRDS_PRTCL_S2=3
++
++/* Enable Serdes 2 PLLF */
++SRDS_PLL_PD_PLL3=0
++
++/* Don't use Serdes 2 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S2=0
++
++/* Enable Serdes 2 PLLS */
++SRDS_PLL_PD_PLL4=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz (Bit 0)
++ * Select Serdes 2 PLLS frequency 100MHz (Bit 1)
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S2=0
+diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
+new file mode 100644
+index 0000000..568fa4d
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
+@@ -0,0 +1,18 @@
++/* Serdes 3 Protocol 2: 1xPCI-e-x8 */
++SRDS_PRTCL_S3=2
++
++/* Disable Serdes 3 PLLF */
++SRDS_PLL_PD_PLL5=1
++
++/* Don't use Serdes 3 PLLF as reference for PLLS */
++SRDS_INTRA_REF_CLK_S3=0
++
++/* Enable Serdes 3 PLLS */
++SRDS_PLL_PD_PLL6=0
++
++/*
++ * Select Serdes 2 PLLF frequency 100MHz (don't care) (Bit 0)
++ * Select Serdes 2 PLLS frequency 100MHz for pcie (Bit 1)
++ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S3=0
+-- 
+2.35.3
+

runme.sh

@@ -132,6 +132,11 @@ case "${SERDES}" in
 		DPC=dpc-6x25g.dtb
 		DPL=dpl-eth.6x25g.21.dtb
 	;;
+	LX2160ACEX6_EVB_3_3_2)
+		DPC=LX2160-CEX6/evb-s1_3-s2-3-dpc.dtb
+		DPL=LX2160-CEX6/evb-s1_3-s2-3-dpl.dtb
+		DEFAULT_FDT_FILE="fsl-lx2160a-cex6.dtb"
+	;;
 	LX2162A_CLEARFOG_0_0_*)
 		DPC=LX2162-USOM/clearfog-s1_0-s2_0-dpc.dtb
 		DPL=LX2162-USOM/clearfog-s1_0-s2_0-dpl.dtb