- 24 May, 2019 40 commits
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Vitaly Prosyak authored
[Why & How] Reuse existent code path and in order to do that apply de gamma in 1D blender LUT and re use MPC OGAM. Follow up is required. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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SivapiriyanKumarasamy authored
[Why] The DPMS state of a display should not impact whether we want to enable fast boot. Currently fast boot is not enabled when resuming from S4 because of this. [How] Remove check for DPMS state when determining if fast boot can be applied. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Many IGT tests require CRC capture in order to confirm that the output is visually correct. These skip on dce120 because configure_crc and get_crc aren't set. [How] Hook up is_tg_enabled, configure_crc and get_crc functions on dce120's timing generator. The logic should be the same as DCE and DCN with some minor register naming differences. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
David Francis <David.Francis@amd.com> Acked-by:
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Charlene Liu authored
add these parameters for future use Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Evan Quan authored
Support hotspot and memory temperature retrieval on sw smu routine. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Support realtime uclk activity report. Signed-off-by:
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Evan Quan authored
Request too frequently may get corrupt data. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Evan Quan authored
Support ppfeatures sysfs interface on Vega20 sw smu routine. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Evan Quan authored
smu_get_clk_info_from_vbios() was called repeatedly. It seems a merge error. Signed-off-by:
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Evan Quan authored
There is already sw smu check on IP block adding. Signed-off-by:
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Harry Wentland authored
[WHY] These were only needed for bringup. They're not needed anymore. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Harry Wentland authored
[WHY] Some early Raven boards had a bad SBIOS that doesn't play nicely with the DMCU FW. We thought the issues were fixed by ignoring errors on DMCU load but that doesn't seem to be the case. We've still seen reports of users unable to boot their systems at all. [HOW] Disable DMCU load on Raven 1. Only load it for Raven 2 and Picasso. v2: Fix ifdef (Alex) Signed-off-by:
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Harry Wentland authored
[WHY] We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1. Signed-off-by:
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Ori Messinger authored
Firmware versions can be found as separate sysfs files at: /sys/class/drm/cardX/device/fw_version (where X is the card number) The firmware versions are displayed in hexadecimal. v2: Moved sysfs files to subfolder Signed-off-by:
Ori Messinger <ori.messinger@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Leo Liu authored
It should be attached to VCN 1.0 Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
Since this is VCN specific and only used by VCN Signed-off-by:
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Tiecheng Zhou authored
it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by:
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Monk Liu authored
only report once per TMO job and the timer would be restarted upon the job finished if it's just slow. Suggested-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Christian König authored
As far as we know this was never used by userspace and so should be removed. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Evan Quan authored
Update Vega10 ACG Avfs GB parameters. Signed-off-by:
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Evan Quan authored
On OD reset, the clock tables in SMU need to be reset to default. Signed-off-by:
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Evan Quan authored
Update Vega10 top performance level power state accordingly on OD. Signed-off-by:
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Evan Quan authored
No need to enable or disable AVFS if it's already in wanted state. Signed-off-by:
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Evan Quan authored
With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS will be disabled. However, the buggy code makes this actually not working as expected. - V2: clear all OD flags excpet DPMTABLE_OD_UPDATE_VDDC Signed-off-by:
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Evan Quan authored
This may affects the Vega10 MCLK OD functionality. Signed-off-by:
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Leo Liu authored
To replace checking ring type and make them generic Signed-off-by:
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Leo Liu authored
There is no user fence support for VCN Signed-off-by:
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Leo Liu authored
There is no user fence support for VCE Signed-off-by:
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Leo Liu authored
There is no user fence support for UVD Signed-off-by:
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Leo Liu authored
So we can generalize the no user fence supported engine Signed-off-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Tested-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
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xinhui pan authored
During S3/S4 bootloader will re-init ras state behind us. Resume might fail or raise a gpu reset. Signed-off-by:
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xinhui pan authored
suspend/resume will change ras state behind us. Let driver get notified. Signed-off-by:
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xinhui pan authored
add ras suspend function. rename ras_post_init to amdgpu_ras_resume. Signed-off-by:
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xinhui pan authored
add badpages node. it will output badpages list in format gpu pfn : gpu page size : flags example 0x00000000 : 0x00001000 : R 0x00000001 : 0x00001000 : R 0x00000002 : 0x00001000 : R 0x00000003 : 0x00001000 : R 0x00000004 : 0x00001000 : R 0x00000005 : 0x00001000 : R 0x00000006 : 0x00001000 : R 0x00000007 : 0x00001000 : P 0x00000008 : 0x00001000 : P 0x00000009 : 0x00001000 : P flags can be one of below characters R: reserved. P: pending for reserve. F: failed to reserve for some reasons. Signed-off-by:
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James Zhu authored
During S3 test, when system wake up and resume, ras interface is already allocated. Move workaround before ras jumps to resume step in gfx_v9_0_ecc_late_init, and make sure workaround applied during resume. Also remove unused mmGB_EDC_MODE clearing. Signed-off-by:
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Wang Hai authored
Fix the following sparse warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:483:21: warning: symbol 'dce120_clock_source_create' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:506:6: warning: symbol 'dce120_clock_source_destroy' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.c:513:6: warning: symbol 'dce120_hw_sequencer_create' was not declared. Should it be static? Fixes: b8fdfcc6 ("drm/amd/display: Add DCE12 core support") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wang Hai <wanghai26@huawei.com> Signed-off-by:
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Trigger Huang authored
Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC to program some registers if supported Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Reviewed-by:
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