- 14 Jul, 2023 3 commits
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Konrad Dybcio authored
ChromeOS folks reported that bwmon is too slow and getting rid of statically defined CPUFREQ-based votes (effectively floor votes because of how opp-peak-kBps is interpreted), has a major performance impact in some common applications. Bring them back until MEMLAT support is introduced. This is a partial revert of the commit referenced in the fixes tag. Fixes: adc16b84 ("arm64: dts: qcom: sc7180: Hook up BWMONs") Reported-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230711-topic-7180ddr-v1-1-56e4f13afe9b@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm6350. There are 3 more NPU BWMONs, but these are skipped for now. Signed-off-by:
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Konrad Dybcio authored
Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm8250. LPDDR4X levels are skipped, as LPDDR5 seems more popular with SM8250 and voting for inexistent levels doesn't uptick the bus frequency, which results in no increased bandwidth, which results in bwmon deciding we shouldn't go higher.. you see the point! Signed-off-by:
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- 13 Jul, 2023 1 commit
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Dmitry Baryshkov authored
Turn CBF into the interconnect provider. Scale CBF frequency (bandwidth) according to CPU frequencies. Reviewed-by:
Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512001334.2983048-5-dmitry.baryshkov@linaro.orgSigned-off-by:
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- 10 Jul, 2023 36 commits
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Konrad Dybcio authored
The SMMUs on SM8250 are cache-coherent. Mark them as such. Fixes: a89441fc ("arm64: dts: qcom: sm8250: add apps_smmu node") Fixes: 04a3605b ("arm64: dts: qcom: add sm8250 GPU nodes") Signed-off-by:
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Konrad Dybcio authored
The PCIe hosts on SM8250 are cache-coherent. Mark them as such. Fixes: e53bdfc0 ("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by:
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Dmitry Baryshkov authored
Add thermal zones controlled through the ADC-TM (ADC thermal monitoring) PMIC interface. This includes several onboard sensors and the XO thermal sensor. Signed-off-by:
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Dmitry Baryshkov authored
Declare the DIE_TEMP channels provided by PMICs. Use them to provide temperature reading for the spmi-temp-alarm thermal zones. Reviewed-by:
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Dmitry Baryshkov authored
The 8450-HDK doesn't use PMR735B PMIC. Drop its inclusion to remove the warning during the HDK bootup. Fixes: 30464456 ("arm64: dts: qcom: sm8450-hdk: add pmic files") Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
The commit b2de4313 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") for the ADC TM (thermal monitoring device) have used the compatible string from the vendor kernel ("qcom,adc-tm7"). Use the proper compatible string that is defined in the upstream kernel ("qcom,spmi-adc-tm5-gen2"). Fixes: b2de4313 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") Reviewed-by:
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Dmitry Baryshkov authored
The name of the thermal zone in pmr735b.dtsi (pmr735a-thermal) conflicts with the thermal zone in pmr735a.dtsi. Rename the thermal zone according to the chip name. Fixes: 6f3426b3 ("arm64: dts: qcom: pmr735b: add temp sensor and thermal zone config") Reviewed-by:
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Dmitry Baryshkov authored
The name of the thermal zone in pm8350b.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 5c139929 ("arm64: dts: qcom: pm8350b: add temp sensor and thermal zone config") Reviewed-by:
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Dmitry Baryshkov authored
The name of the thermal zone in pm8350.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 7a79b95f ("arm64: dts: qcom: pm8350: add temp sensor and thermal zone config") Reviewed-by:
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Konrad Dybcio authored
The Kryo names (once again) turned out to be fake. The CPUs report: 0x412fd050 (CA55 r2p0) (0 - 3) 0x411fd410 (CA78 r1p1) (4 - 6) 0x411fd440 (CX1 r1p1) (7) Use the compatibles that reflect that. Fixes: b7e8f433 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by:
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Konrad Dybcio authored
The value was copypasted from 8150, but 8180 expects a different one. Confirmed with both downstream device tree and Windows DSDT, not tested on hardware (sorry, I don't have any). Fix it. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
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Krzysztof Kozlowski authored
Add missing whitespace between node name/label and opening {. Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Konrad Dybcio authored
Add the missing interrupts that communicate the hardware-managed throttling to Linux. Fixes: ccbb3abb ("arm64: dts: qcom: sm8350: Add cpufreq node") Signed-off-by:
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Konrad Dybcio authored
The present values look to have been copypasted from 8150 or 8180. Fix that. Fixes: 07ddb302 ("arm64: dts: qcom: sm8350: Add CPU topology and idle-states") Signed-off-by:
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Konrad Dybcio authored
SM8350's cores can be shut off, without engaging full-on SoC-wide power collapse. Add the missing idle state to allow for that. Signed-off-by:
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Komal Bajaj authored
Add reserve gpios for QRU1000 IDP platform. These gpios are needed for modem subsystem. Signed-off-by:
Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by:
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Komal Bajaj authored
Add reserve gpios for QDU1000 IDP platform. These gpios are needed for modem subsystem. Signed-off-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by:
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Konrad Dybcio authored
The RPMCC node should be fed a reference to the XO fixed clock. Do so. Signed-off-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/20230627-topic-98_rpmcc-v1-1-4024e43ad0fc@linaro.orgSigned-off-by:
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Konrad Dybcio authored
UART6 is used for debug (routed via uSD pins) and UART9 is connected to the bluetooth chip. Set indexed aliases to make the GENI UART driver happy and route serial traffic through the debug uart by default. Fixes: 30a7f99b ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20230627-topic-tama_uart-v1-1-0fa790248db8@linaro.orgSigned-off-by:
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Konrad Dybcio authored
The interrupt line was previously not described. Take care of that. Fixes: 1e39255e ("arm64: dts: msm8996: Add device node for qcom,dwc3") Signed-off-by:
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Konrad Dybcio authored
'pin-switch-delay-us' is not used anywhere in the mainline kernel. Drop it. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-4-6b4b6cd081e5@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Add the missing property to fix the dt checker warning: qcom/apq8039-t2.dtb: l2-cache: 'cache-unified' is a required property Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by:
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Konrad Dybcio authored
As of today, the only cool and legal way to get ARM64 SMP going is via PSCI (or spin tables). Sadly, not all chip and device vendors were considerate of this in the early days of arm64. Qualcomm, for example reused their tried-and-true spin-up method from MSM8974 and their Krait/ arm32 Cortex designs. MSM8916 supports SMP with its arm32 dt overlay, as probably could 8939. But the arm64 DT should not define non-PSCI SMP or CPUidle stuff. Drop the qcom,idle-state-spc compatible (associated with Qualcomm-specific CPUIdle) to make the dt checker happy: apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible: ['qcom,idle-state-spc', 'arm,idle-state'] is too long Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by:
Benjamin Li <benl@squareup.com> Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-2-6b4b6cd081e5@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Commit 2b616f86 ("arm64: dts: qcom: sc7180: rename labels for DSI nodes") broke reg-names, possibly with search-and-replace. Fix it. Fixes: 2b616f86 ("arm64: dts: qcom: sc7180: rename labels for DSI nodes") Signed-off-by:
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Konrad Dybcio authored
Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. They will be replaced with a dynamic, bwmon-style decision maker once support for MEMLAT is introduced upstream. Available values from the HW LUT: 300000 556800 652800 768000 844800 921600 1171200 1382400 1497600 This commit dramatically improves overall performance of the system. Signed-off-by:
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Johan Hovold authored
Unless explicitly specified the interrupt-parent property is inherited from the parent node on Linux even though this may not be in full compliance with the devicetree specification. Following commit 2d5cab92 ("arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly"), add an explicit interrupt parent also for the PMIC RTC node for the benefit of other operating systems which may be confused by this omission. Note that any such OS must still implement a fallback to the root interrupt domain as most devicetrees are written under the assumption that the interrupt parent is inherited. Reported-by:
Patrick Wildt <patrick@blueri.se> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Luca Weiss authored
With the ICE driver now merged let's convert the ufs node to use the new style. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Rob Herring authored
The defined value for "status" is "disabled", not "disable". Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Bjorn Andersson authored
Merge a set of new SC8280XP GCC GDSC constants from a topic branch, in order to allow them being used in DeviceTree source.
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Konrad Dybcio authored
There are 10 more GDSCs that we've not been caring about, and by extension (and perhaps even more importantly), not putting to sleep. Add them. Fixes: a66a82f2 ("dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings") Acked-by:
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Luca Weiss authored
Define the themal zones using the temperature values found in the downstream 4.9 sources so that the spmi-temp-alarm driver becomes active. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Sridharan S N authored
Add a dtsi file to include interfaces that are common across IPQ5332 RDPs. Signed-off-by:
Sridharan S N <quic_sridsn@quicinc.com> Link: https://lore.kernel.org/r/20230623090001.27778-1-quic_sridsn@quicinc.comSigned-off-by:
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Konrad Dybcio authored
The SCM interconnect path was missing. Add it. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Bartosz Golaszewski authored
Enable the first 1Gb ethernet port on sa8775p-ride development board. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.plSigned-off-by:
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Bartosz Golaszewski authored
Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride. Signed-off-by:
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