This is a driver for the complex divider cells found on Marvell Berlin2
SoCs. The cells come in two flavors: single register cells and shared
register cells.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

This is a clock driver for the simple PLLs found on Berlin SoCs.
With repect to PLL registers and features, BG2/BG2CD and BG2Q are
slightly different, e.g. different allowed VCO dividers and bit
shifts.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

This is a driver for the AVPLLs built upon a VCO with 8 channels each
found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share
the same register set, sometimes registers shifts for one of the VCOs
are a bit off. Nothing serious that should require a separate driver,
so deal with both VCOs in a single driver instead.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Failure to terminate this match table can lead to boot failures
depending on where the compiler places the match table.

Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Fixes the following warning:
WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown)
   The function exynos4_clk_sleep_init() references
   the (unknown reference) __initdata (unknown).
   This is often because exynos4_clk_sleep_init lacks a __initdata
   annotation or the annotation of (unknown) is wrong.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes

PLLE fixes for 3.15

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Commit c686078 ("clk: divider: Add round to closest divider") introduced
a helper function to check whether given divisor is the best one instead
of direct check. However due to int type used instead of unsigned long
for passing calculated rates to this function in certain cases an
overflow could occur, for example when trying to obtain maximum possible
clock rate by calling clk_round_rate(..., UINT_MAX).

This patch fixes this issue by changing the type of rate, now and best
arguments of the function to unsigned long, which is the type that
should be used for clock rates.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Failure to terminate this match table can lead to boot failures
depending on where the compiler places the match table.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Implement the clk->determine_rate method for Broadcom Kona peripheral
clocks.  This allows a peripheral clock to be re-parented in order to
satisfy a rate change request.  This takes the place of the previous
kona_peri_clk_round_rate() functionality, though that function remains
because it is used by the new one.

The parent clock that allows the peripheral clock to produce a rate
closest to the one requested is the one selected, though the current
parent is used by default.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

The address of the blsp2_ahb_clk register is incorrect. Fix it.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the
s2mps11 clock driver.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

There is no need for checking if 'clk_table' is not NULL twice (first
after allocation and second at the end of probe()). Also move allocation
of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is
logical place for it.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Add of_clk_del_provider to remove previously registered clock provider.
Add of_node_put to decrement the ref count of clock nodes.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

When it fails to allocate div, gate should be free'd before return
Signed-off-by: Valentin Ilie <valentin.ilie@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and
table dividers") introduces a regression in its _table_round_up function.

When the divider passed to this function is greater than the max divider
available in the table, this function returns table's max divider.
Problem is that it causes an infinite loop in clk_divider_bestdiv() because
_next_div() will never return a value greater than maxdiv.

Instead of returning table's max divider, this patch returns INT_MAX.
Reported-by: Fabio Estevam <festevam@gmail.com>
Reported-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

  - Limit ruler to 80 characters (was: 81),
  - Widen rate column by 1 for nicer spacing,
  - Right-align numbers and their column headers,
  - Move a newline to reduce the number of seq_printf() calls,
  - Use set_puts() for fixed strings.

Before:

   clock                        enable_cnt  prepare_cnt  rate        accuracy
---------------------------------------------------------------------------------
 extal                          2           2            20000000   0
    thermal                     1           1            20000000   0
    cp                          0           0            10000000   0
       tpu0                     0           0            10000000   0
       tmu0                     0           0            10000000   0
    main                        1           1            20000000   0
       pll3                     0           0            1600000000 0
          ddr                   0           0            200000000  0
          zb3d2                 0           0            200000000  0
          zb3                   0           0            400000000  0
       pll1                     4           4            1560000000 0
          oscclk                0           0            126953     0
          rclk                  1           1            31738      0
             cmt1               0           0            31738      0
             cmt0               1           1            31738      0
          imp                   0           0            390000000  0

After:

   clock                         enable_cnt  prepare_cnt        rate   accuracy
--------------------------------------------------------------------------------
 extal                                    2            2    20000000          0
    thermal                               1            1    20000000          0
    cp                                    0            0    10000000          0
       tpu0                               0            0    10000000          0
       tmu0                               0            0    10000000          0
    main                                  1            1    20000000          0
       pll3                               0            0  1600000000          0
          ddr                             0            0   200000000          0
          zb3d2                           0            0   200000000          0
          zb3                             0            0   400000000          0
       pll1                               4            4  1560000000          0
          oscclk                          0            0      126953          0
          rclk                            1            1       31738          0
             cmt1                         0            0       31738          0
             cmt0                         1            1       31738          0
          imp                             0            0   390000000          0
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

From: Heiko Stuebner <heiko@sntech.de>

Similar to muxes which already have a read-only flag there sometimes
exist dividers which should not be changed by the clock framework
but whose value still should be readable.

Therefore add a READ_ONLY flag similar to the mux-one to clk-divider
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[changed flag bit to BIT(5) as suggested by Tomasz Figa]
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Driver for the R8A7740's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Initialize the XUSB-related clocks with appropriate parents and rates
for both Tegra114 and Tegra124.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Enable hardware control of PLLE spread-spectrum, IDDQ, and enable
controls when enabling PLLE.  The hardware (e.g. XUSB) using PLLE
will use these controls for power-saving optimizations.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Add clk driver to support clock blocks found on the AXM55xx devices. The driver
provides clock implementations for three different types of clock devices on
the AXM55xx device: PLL clock, a clock divider and a clock mux.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

The MSTP[SC]R registers have clock stop bits, not clock enable bits. The
bit value should thus be inverted in the is_enabled() operation.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

This patch adds of_clk_get_by_clkspec() helper function, which does only
a struct clk lookup from the clock providers. It is used in the subsequent
patch where parsing of a clock from device tree and the lookup from
providers needed to be split.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

The IM-PD1 PrimeCells all have pclk assignments though this clock
cannot be controlled, and we need to provide this as a dummy
clock for the PL061 GPIO driver to probe, so let's assign it to
all the cells on the board.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Pull two powerpc fixes from Ben Herrenschmidt:
 "Here are a couple of fixes for 3.15.  One from Anton fixes a nasty
  regression I introduced when trying to fix a loss of irq_work whose
  consequences is that we can completely lose timer interrupts on a
  CPU... not pretty.

  The other one is a change to our PCIe reset hook to use a firmware
  call instead of direct config space accesses to trigger a fundamental
  reset on the root port.  This is necessary so that the FW gets a
  chance to disable the link down error monitoring, which would
  otherwise trip and cause subsequent fatal EEH error"

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc: irq work racing with timer interrupt can result in timer interrupt hang
  powerpc/powernv: Reset root port in firmware

Pull two btrfs fixes from Chris Mason:
 "This has two fixes that we've been testing for 3.16, but since both
  are safe and fix real bugs, it makes sense to send for 3.15 instead"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs:
  Btrfs: send, fix incorrect ref access when using extrefs
  Btrfs: fix EIO on reading file after ioctl clone works on it

Pull two ceph fixes from Sage Weil:
 "The first patch fixes a problem when we have a page count of 0 for
  sendpage which is triggered by zfs.  The second fixes a bug in CRUSH
  that was resolved in the userland code a while back but fell through
  the cracks on the kernel side"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph-client:
  crush: decode and initialize chooseleaf_vary_r
  libceph: fix corruption when using page_count 0 page in rbd

Pull xfs fixes from Dave Chinner:
 "Code inspection of the XFS error number sign translations found a
  bunch of issues, including returning incorrectly signed errors for
  some data integrity operations.

  These leak to userspace and result in applications not getting the
  errors correctly reported.  Hence they need fixing sooner rather than
  later.

  A couple of the bugs are in data integrity operations, a couple more
  are in the new COLLAPSE_RANGE code.  One of these came in through a
  recent ext4 merge and so I had to update the base tree to 3.15-rc5
  before fixing the issues"

* tag 'xfs-for-linus-3.15-rc6' of git://oss.sgi.com/xfs/xfs:
  xfs: list_lru_init returns a negative error
  xfs: negate xfs_icsb_init_counters error value
  xfs: negate mount workqueue init error value
  xfs: fix wrong err sign on xfs_set_acl()
  xfs: fix wrong errno from xfs_initxattrs
  xfs: correct error sign on COLLAPSE_RANGE errors
  xfs: xfs_commit_metadata returns wrong errno
  xfs: fix incorrect error sign in xfs_file_aio_read
  xfs: xfs_dir_fsync() returns positive errno

Pull renameat2 arch support from Miklos Szeredi:
 "I've collected architecture patches for the renameat2 syscall that
  maintainers acked and/or asked me to queue.

  This adds architecture support for the renameat2 syscall to m68k,
  parisc, ia64 and through asm-generic to arc, arm64, c6x, hexagon,
  metag, openrisc, score, tile, unicore32"

* 'renameat2' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs:
  scripts/checksyscalls.sh: Make renameat optional
  asm-generic: Add renameat2 syscall
  ia64: add renameat2 syscall
  parisc: add renameat2 syscall
  m68k: add renameat2 syscall

Pull iommu fixes from Joerg Roedel:
 "Three fixes for the AMD IOMMU driver:
   - fix a locking issue around get_user_pages()
   - fix two issues with device aliasing and exclusion range handling"

* tag 'iommu-fixes-v3.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu/amd: fix enabling exclusion range for an exact device
  iommu/amd: Take mmap_sem when calling get_user_pages
  iommu/amd: Fix interrupt remapping for aliased devices

Merge tag 'stable/for-linus-3.15-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/ibft

Pull iscsi_ibft fix from Konrad Rzeszutek Wilk:
 "Fix iBFT regression on Broadcom NICs introduced in 3.2"

* tag 'stable/for-linus-3.15-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/ibft:
  iscsi_ibft: Fix finding Broadcom specific ibft sign

Merge tag 'renesas-sh-drivers-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

Pull SH driver fix from Simon Horman:
 "Compile drivers/sh/pm_runtime.c if ARCH_SHMOBILE_MULTI

  This resolves a regression introduced in v3.14 by commit bf98c1ea
  ("ARM: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY")"

* tag 'renesas-sh-drivers-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  drivers: sh: compile drivers/sh/pm_runtime.c if ARCH_SHMOBILE_MULTI