- 08 Feb, 2023 4 commits
-
-
Konrad Dybcio authored
SM6115's SMMU uses 36bit VAs, which is a good indicator that we should increase (dma-)ranges - and by extension #address- and #size-cells to prevent things from getting lost in translation (both literally and figuratively). Do so. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230119101644.10711-2-konrad.dybcio@linaro.org
-
Konrad Dybcio authored
Add a mdss_ prefix to mdss nodes to keep them all near each other when referencing them by label in device DTs. Signed-off-by:
-
Yang Xiwen authored
This commit adds support for the ufi-001C and uf896 WiFi/LTE dongle made by Tong Heng Wei Chuang based on MSM8916. uf896 is another variant for the usb stick. The board design differs by using different gpios for the keys and leds. Note: The original firmware does not support 64-bit OS. It is necessary to flash 64-bit TZ firmware to boot arm64. Currently supported: - All CPU cores - Buttons - LEDs - Modem - SDHC - USB Device Mode - UART Co-developed-by:
Jaime Breva <jbreva@nayarsystems.com> Signed-off-by:
Nikita Travkin <nikita@trvn.ru> Signed-off-by:
Yang Xiwen <forbidden405@foxmail.com> Signed-off-by:
-
Bhupesh Sharma authored
qup0 on sm6115 / sm4250 has 6 SEs, with SE4 as debug uart. Add the debug uart node in sm6115 dtsi file. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
-
- 06 Feb, 2023 1 commit
-
-
Krzysztof Kozlowski authored
Add the ADSP GPR (Generic Packet Router) and LPASS LPI (Low Power Audio SubSystem Low Power Island) pin controller nodes used as part of audio subsystem on SM8550. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
-
- 03 Feb, 2023 2 commits
-
-
Rajendra Nayak authored
Some of the qualcomm qcard based herobrine devices can come with a Pro variant of the chipset on the qcard. Such Pro qcards have the smps9 from pm8350c ganged up with smps7 and smps8, so add a .dtsi for pro skus that deletes the smps9 node and include it from the new dts for the CRD Pro Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
-
Konrad Dybcio authored
Nagara is definitely not SM8350, fix it! Fixes: c53532f7 ("arm64: dts: qcom: pdx223: correct firmware paths") Signed-off-by:
-
- 31 Jan, 2023 7 commits
-
-
Dmitry Baryshkov authored
Add the per-SoC (qcom,sm8350-dsi-ctrl) compatible strings to DSI nodes to follow the pending DSI bindings changes. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
-
Dmitry Baryshkov authored
Per DT bindings add p1 register blocks to all DP controllers on SC8280XP platform. Fixes: 6f299ae7f96d ("arm64: dts: qcom: sc8280xp: add p1 register blocks to DP nodes") Signed-off-by: -
Dmitry Baryshkov authored
The eDP device doesn't provide sound DAI. Drop corresponding property from the eDP node. Signed-off-by:
-
Melody Olvera authored
Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 SoCs. Signed-off-by:
Melody Olvera <quic_molvera@quicinc.com> Signed-off-by:
-
Melody Olvera authored
Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller to boot to shell with console on these SoCs. Signed-off-by:
-
Bjorn Andersson authored
Merge DT binding in order to get GCC clock defines.
-
Bjorn Andersson authored
Merge branch 'icc-qdu1000-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD Merge DT binding to gain interconnect defines.
-
- 26 Jan, 2023 7 commits
-
-
Konrad Dybcio authored
Somehow DSI1 was not hooked up to MDP resulting in it not working. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
-
Konrad Dybcio authored
Add the mdss_ prefix to DSIn labels, so that the hardware blocks can be organized near each other while retaining the alphabetical order in device DTs when referencing by label. Signed-off-by:
-
Konrad Dybcio authored
As downstream indicates, DSI PLL is actually 0x27c and not 0x260- wide. Fix that to reserve the correct registers. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
-
Konrad Dybcio authored
The compatibles were wrong, resulting in the driver not probing. Fix that. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
-
Konrad Dybcio authored
This was omitted but is necessary for DSI1 to function. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
-
Konrad Dybcio authored
The interrupt was wrong, likely copypasted from DSI0. Fix it. Fixes: d4a44105 ("arm64: dts: qcom: sm8350: Add display system nodes") Signed-off-by:
-
Konrad Dybcio authored
Panels/DRM bridges definitely don't need 64bits of address space and are usually not 32-bit wide. Set address-cells to 1 and size-cells to 0. Signed-off-by:
-
- 19 Jan, 2023 19 commits
-
-
Sibi Sankar authored
Add a new carveout for modem metadata on SC7280 SoCs. Signed-off-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
-
Sibi Sankar authored
Add a new carveout for modem metadata on SC7180 SoCs. Signed-off-by:
-
Sibi Sankar authored
Add a new carveout for modem metadata on SDM845 SoCs. Tested-by:
Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
-
Sibi Sankar authored
Add a new carveout for modem metadata on MSM8998 SoCs. Signed-off-by:
-
Sibi Sankar authored
Add a new carveout for modem metadata on MSM8996 SoCs. Signed-off-by:
-
Robert Marko authored
Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC driver is relying on the old names to match them as they are being used as the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk. This broke parenting as GCC could not find the parent clock, so fix it by changing to the names that driver is expecting. Fixes: 942bcd33 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by:Robert Marko <robimarko@gmail.com> Signed-off-by:
-
Robert Marko authored
IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Finish the PCIe fixup by using the correct compatible, adding missing ATU register space, declaring max-link-speed, use correct ranges, add missing clocks and resets. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
-
Robert Marko authored
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link generation limit. This allows the generic DWC code to configure the link speed correctly. Signed-off-by:
-
Robert Marko authored
Current ranges property set in Gen2 PCIe node is incorrect, replace it with the downstream 5.4 QCA kernel value. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
-
Robert Marko authored
IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first. Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by:
-
Robert Marko authored
Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel. Fixes: 942bcd33 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by:
-
Krzysztof Kozlowski authored
Geni I2C Controller node does not allow a "label" property and Linux driver does not parse it: sdm845-db845c.dtb: i2c@a8c000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: -
Dmitry Baryshkov authored
In some cases the driver might need using GPLL0 to drive CPU clocks. Bring it in through the sys_apcs_aux clock. Signed-off-by:
-
Melody Olvera authored
Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by:
-
Manivannan Sadhasivam authored
The devicetree should specify both MSI implementations and the OS/driver should choose the one based on the platform requirements. Currently, Linux DWC driver will choose GIC-ITS over the internal MSI controller. Fixes: a11bbf6adef4 ("arm64: dts: qcom: sm8450: Use GIC-ITS for PCIe0 and PCIe1") Suggested-by:Rob Herring <robh@kernel.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
-
Abel Vesa authored
Enable USB HC and PHYs nodes on SM8550 MTP board. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
-
Abel Vesa authored
Add USB host controller and PHY nodes. Signed-off-by:
-
Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-tx-macro bindings nor the driver use "clock-frequency" and address/size cells properties. sm8250-mtp.dtb: txmacro@3220000: Unevaluated properties are not allowed ('clock-frequency', '#address-cells', '#size-cells' were unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-wsa-macro bindings nor the driver use "clock-frequency" property. sm8250-hdk.dtb: codec@3240000: Unevaluated properties are not allowed ('clock-frequency' was unexpected) Signed-off-by:
-
