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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

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#include <linux/dma-resv.h>
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#include <linux/i2c.h>
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#include <linux/input.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/string_helpers.h>
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#include <drm/display/drm_dp_helper.h>
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#include <drm/display/drm_dp_tunnel.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_atomic_uapi.h>
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#include <drm/drm_damage_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_fixed.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_rect.h>
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#include "gem/i915_gem_lmem.h"
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#include "gem/i915_gem_object.h"

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#include "g4x_dp.h"
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#include "g4x_hdmi.h"
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#include "hsw_ips.h"
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#include "i915_config.h"
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "i915_utils.h"
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#include "i9xx_plane.h"
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#include "i9xx_plane_regs.h"
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#include "i9xx_wm.h"
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#include "intel_atomic.h"
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#include "intel_atomic_plane.h"
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#include "intel_audio.h"
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#include "intel_bw.h"
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#include "intel_cdclk.h"
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#include "intel_clock_gating.h"
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#include "intel_color.h"
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#include "intel_crt.h"
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#include "intel_crtc.h"
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#include "intel_crtc_state_dump.h"
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#include "intel_cursor_regs.h"
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#include "intel_cx0_phy.h"
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#include "intel_cursor.h"
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#include "intel_ddi.h"
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#include "intel_de.h"
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#include "intel_display_driver.h"
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#include "intel_display_power.h"
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#include "intel_display_types.h"
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#include "intel_dmc.h"
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#include "intel_dp.h"
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#include "intel_dp_link_training.h"
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#include "intel_dp_mst.h"
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#include "intel_dp_tunnel.h"
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#include "intel_dpll.h"
#include "intel_dpll_mgr.h"
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#include "intel_dpt.h"
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#include "intel_dpt_common.h"
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#include "intel_drrs.h"
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#include "intel_dsb.h"
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#include "intel_dsi.h"
#include "intel_dvo.h"
#include "intel_fb.h"
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#include "intel_fbc.h"
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#include "intel_fdi.h"
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#include "intel_fifo_underrun.h"
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#include "intel_frontbuffer.h"
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#include "intel_hdmi.h"
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#include "intel_hotplug.h"
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#include "intel_link_bw.h"
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#include "intel_lvds.h"
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#include "intel_lvds_regs.h"
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#include "intel_modeset_setup.h"
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#include "intel_modeset_verify.h"
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#include "intel_overlay.h"
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#include "intel_panel.h"
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#include "intel_pch_display.h"
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#include "intel_pch_refclk.h"
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#include "intel_pcode.h"
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#include "intel_pipe_crc.h"
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#include "intel_plane_initial.h"
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#include "intel_pmdemand.h"
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#include "intel_pps.h"
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#include "intel_psr.h"
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#include "intel_psr_regs.h"
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#include "intel_sdvo.h"
#include "intel_snps_phy.h"
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#include "intel_tc.h"
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#include "intel_tdf.h"
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#include "intel_tv.h"
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#include "intel_vblank.h"
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#include "intel_vdsc.h"
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#include "intel_vdsc_regs.h"
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#include "intel_vga.h"
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#include "intel_vrr.h"
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#include "intel_wm.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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#include "skl_universal_plane_regs.h"
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#include "skl_watermark.h"
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#include "vlv_dpio_phy_regs.h"
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#include "vlv_dsi.h"
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#include "vlv_dsi_pll.h"
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#include "vlv_dsi_regs.h"
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#include "vlv_sideband.h"
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static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
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static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
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static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
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static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
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/* returns HPLL frequency in kHz */
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int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
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{
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };

	/* Obtain SKU information */
	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
		CCK_FUSE_HPLL_FREQ_MASK;

	return vco_freq[hpll_freq] * 1000;
}

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int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
		      const char *name, u32 reg, int ref_freq)
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{
	u32 val;
	int divider;

	val = vlv_cck_read(dev_priv, reg);
	divider = val & CCK_FREQUENCY_VALUES;

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	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
		 (divider << CCK_FREQUENCY_STATUS_SHIFT),
		 "%s change in progress\n", name);
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	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}

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int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
			   const char *name, u32 reg)
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{
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	int hpll;

	vlv_cck_get(dev_priv);

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	if (dev_priv->hpll_freq == 0)
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		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
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	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);

	vlv_cck_put(dev_priv);

	return hpll;
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}

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void intel_update_czclk(struct drm_i915_private *dev_priv)
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{
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	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
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		return;

	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
						      CCK_CZ_CLOCK_CONTROL);

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	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
		dev_priv->czclk_freq);
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}

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static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
{
	return (crtc_state->active_planes &
		~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
}

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/* WA Display #0827: Gen9:all */
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static void
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skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
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{
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	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
		     DUPS1_GATING_DIS | DUPS2_GATING_DIS,
		     enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
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}

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/* Wa_2006604312:icl,ehl */
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static void
icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
		       bool enable)
{
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	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
		     DPFR_GATING_DIS,
		     enable ? DPFR_GATING_DIS : 0);
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}

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/* Wa_1604331009:icl,jsl,ehl */
static void
icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
		       bool enable)
{
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	intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
		     CURSOR_GATING_DIS,
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		     enable ? CURSOR_GATING_DIS : 0);
}

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static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
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{
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	return crtc_state->master_transcoder != INVALID_TRANSCODER;
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}

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bool
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is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
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{
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	return crtc_state->sync_mode_slaves_mask != 0;
}

bool
is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
{
	return is_trans_port_sync_master(crtc_state) ||
		is_trans_port_sync_slave(crtc_state);
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}

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static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
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{
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	return ffs(crtc_state->joiner_pipes) - 1;
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}

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u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
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{
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	if (crtc_state->joiner_pipes)
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		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
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	else
		return 0;
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}

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bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

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	return crtc_state->joiner_pipes &&
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		crtc->pipe != joiner_primary_pipe(crtc_state);
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}

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bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

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	return crtc_state->joiner_pipes &&
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		crtc->pipe == joiner_primary_pipe(crtc_state);
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}

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static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state)
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{
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	return hweight8(crtc_state->joiner_pipes);
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}

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u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

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	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
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}

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struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
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{
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	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

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	if (intel_crtc_is_joiner_secondary(crtc_state))
		return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state));
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	else
		return to_intel_crtc(crtc_state->uapi.crtc);
}

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static void
intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	if (DISPLAY_VER(dev_priv) >= 4) {
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		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
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		/* Wait for the Pipe State to go off */
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		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
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					    TRANSCONF_STATE_ENABLE, 100))
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			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
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	} else {
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		intel_wait_for_pipe_scanline_stopped(crtc);
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	}
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}

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void assert_transcoder(struct drm_i915_private *dev_priv,
		       enum transcoder cpu_transcoder, bool state)
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{
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	bool cur_state;
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	enum intel_display_power_domain power_domain;
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	intel_wakeref_t wakeref;
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	/* we keep both pipes enabled on 830 */
	if (IS_I830(dev_priv))
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		state = true;

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	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (wakeref) {
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		u32 val = intel_de_read(dev_priv,
					TRANSCONF(dev_priv, cpu_transcoder));
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		cur_state = !!(val & TRANSCONF_ENABLE);
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		intel_display_power_put(dev_priv, power_domain, wakeref);
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	} else {
		cur_state = false;
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	}

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	I915_STATE_WARN(dev_priv, cur_state != state,
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			"transcoder %s assertion failure (expected %s, current %s)\n",
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			transcoder_name(cpu_transcoder), str_on_off(state),
			str_on_off(cur_state));
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}

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static void assert_plane(struct intel_plane *plane, bool state)
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{
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	struct drm_i915_private *i915 = to_i915(plane->base.dev);
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	enum pipe pipe;
	bool cur_state;

	cur_state = plane->get_hw_state(plane, &pipe);
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	I915_STATE_WARN(i915, cur_state != state,
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			"%s assertion failure (expected %s, current %s)\n",
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			plane->base.name, str_on_off(state),
			str_on_off(cur_state));
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}

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#define assert_plane_enabled(p) assert_plane(p, true)
#define assert_plane_disabled(p) assert_plane(p, false)
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static void assert_planes_disabled(struct intel_crtc *crtc)
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{
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	struct intel_plane *plane;
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	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
		assert_plane_disabled(plane);
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}

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void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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			 struct intel_digital_port *dig_port,
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			 unsigned int expected_mask)
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{
	u32 port_mask;
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	i915_reg_t dpll_reg;
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	switch (dig_port->base.port) {
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	default:
		MISSING_CASE(dig_port->base.port);
		fallthrough;
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	case PORT_B:
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		port_mask = DPLL_PORTB_READY_MASK;
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		dpll_reg = DPLL(dev_priv, 0);
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		break;
	case PORT_C:
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		port_mask = DPLL_PORTC_READY_MASK;
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		dpll_reg = DPLL(dev_priv, 0);
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		expected_mask <<= 4;
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		break;
	case PORT_D:
		port_mask = DPLL_PORTD_READY_MASK;
		dpll_reg = DPIO_PHY_STATUS;
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		break;
	}
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	if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
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		drm_WARN(&dev_priv->drm, 1,
			 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
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			 dig_port->base.base.base.id, dig_port->base.base.name,
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			 intel_de_read(dev_priv, dpll_reg) & port_mask,
			 expected_mask);
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}

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void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
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	enum pipe pipe = crtc->pipe;
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	u32 val;

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	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
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	assert_planes_disabled(crtc);
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	/*
	 * A pipe without a PLL won't actually be able to drive bits from
	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
	 * need the check.
	 */
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	if (HAS_GMCH(dev_priv)) {
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		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
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			assert_dsi_pll_enabled(dev_priv);
		else
			assert_pll_enabled(dev_priv, pipe);
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	} else {
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		if (new_crtc_state->has_pch_encoder) {
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			/* if driving the PCH, we need FDI enabled */
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			assert_fdi_rx_pll_enabled(dev_priv,
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						  intel_crtc_pch_transcoder(crtc));
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			assert_fdi_tx_pll_enabled(dev_priv,
						  (enum pipe) cpu_transcoder);
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		}
		/* FIXME: assert CPU port conditions for SNB+ */
	}
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	/* Wa_22012358565:adl-p */
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	if (DISPLAY_VER(dev_priv) == 13)
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		intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
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			     0, PIPE_ARB_USE_PROG_SLOTS);

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	if (DISPLAY_VER(dev_priv) >= 14) {
		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
		u32 set = 0;

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		if (DISPLAY_VER(dev_priv) == 14)
			set |= DP_FEC_BS_JITTER_WA;

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		intel_de_rmw(dev_priv,
			     hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
			     clear, set);
	}

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	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
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	if (val & TRANSCONF_ENABLE) {
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		/* we keep both pipes enabled on 830 */
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		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
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		return;
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	}
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	/* Wa_1409098942:adlp+ */
	if (DISPLAY_VER(dev_priv) >= 13 &&
	    new_crtc_state->dsc.compression_enable) {
		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
	}

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	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
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		       val | TRANSCONF_ENABLE);
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	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
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	/*
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	 * Until the pipe starts PIPEDSL reads will return a stale value,
	 * which causes an apparent vblank timestamp jump when PIPEDSL
	 * resets to its proper value. That also messes up the frame count
	 * when it's derived from the timestamps. So let's wait for the
	 * pipe to start properly before we call drm_crtc_vblank_on()
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	 */
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	if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
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		intel_wait_for_pipe_scanline_moving(crtc);
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}

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void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
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{
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	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
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	enum pipe pipe = crtc->pipe;
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	u32 val;

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	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
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	/*
	 * Make sure planes won't keep trying to pump pixels to us,
	 * or we might hang the display.
	 */
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	assert_planes_disabled(crtc);
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	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
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	if ((val & TRANSCONF_ENABLE) == 0)
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		return;

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	/*
	 * Double wide has implications for planes
	 * so best keep it disabled when not needed.
	 */
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	if (old_crtc_state->double_wide)
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		val &= ~TRANSCONF_DOUBLE_WIDE;
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	/* Don't disable pipe or pipe PLLs if needed */
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	if (!IS_I830(dev_priv))
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		val &= ~TRANSCONF_ENABLE;
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	/* Wa_1409098942:adlp+ */
	if (DISPLAY_VER(dev_priv) >= 13 &&
	    old_crtc_state->dsc.compression_enable)
		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;

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	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
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	if (DISPLAY_VER(dev_priv) >= 12)
		intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
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			     FECSTALL_DIS_DPTSTREAM_DPTTG, 0);

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	if ((val & TRANSCONF_ENABLE) == 0)
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		intel_wait_for_pipe_off(old_crtc_state);
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}

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unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
{
	unsigned int size = 0;
	int i;

	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
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		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
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	return size;
}

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unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
{
	unsigned int size = 0;
	int i;

551
	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
552 553
		unsigned int plane_size;

554 555 556 557 558
		if (rem_info->plane[i].linear)
			plane_size = rem_info->plane[i].size;
		else
			plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;

559 560 561
		if (plane_size == 0)
			continue;

562 563
		if (rem_info->plane_alignment)
			size = ALIGN(size, rem_info->plane_alignment);
564 565

		size += plane_size;
566
	}
567 568 569 570

	return size;
}

571
bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
572
{
573
	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
574 575
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

576
	return DISPLAY_VER(dev_priv) < 4 ||
577
		(plane->fbc && !plane_state->no_fbc_reason &&
578
		 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
579 580
}

581 582 583 584 585 586 587
/*
 * Convert the x/y offsets into a linear offset.
 * Only valid with 0/180 degree rotation, which is fine since linear
 * offset is only used with linear buffers on pre-hsw and tiled buffers
 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 */
u32 intel_fb_xy_to_linear(int x, int y,
588
			  const struct intel_plane_state *state,
589
			  int color_plane)
590
{
591
	const struct drm_framebuffer *fb = state->hw.fb;
592
	unsigned int cpp = fb->format->cpp[color_plane];
593
	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
594 595 596 597 598 599 600 601 602 603

	return y * pitch + x * cpp;
}

/*
 * Add the x/y offsets derived from fb->offsets[] to the user
 * specified plane src x/y offsets. The resulting x/y offsets
 * specify the start of scanout from the beginning of the gtt mapping.
 */
void intel_add_fb_offsets(int *x, int *y,
604
			  const struct intel_plane_state *state,
605
			  int color_plane)
606 607

{
608 609
	*x += state->view.color_plane[color_plane].x;
	*y += state->view.color_plane[color_plane].y;
610 611
}

612 613
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
			      u32 pixel_format, u64 modifier)
614 615 616 617
{
	struct intel_crtc *crtc;
	struct intel_plane *plane;

618 619 620
	if (!HAS_DISPLAY(dev_priv))
		return 0;

621 622
	/*
	 * We assume the primary plane for pipe A has
623 624
	 * the highest stride limits of them all,
	 * if in case pipe A is disabled, use the first pipe from pipe_mask.
625
	 */
626
	crtc = intel_first_crtc(dev_priv);
627 628 629
	if (!crtc)
		return 0;

630 631 632 633 634 635
	plane = to_intel_plane(crtc->base.primary);

	return plane->max_stride(plane, pixel_format, modifier,
				 DRM_MODE_ROTATE_0);
}

636 637 638
void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
			     struct intel_plane_state *plane_state,
			     bool visible)
639
{
640
	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
641

642
	plane_state->uapi.visible = visible;
643

644
	if (visible)
645
		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
646
	else
647
		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
648 649
}

650
void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
651
{
652
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
653 654 655 656 657 658 659
	struct drm_plane *plane;

	/*
	 * Active_planes aliases if multiple "primary" or cursor planes
	 * have been used on the same (or wrong) pipe. plane_mask uses
	 * unique ids, hence we can use that to reconstruct active_planes.
	 */
660
	crtc_state->enabled_planes = 0;
661 662 663
	crtc_state->active_planes = 0;

	drm_for_each_plane_mask(plane, &dev_priv->drm,
664 665
				crtc_state->uapi.plane_mask) {
		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
666
		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
667
	}
668 669
}

670 671
void intel_plane_disable_noatomic(struct intel_crtc *crtc,
				  struct intel_plane *plane)
672
{
673
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
674 675 676 677 678
	struct intel_crtc_state *crtc_state =
		to_intel_crtc_state(crtc->base.state);
	struct intel_plane_state *plane_state =
		to_intel_plane_state(plane->base.state);

679 680 681 682
	drm_dbg_kms(&dev_priv->drm,
		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
		    plane->base.base.id, plane->base.name,
		    crtc->base.base.id, crtc->base.name);
683

684
	intel_set_plane_visible(crtc_state, plane_state, false);
685
	intel_plane_fixup_bitmasks(crtc_state);
686
	crtc_state->data_rate[plane->id] = 0;
687
	crtc_state->data_rate_y[plane->id] = 0;
688 689
	crtc_state->rel_data_rate[plane->id] = 0;
	crtc_state->rel_data_rate_y[plane->id] = 0;
690
	crtc_state->min_cdclk[plane->id] = 0;
691

692 693 694
	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
	    hsw_ips_disable(crtc_state)) {
		crtc_state->ips_enabled = false;
695
		intel_crtc_wait_for_next_vblank(crtc);
696
	}
697 698 699 700 701 702 703 704 705 706 707 708

	/*
	 * Vblank time updates from the shadow to live plane control register
	 * are blocked if the memory self-refresh mode is active at that
	 * moment. So to make sure the plane gets truly disabled, disable
	 * first the self-refresh mode. The self-refresh enable bit in turn
	 * will be checked/applied by the HW only at the next frame start
	 * event which is after the vblank start event, so we need to have a
	 * wait-for-vblank between disabling the plane and the pipe.
	 */
	if (HAS_GMCH(dev_priv) &&
	    intel_set_memory_cxsr(dev_priv, false))
709
		intel_crtc_wait_for_next_vblank(crtc);
710 711 712 713 714

	/*
	 * Gen2 reports pipe underruns whenever all planes are disabled.
	 * So disable underrun reporting before all the planes get disabled.
	 */
715
	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
716
		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
717

718
	intel_plane_disable_arm(plane, crtc_state);
719
	intel_crtc_wait_for_next_vblank(crtc);
720
}
721

722 723 724 725 726 727
unsigned int
intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
{
	int x = 0, y = 0;

	intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
728
					  plane_state->view.color_plane[0].offset, 0);
729 730 731 732

	return y;
}

733 734 735
static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
736 737 738 739
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
	u32 tmp;

740
	tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
741 742 743 744 745 746 747

	/*
	 * Display WA #1153: icl
	 * enable hardware to bypass the alpha math
	 * and rounding for per-pixel values 00 and 0xff
	 */
	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
748 749 750 751 752 753 754
	/*
	 * Display WA # 1605353570: icl
	 * Set the pixel rounding bit to 1 for allowing
	 * passthrough of Frame buffer pixels unmodified
	 * across pipe
	 */
	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
755

756 757 758 759 760
	/*
	 * Underrun recovery must always be disabled on display 13+.
	 * DG2 chicken bit meaning is inverted compared to other platforms.
	 */
	if (IS_DG2(dev_priv))
761
		tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
762 763
	else if (DISPLAY_VER(dev_priv) >= 13)
		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
764

765
	/* Wa_14010547955:dg2 */
766
	if (IS_DG2(dev_priv))
767 768
		tmp |= DG2_RENDER_CCSTAG_4_3_EN;

769
	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
770 771
}

772
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
773
{
774 775 776 777 778 779 780 781 782 783 784 785 786
	struct drm_crtc *crtc;
	bool cleanup_done;

	drm_for_each_crtc(crtc, &dev_priv->drm) {
		struct drm_crtc_commit *commit;
		spin_lock(&crtc->commit_lock);
		commit = list_first_entry_or_null(&crtc->commit_list,
						  struct drm_crtc_commit, commit_entry);
		cleanup_done = commit ?
			try_wait_for_completion(&commit->cleanup_done) : true;
		spin_unlock(&crtc->commit_lock);

		if (cleanup_done)
787 788
			continue;

789
		intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
790 791 792 793 794 795 796

		return true;
	}

	return false;
}

797 798 799 800
/*
 * Finds the encoder associated with the given CRTC. This can only be
 * used when we know that the CRTC isn't feeding multiple encoders!
 */
801
struct intel_encoder *
802 803
intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
			   const struct intel_crtc_state *crtc_state)
804 805 806 807
{
	const struct drm_connector_state *connector_state;
	const struct drm_connector *connector;
	struct intel_encoder *encoder = NULL;
808
	struct intel_crtc *primary_crtc;
809 810 811
	int num_encoders = 0;
	int i;

812
	primary_crtc = intel_primary_crtc(crtc_state);
813

814
	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
815
		if (connector_state->crtc != &primary_crtc->base)
816 817 818 819 820 821
			continue;

		encoder = to_intel_encoder(connector_state->best_encoder);
		num_encoders++;
	}

822
	drm_WARN(state->base.dev, num_encoders != 1,
823
		 "%d encoders for pipe %c\n",
824
		 num_encoders, pipe_name(primary_crtc->pipe));
825 826 827 828

	return encoder;
}

829
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
830
{
831
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
832
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
833
	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
834
	enum pipe pipe = crtc->pipe;
835 836 837 838
	int width = drm_rect_width(dst);
	int height = drm_rect_height(dst);
	int x = dst->x1;
	int y = dst->y1;
839

840 841 842 843 844 845 846 847
	if (!crtc_state->pch_pfit.enabled)
		return;

	/* Force use of hard-coded filter coefficients
	 * as some pre-programmed values are broken,
	 * e.g. x201.
	 */
	if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
848 849
		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
				  PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
850
	else
851 852
		intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
				  PF_FILTER_MED_3x3);
853 854 855 856
	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
			  PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
			  PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
857 858
}

859
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
860
{
861 862
	if (crtc->overlay)
		(void) intel_overlay_switch_off(crtc->overlay);
863 864 865 866 867 868

	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
}

869
static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
870
{
871 872
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

873 874 875
	if (!crtc_state->nv12_planes)
		return false;

876
	/* WA Display #0827: Gen9:all */
877
	if (DISPLAY_VER(dev_priv) == 9)
878 879 880 881 882
		return true;

	return false;
}

883
static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
884
{
885 886
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

887
	/* Wa_2006604312:icl,ehl */
888
	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
889 890 891 892 893
		return true;

	return false;
}

894 895 896 897 898 899 900 901 902 903 904 905 906
static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);

	/* Wa_1604331009:icl,jsl,ehl */
	if (is_hdr_mode(crtc_state) &&
	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&
	    DISPLAY_VER(dev_priv) == 11)
		return true;

	return false;
}

907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929
static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
				    enum pipe pipe, bool enable)
{
	if (DISPLAY_VER(i915) == 9) {
		/*
		 * "Plane N strech max must be programmed to 11b (x1)
		 *  when Async flips are enabled on that plane."
		 */
		intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
			     SKL_PLANE1_STRETCH_MAX_MASK,
			     enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
	} else {
		/* Also needed on HSW/BDW albeit undocumented */
		intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
			     HSW_PRI_STRETCH_MAX_MASK,
			     enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
	}
}

static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

930
	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
931 932 933
		(DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
}

934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
static void intel_encoders_audio_enable(struct intel_atomic_state *state,
					struct intel_crtc *crtc)
{
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct drm_connector_state *conn_state;
	struct drm_connector *conn;
	int i;

	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);

		if (conn_state->crtc != &crtc->base)
			continue;

		if (encoder->audio_enable)
			encoder->audio_enable(encoder, crtc_state, conn_state);
	}
}

static void intel_encoders_audio_disable(struct intel_atomic_state *state,
					 struct intel_crtc *crtc)
{
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct drm_connector_state *old_conn_state;
	struct drm_connector *conn;
	int i;

	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
		struct intel_encoder *encoder =
			to_intel_encoder(old_conn_state->best_encoder);

		if (old_conn_state->crtc != &crtc->base)
			continue;

		if (encoder->audio_disable)
			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
	}
}

976 977 978 979 980 981 982
#define is_enabling(feature, old_crtc_state, new_crtc_state) \
	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
	 (new_crtc_state)->feature)
#define is_disabling(feature, old_crtc_state, new_crtc_state) \
	((old_crtc_state)->feature && \
	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))

983 984 985
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
			    const struct intel_crtc_state *new_crtc_state)
{
986 987 988
	if (!new_crtc_state->hw.active)
		return false;

989
	return is_enabling(active_planes, old_crtc_state, new_crtc_state);
990 991 992 993 994
}

static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
			     const struct intel_crtc_state *new_crtc_state)
{
995 996 997
	if (!old_crtc_state->hw.active)
		return false;

998
	return is_disabling(active_planes, old_crtc_state, new_crtc_state);
999 1000
}

1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
			       const struct intel_crtc_state *new_crtc_state)
{
	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}

1011 1012 1013 1014 1015 1016 1017
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
				const struct intel_crtc_state *new_crtc_state)
{
	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
}

1018 1019
static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
1020
{
1021 1022 1023 1024 1025
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);

1026 1027 1028
	if (!new_crtc_state->hw.active)
		return false;

1029
	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1030
		(new_crtc_state->vrr.enable &&
1031
		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1032
		  vrr_params_changed(old_crtc_state, new_crtc_state)));
1033 1034
}

1035 1036
bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
1037
{
1038 1039 1040 1041 1042
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);

1043 1044 1045
	if (!old_crtc_state->hw.active)
		return false;

1046
	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1047
		(old_crtc_state->vrr.enable &&
1048
		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1049
		  vrr_params_changed(old_crtc_state, new_crtc_state)));
1050 1051
}

1052 1053 1054 1055 1056 1057
static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
			   const struct intel_crtc_state *new_crtc_state)
{
	if (!new_crtc_state->hw.active)
		return false;

1058 1059 1060
	return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
		(new_crtc_state->has_audio &&
		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1061 1062 1063 1064 1065 1066 1067 1068
}

static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
			    const struct intel_crtc_state *new_crtc_state)
{
	if (!old_crtc_state->hw.active)
		return false;

1069 1070 1071
	return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
		(old_crtc_state->has_audio &&
		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1072 1073
}

1074 1075 1076
#undef is_disabling
#undef is_enabling

1077 1078
static void intel_post_plane_update(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
1079
{
1080 1081 1082 1083 1084
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
1085
	enum pipe pipe = crtc->pipe;
1086

1087 1088
	intel_psr_post_plane_update(state, crtc);

1089
	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1090

1091
	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1092
		intel_update_watermarks(dev_priv);
1093

1094
	intel_fbc_post_update(state, crtc);
1095

1096 1097 1098 1099
	if (needs_async_flip_vtd_wa(old_crtc_state) &&
	    !needs_async_flip_vtd_wa(new_crtc_state))
		intel_async_flip_vtd_wa(dev_priv, pipe, false);

1100
	if (needs_nv12_wa(old_crtc_state) &&
1101
	    !needs_nv12_wa(new_crtc_state))
1102
		skl_wa_827(dev_priv, pipe, false);
1103

1104
	if (needs_scalerclk_wa(old_crtc_state) &&
1105
	    !needs_scalerclk_wa(new_crtc_state))
1106
		icl_wa_scalerclkgating(dev_priv, pipe, false);
1107 1108 1109 1110

	if (needs_cursorclk_wa(old_crtc_state) &&
	    !needs_cursorclk_wa(new_crtc_state))
		icl_wa_cursorclkgating(dev_priv, pipe, false);
1111 1112 1113

	if (intel_crtc_needs_color_update(new_crtc_state))
		intel_color_post_update(new_crtc_state);
1114 1115 1116

	if (audio_enabling(old_crtc_state, new_crtc_state))
		intel_encoders_audio_enable(state, crtc);
1117 1118
}

1119 1120 1121 1122 1123 1124
static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
					struct intel_crtc *crtc)
{
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	u8 update_planes = crtc_state->update_planes;
1125
	const struct intel_plane_state __maybe_unused *plane_state;
1126 1127 1128 1129
	struct intel_plane *plane;
	int i;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1130 1131
		if (plane->pipe == crtc->pipe &&
		    update_planes & BIT(plane->id))
1132 1133 1134 1135 1136 1137 1138 1139 1140 1141
			plane->enable_flip_done(plane);
	}
}

static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
					 struct intel_crtc *crtc)
{
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	u8 update_planes = crtc_state->update_planes;
1142
	const struct intel_plane_state __maybe_unused *plane_state;
1143 1144 1145 1146
	struct intel_plane *plane;
	int i;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1147 1148
		if (plane->pipe == crtc->pipe &&
		    update_planes & BIT(plane->id))
1149 1150 1151 1152
			plane->disable_flip_done(plane);
	}
}

1153 1154
static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
					     struct intel_crtc *crtc)
1155
{
1156 1157 1158 1159
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
1160 1161
	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
				       ~new_crtc_state->async_flip_planes;
1162
	const struct intel_plane_state *old_plane_state;
1163
	struct intel_plane *plane;
1164
	bool need_vbl_wait = false;
1165 1166
	int i;

1167
	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1168
		if (plane->need_async_flip_toggle_wa &&
1169
		    plane->pipe == crtc->pipe &&
1170
		    disable_async_flip_planes & BIT(plane->id)) {
1171 1172 1173 1174
			/*
			 * Apart from the async flip bit we want to
			 * preserve the old state for the plane.
			 */
1175 1176
			intel_plane_async_flip(plane, old_crtc_state,
					       old_plane_state, false);
1177 1178
			need_vbl_wait = true;
		}
1179 1180
	}

1181
	if (need_vbl_wait)
1182
		intel_crtc_wait_for_next_vblank(crtc);
1183 1184
}

1185 1186
static void intel_pre_plane_update(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
1187
{
1188 1189 1190 1191 1192
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
1193
	enum pipe pipe = crtc->pipe;
1194

1195
	if (intel_crtc_vrr_disabling(state, crtc)) {
1196 1197 1198 1199
		intel_vrr_disable(old_crtc_state);
		intel_crtc_update_active_timings(old_crtc_state, false);
	}

1200 1201 1202
	if (audio_disabling(old_crtc_state, new_crtc_state))
		intel_encoders_audio_disable(state, crtc);

1203
	intel_drrs_deactivate(old_crtc_state);
1204

1205 1206
	intel_psr_pre_plane_update(state, crtc);

1207
	if (hsw_ips_pre_update(state, crtc))
1208
		intel_crtc_wait_for_next_vblank(crtc);
1209

1210
	if (intel_fbc_pre_update(state, crtc))
1211
		intel_crtc_wait_for_next_vblank(crtc);
1212

1213 1214 1215 1216
	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
	    needs_async_flip_vtd_wa(new_crtc_state))
		intel_async_flip_vtd_wa(dev_priv, pipe, true);

1217
	/* Display WA 827 */
1218
	if (!needs_nv12_wa(old_crtc_state) &&
1219
	    needs_nv12_wa(new_crtc_state))
1220
		skl_wa_827(dev_priv, pipe, true);
1221

1222
	/* Wa_2006604312:icl,ehl */
1223
	if (!needs_scalerclk_wa(old_crtc_state) &&
1224
	    needs_scalerclk_wa(new_crtc_state))
1225
		icl_wa_scalerclkgating(dev_priv, pipe, true);
1226

1227 1228 1229 1230 1231
	/* Wa_1604331009:icl,jsl,ehl */
	if (!needs_cursorclk_wa(old_crtc_state) &&
	    needs_cursorclk_wa(new_crtc_state))
		icl_wa_cursorclkgating(dev_priv, pipe, true);

1232 1233 1234 1235 1236 1237 1238 1239 1240
	/*
	 * Vblank time updates from the shadow to live plane control register
	 * are blocked if the memory self-refresh mode is active at that
	 * moment. So to make sure the plane gets truly disabled, disable
	 * first the self-refresh mode. The self-refresh enable bit in turn
	 * will be checked/applied by the HW only at the next frame start
	 * event which is after the vblank start event, so we need to have a
	 * wait-for-vblank between disabling the plane and the pipe.
	 */
1241
	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1242
	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1243
		intel_crtc_wait_for_next_vblank(crtc);
1244

1245 1246 1247 1248 1249 1250 1251
	/*
	 * IVB workaround: must disable low power watermarks for at least
	 * one frame before enabling scaling.  LP watermarks can be re-enabled
	 * when scaling is disabled.
	 *
	 * WaCxSRDisabledForSpriteScaling:ivb
	 */
1252 1253
	if (old_crtc_state->hw.active &&
	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1254
		intel_crtc_wait_for_next_vblank(crtc);
1255 1256

	/*
1257 1258
	 * If we're doing a modeset we don't need to do any
	 * pre-vblank watermark programming here.
1259
	 */
1260
	if (!intel_crtc_needs_modeset(new_crtc_state)) {
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274
		/*
		 * For platforms that support atomic watermarks, program the
		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
		 * will be the intermediate values that are safe for both pre- and
		 * post- vblank; when vblank happens, the 'active' values will be set
		 * to the final 'target' values and we'll do this again to get the
		 * optimal watermarks.  For gen9+ platforms, the values we program here
		 * will be the final target values which will get automatically latched
		 * at vblank time; no further programming will be necessary.
		 *
		 * If a platform hasn't been transitioned to atomic watermarks yet,
		 * we'll continue to update watermarks the old way, if flags tell
		 * us to.
		 */
1275 1276 1277
		if (!intel_initial_watermarks(state, crtc))
			if (new_crtc_state->update_wm_pre)
				intel_update_watermarks(dev_priv);
1278
	}
1279 1280

	/*
1281 1282
	 * Gen2 reports pipe underruns whenever all planes are disabled.
	 * So disable underrun reporting before all the planes get disabled.
1283
	 *
1284 1285 1286
	 * We do this after .initial_watermarks() so that we have a
	 * chance of catching underruns with the intermediate watermarks
	 * vs. the old plane configuration.
1287
	 */
1288
	if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1289
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1290 1291 1292 1293 1294

	/*
	 * WA for platforms where async address update enable bit
	 * is double buffered and only latched at start of vblank.
	 */
1295
	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1296
		intel_crtc_async_flip_disable_wa(state, crtc);
1297 1298
}

1299 1300
static void intel_crtc_disable_planes(struct intel_atomic_state *state,
				      struct intel_crtc *crtc)
1301
{
1302 1303 1304 1305 1306
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	unsigned int update_mask = new_crtc_state->update_planes;
	const struct intel_plane_state *old_plane_state;
1307 1308
	struct intel_plane *plane;
	unsigned fb_bits = 0;
1309
	int i;
1310

1311
	intel_crtc_dpms_overlay_disable(crtc);
1312

1313 1314 1315 1316 1317
	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
		if (crtc->pipe != plane->pipe ||
		    !(update_mask & BIT(plane->id)))
			continue;

1318
		intel_plane_disable_arm(plane, new_crtc_state);
1319

1320
		if (old_plane_state->uapi.visible)
1321 1322 1323
			fb_bits |= plane->frontbuffer_bit;
	}

1324
	intel_frontbuffer_flip(dev_priv, fb_bits);
1325 1326
}

1327 1328
static void intel_encoders_update_prepare(struct intel_atomic_state *state)
{
1329 1330 1331
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
	struct intel_crtc *crtc;
1332 1333
	int i;

1334 1335 1336 1337
	/*
	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
	 */
1338
	if (i915->display.dpll.mgr) {
1339 1340 1341 1342 1343 1344 1345 1346
		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
			if (intel_crtc_needs_modeset(new_crtc_state))
				continue;

			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
		}
	}
1347 1348
}

1349 1350
static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
					  struct intel_crtc *crtc)
1351
{
1352 1353 1354
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct drm_connector_state *conn_state;
1355 1356 1357
	struct drm_connector *conn;
	int i;

1358
	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1359 1360 1361
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);

1362
		if (conn_state->crtc != &crtc->base)
1363 1364 1365
			continue;

		if (encoder->pre_pll_enable)
1366 1367
			encoder->pre_pll_enable(state, encoder,
						crtc_state, conn_state);
1368 1369 1370
	}
}

1371 1372
static void intel_encoders_pre_enable(struct intel_atomic_state *state,
				      struct intel_crtc *crtc)
1373
{
1374 1375 1376
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct drm_connector_state *conn_state;
1377 1378 1379
	struct drm_connector *conn;
	int i;

1380
	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1381 1382 1383
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);

1384
		if (conn_state->crtc != &crtc->base)
1385 1386 1387
			continue;

		if (encoder->pre_enable)
1388 1389
			encoder->pre_enable(state, encoder,
					    crtc_state, conn_state);
1390 1391 1392
	}
}

1393 1394
static void intel_encoders_enable(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
1395
{
1396 1397 1398
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct drm_connector_state *conn_state;
1399 1400 1401
	struct drm_connector *conn;
	int i;

1402
	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1403 1404 1405
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);

1406
		if (conn_state->crtc != &crtc->base)
1407 1408
			continue;

1409
		if (encoder->enable)
1410 1411
			encoder->enable(state, encoder,
					crtc_state, conn_state);
1412 1413 1414 1415
		intel_opregion_notify_encoder(encoder, true);
	}
}

1416 1417
static void intel_encoders_disable(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
1418
{
1419 1420 1421
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct drm_connector_state *old_conn_state;
1422 1423 1424
	struct drm_connector *conn;
	int i;

1425
	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1426 1427 1428
		struct intel_encoder *encoder =
			to_intel_encoder(old_conn_state->best_encoder);

1429
		if (old_conn_state->crtc != &crtc->base)
1430 1431 1432
			continue;

		intel_opregion_notify_encoder(encoder, false);
1433
		if (encoder->disable)
1434 1435
			encoder->disable(state, encoder,
					 old_crtc_state, old_conn_state);
1436 1437 1438
	}
}

1439 1440
static void intel_encoders_post_disable(struct intel_atomic_state *state,
					struct intel_crtc *crtc)
1441
{
1442 1443 1444
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct drm_connector_state *old_conn_state;
1445 1446 1447
	struct drm_connector *conn;
	int i;

1448
	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1449 1450 1451
		struct intel_encoder *encoder =
			to_intel_encoder(old_conn_state->best_encoder);

1452
		if (old_conn_state->crtc != &crtc->base)
1453 1454 1455
			continue;

		if (encoder->post_disable)
1456 1457
			encoder->post_disable(state, encoder,
					      old_crtc_state, old_conn_state);
1458 1459 1460
	}
}

1461 1462
static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
					    struct intel_crtc *crtc)
1463
{
1464 1465 1466
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct drm_connector_state *old_conn_state;
1467 1468 1469
	struct drm_connector *conn;
	int i;

1470
	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1471 1472 1473
		struct intel_encoder *encoder =
			to_intel_encoder(old_conn_state->best_encoder);

1474
		if (old_conn_state->crtc != &crtc->base)
1475 1476 1477
			continue;

		if (encoder->post_pll_disable)
1478 1479
			encoder->post_pll_disable(state, encoder,
						  old_crtc_state, old_conn_state);
1480 1481 1482
	}
}

1483 1484
static void intel_encoders_update_pipe(struct intel_atomic_state *state,
				       struct intel_crtc *crtc)
1485
{
1486 1487 1488
	const struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct drm_connector_state *conn_state;
1489 1490 1491
	struct drm_connector *conn;
	int i;

1492
	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1493 1494 1495
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);

1496
		if (conn_state->crtc != &crtc->base)
1497 1498 1499
			continue;

		if (encoder->update_pipe)
1500 1501
			encoder->update_pipe(state, encoder,
					     crtc_state, conn_state);
1502 1503 1504
	}
}

1505 1506
static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
{
1507
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1508 1509
	struct intel_plane *plane = to_intel_plane(crtc->base.primary);

1510
	plane->disable_arm(plane, crtc_state);
1511 1512
}

1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532
static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	if (crtc_state->has_pch_encoder) {
		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
					       &crtc_state->fdi_m_n);
	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
					       &crtc_state->dp_m_n);
		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
					       &crtc_state->dp_m2_n2);
	}

	intel_set_transcoder_timings(crtc_state);

	ilk_set_pipeconf(crtc_state);
}

1533 1534
static void ilk_crtc_enable(struct intel_atomic_state *state,
			    struct intel_crtc *crtc)
1535
{
1536 1537
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
1538 1539
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
1540

1541
	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1542 1543
		return;

1544 1545 1546 1547 1548 1549 1550 1551 1552 1553
	/*
	 * Sometimes spurious CPU pipe underruns happen during FDI
	 * training, at least with VGA+HDMI cloning. Suppress them.
	 *
	 * On ILK we get an occasional spurious CPU pipe underruns
	 * between eDP port A enable and vdd enable. Also PCH port
	 * enable seems to result in the occasional CPU pipe underrun.
	 *
	 * Spurious PCH underruns also occur during PCH enabling.
	 */
1554 1555
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1556

1557
	ilk_configure_cpu_transcoder(new_crtc_state);
1558

1559
	intel_set_pipe_src_size(new_crtc_state);
1560

1561
	crtc->active = true;
1562

1563
	intel_encoders_pre_enable(state, crtc);
1564

1565
	if (new_crtc_state->has_pch_encoder) {
1566
		ilk_pch_pre_enable(state, crtc);
1567 1568 1569 1570
	} else {
		assert_fdi_tx_disabled(dev_priv, pipe);
		assert_fdi_rx_disabled(dev_priv, pipe);
	}
1571

1572
	ilk_pfit_enable(new_crtc_state);
1573

1574 1575 1576 1577
	/*
	 * On ILK+ LUT must be loaded before the pipe is running but with
	 * clocks enabled
	 */
1578
	intel_color_load_luts(new_crtc_state);
1579 1580
	intel_color_commit_noarm(new_crtc_state);
	intel_color_commit_arm(new_crtc_state);
1581
	/* update DSPCNTR to configure gamma for pipe bottom color */
1582
	intel_disable_primary_plane(new_crtc_state);
1583

1584
	intel_initial_watermarks(state, crtc);
1585
	intel_enable_transcoder(new_crtc_state);
1586

1587
	if (new_crtc_state->has_pch_encoder)
1588
		ilk_pch_enable(state, crtc);
1589

1590
	intel_crtc_vblank_on(new_crtc_state);
1591

1592
	intel_encoders_enable(state, crtc);
1593

1594
	if (HAS_PCH_CPT(dev_priv))
1595
		intel_wait_for_pipe_scanline_moving(crtc);
1596

1597 1598 1599 1600 1601 1602
	/*
	 * Must wait for vblank to avoid spurious PCH FIFO underruns.
	 * And a second vblank wait is needed at least on ILK with
	 * some interlaced HDMI modes. Let's do the double wait always
	 * in case there are more corner cases we don't know about.
	 */
1603
	if (new_crtc_state->has_pch_encoder) {
1604 1605
		intel_crtc_wait_for_next_vblank(crtc);
		intel_crtc_wait_for_next_vblank(crtc);
1606
	}
1607
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1608
	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1609 1610
}

1611 1612 1613 1614 1615 1616 1617 1618
/* Display WA #1180: WaDisableScalarClockGating: glk */
static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled;
}

1619
static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1620
{
1621
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1622 1623
	u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;

1624 1625
	intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),
		     mask, enable ? mask : 0);
1626 1627
}

1628 1629 1630 1631 1632 1633 1634 1635 1636 1637
static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
		       HSW_LINETIME(crtc_state->linetime) |
		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
}

1638 1639 1640
static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1641
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1642

1643
	intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),
1644 1645
		     HSW_FRAME_START_DELAY_MASK,
		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1646 1647
}

1648 1649 1650 1651 1652 1653
static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
	if (crtc_state->has_pch_encoder) {
		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
					       &crtc_state->fdi_m_n);
	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
					       &crtc_state->dp_m_n);
		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
					       &crtc_state->dp_m2_n2);
	}

1664
	intel_set_transcoder_timings(crtc_state);
1665 1666
	if (HAS_VRR(dev_priv))
		intel_vrr_set_transcoder_timings(crtc_state);
1667 1668

	if (cpu_transcoder != TRANSCODER_EDP)
1669
		intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
1670 1671 1672 1673 1674 1675 1676
			       crtc_state->pixel_multiplier - 1);

	hsw_set_frame_start_delay(crtc_state);

	hsw_set_transconf(crtc_state);
}

1677 1678
static void hsw_crtc_enable(struct intel_atomic_state *state,
			    struct intel_crtc *crtc)
1679
{
1680 1681
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
1682
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1683
	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1684
	struct intel_crtc *pipe_crtc;
1685

1686
	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1687 1688
		return;

1689 1690 1691
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state))
		intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
1692

1693
	intel_encoders_pre_pll_enable(state, crtc);
1694

1695 1696 1697 1698
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
		const struct intel_crtc_state *pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1699

1700 1701
		if (pipe_crtc_state->shared_dpll)
			intel_enable_shared_dpll(pipe_crtc_state);
1702
	}
1703

1704
	intel_encoders_pre_enable(state, crtc);
1705

1706 1707 1708 1709
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
		const struct intel_crtc_state *pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1710

1711
		intel_dsc_enable(pipe_crtc_state);
1712

1713 1714 1715 1716 1717 1718 1719 1720 1721 1722
		if (DISPLAY_VER(dev_priv) >= 13)
			intel_uncompressed_joiner_enable(pipe_crtc_state);

		intel_set_pipe_src_size(pipe_crtc_state);

		if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
			bdw_set_pipe_misc(pipe_crtc_state);
	}

	if (!transcoder_is_dsi(cpu_transcoder))
1723
		hsw_configure_cpu_transcoder(new_crtc_state);
1724

1725 1726 1727 1728
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
		const struct intel_crtc_state *pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1729

1730
		pipe_crtc->active = true;
1731

1732 1733
		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
			glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
1734

1735 1736 1737 1738
		if (DISPLAY_VER(dev_priv) >= 9)
			skl_pfit_enable(pipe_crtc_state);
		else
			ilk_pfit_enable(pipe_crtc_state);
1739

1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
		/*
		 * On ILK+ LUT must be loaded before the pipe is running but with
		 * clocks enabled
		 */
		intel_color_load_luts(pipe_crtc_state);
		intel_color_commit_noarm(pipe_crtc_state);
		intel_color_commit_arm(pipe_crtc_state);
		/* update DSPCNTR to configure gamma/csc for pipe bottom color */
		if (DISPLAY_VER(dev_priv) < 9)
			intel_disable_primary_plane(pipe_crtc_state);
1750

1751
		hsw_set_linetime_wm(pipe_crtc_state);
1752

1753 1754
		if (DISPLAY_VER(dev_priv) >= 11)
			icl_set_pipe_chicken(pipe_crtc_state);
1755

1756 1757
		intel_initial_watermarks(state, pipe_crtc);
	}
1758

1759
	intel_encoders_enable(state, crtc);
1760

1761 1762 1763 1764 1765
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
		const struct intel_crtc_state *pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);
		enum pipe hsw_workaround_pipe;
1766

1767 1768 1769 1770
		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) {
			intel_crtc_wait_for_next_vblank(pipe_crtc);
			glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
		}
1771

1772 1773 1774 1775 1776 1777 1778 1779
		/*
		 * If we change the relative order between pipe/planes
		 * enabling, we need to change the workaround.
		 */
		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
		if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
			struct intel_crtc *wa_crtc =
				intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1780

1781 1782 1783
			intel_crtc_wait_for_next_vblank(wa_crtc);
			intel_crtc_wait_for_next_vblank(wa_crtc);
		}
1784
	}
1785 1786
}

1787
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1788
{
1789
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1790 1791
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
1792 1793 1794

	/* To avoid upsetting the power well on haswell only disable the pfit if
	 * it's in use. The hw state code will make sure we get this right. */
1795 1796 1797
	if (!old_crtc_state->pch_pfit.enabled)
		return;

1798 1799 1800
	intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
	intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
	intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1801 1802
}

1803 1804
static void ilk_crtc_disable(struct intel_atomic_state *state,
			     struct intel_crtc *crtc)
1805
{
1806 1807
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
1808 1809
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
1810

1811 1812 1813 1814 1815
	/*
	 * Sometimes spurious CPU pipe underruns happen when the
	 * pipe is already disabled, but FDI RX/TX is still enabled.
	 * Happens at least with VGA+HDMI cloning. Suppress them.
	 */
1816 1817
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1818

1819
	intel_encoders_disable(state, crtc);
1820

1821
	intel_crtc_vblank_off(old_crtc_state);
1822

1823
	intel_disable_transcoder(old_crtc_state);
1824

1825
	ilk_pfit_disable(old_crtc_state);
1826

1827
	if (old_crtc_state->has_pch_encoder)
1828
		ilk_pch_disable(state, crtc);
1829

1830
	intel_encoders_post_disable(state, crtc);
1831

1832 1833
	if (old_crtc_state->has_pch_encoder)
		ilk_pch_post_disable(state, crtc);
1834

1835
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1836
	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1837 1838

	intel_disable_shared_dpll(old_crtc_state);
1839
}
1840

1841 1842
static void hsw_crtc_disable(struct intel_atomic_state *state,
			     struct intel_crtc *crtc)
1843
{
1844 1845
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
1846
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1847
	struct intel_crtc *pipe_crtc;
1848

1849 1850 1851 1852
	/*
	 * FIXME collapse everything to one hook.
	 * Need care with mst->ddi interactions.
	 */
1853 1854
	intel_encoders_disable(state, crtc);
	intel_encoders_post_disable(state, crtc);
1855

1856 1857 1858 1859
	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
		const struct intel_crtc_state *old_pipe_crtc_state =
			intel_atomic_get_old_crtc_state(state, pipe_crtc);
1860

1861 1862
		intel_disable_shared_dpll(old_pipe_crtc_state);
	}
1863

1864
	intel_encoders_post_pll_disable(state, crtc);
1865

1866 1867 1868
	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
					 intel_crtc_joined_pipe_mask(old_crtc_state))
		intel_dmc_disable_pipe(i915, pipe_crtc->pipe);
1869 1870
}

1871
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1872
{
1873
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1874
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1875

1876
	if (!crtc_state->gmch_pfit.control)
1877 1878 1879
		return;

	/*
1880 1881
	 * The panel fitter should only be adjusted whilst the pipe is disabled,
	 * according to register description and PRM.
1882
	 */
1883
	drm_WARN_ON(&dev_priv->drm,
1884
		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
1885
	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1886

1887
	intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
1888
		       crtc_state->gmch_pfit.pgm_ratios);
1889 1890
	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
		       crtc_state->gmch_pfit.control);
1891 1892 1893

	/* Border color in case we don't scale up to the full screen. Black by
	 * default, change to something else for debugging. */
1894
	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
1895 1896
}

1897
/* Prefer intel_encoder_is_combo() */
1898 1899 1900 1901
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
	if (phy == PHY_NONE)
		return false;
1902 1903
	else if (IS_ALDERLAKE_S(dev_priv))
		return phy <= PHY_E;
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1904
	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1905
		return phy <= PHY_D;
1906
	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1907
		return phy <= PHY_C;
1908
	else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1909
		return phy <= PHY_B;
1910
	else
1911 1912 1913 1914 1915
		/*
		 * DG2 outputs labelled as "combo PHY" in the bspec use
		 * SNPS PHYs with completely different programming,
		 * hence we always return false here.
		 */
1916
		return false;
1917 1918
}

1919
/* Prefer intel_encoder_is_tc() */
1920 1921
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
1922
	/*
1923 1924
	 * Discrete GPU phy's are not attached to FIA's to support TC
	 * subsystem Legacy or non-legacy, and only support native DP/HDMI
1925
	 */
1926
	if (IS_DGFX(dev_priv))
1927
		return false;
1928 1929

	if (DISPLAY_VER(dev_priv) >= 13)
1930 1931
		return phy >= PHY_F && phy <= PHY_I;
	else if (IS_TIGERLAKE(dev_priv))
1932
		return phy >= PHY_D && phy <= PHY_I;
1933
	else if (IS_ICELAKE(dev_priv))
1934
		return phy >= PHY_C && phy <= PHY_F;
1935 1936

	return false;
1937 1938
}

1939
/* Prefer intel_encoder_is_snps() */
1940 1941
bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
{
1942 1943 1944 1945 1946
	/*
	 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
	 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
	 */
	return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
1947 1948
}

1949
/* Prefer intel_encoder_to_phy() */
1950 1951
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
1952 1953 1954 1955 1956
	if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
		return PHY_D + port - PORT_D_XELPD;
	else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
		return PHY_F + port - PORT_TC1;
	else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1957 1958
		return PHY_B + port - PORT_TC1;
	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1959
		return PHY_C + port - PORT_TC1;
1960 1961
	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
		 port == PORT_D)
1962 1963
		return PHY_A;

1964
	return PHY_A + port - PORT_A;
1965 1966
}

1967
/* Prefer intel_encoder_to_tc() */
1968 1969
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
{
1970
	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1971
		return TC_PORT_NONE;
1972

1973
	if (DISPLAY_VER(dev_priv) >= 12)
1974 1975 1976
		return TC_PORT_1 + port - PORT_TC1;
	else
		return TC_PORT_1 + port - PORT_C;
1977 1978
}

1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013
enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
{
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	return intel_port_to_phy(i915, encoder->port);
}

bool intel_encoder_is_combo(struct intel_encoder *encoder)
{
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
}

bool intel_encoder_is_snps(struct intel_encoder *encoder)
{
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder));
}

bool intel_encoder_is_tc(struct intel_encoder *encoder)
{
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder));
}

enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
{
	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	return intel_port_to_tc(i915, encoder->port);
}

2014 2015 2016
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
2017
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2018

2019 2020
	if (intel_tc_port_in_tbt_alt_mode(dig_port))
		return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2021

2022
	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2023 2024
}

2025 2026
static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
				   struct intel_power_domain_mask *mask)
2027
{
2028
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2029
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2030
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2031
	struct drm_encoder *encoder;
2032
	enum pipe pipe = crtc->pipe;
2033 2034

	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2035

2036
	if (!crtc_state->hw.active)
2037
		return;
2038

2039 2040
	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2041 2042
	if (crtc_state->pch_pfit.enabled ||
	    crtc_state->pch_pfit.force_thru)
2043
		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2044

2045
	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2046
				  crtc_state->uapi.encoder_mask) {
2047 2048
		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

2049
		set_bit(intel_encoder->power_domain, mask->bits);
2050
	}
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2051

2052
	if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2053
		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2054

2055
	if (crtc_state->shared_dpll)
2056
		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2057

2058
	if (crtc_state->dsc.compression_enable)
2059
		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2060 2061
}

2062 2063
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
					  struct intel_power_domain_mask *old_domains)
2064
{
2065
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2066
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2067
	enum intel_display_power_domain domain;
2068
	struct intel_power_domain_mask domains, new_domains;
2069

2070
	get_crtc_power_domains(crtc_state, &domains);
2071

2072 2073 2074 2075 2076 2077 2078 2079
	bitmap_andnot(new_domains.bits,
		      domains.bits,
		      crtc->enabled_power_domains.mask.bits,
		      POWER_DOMAIN_NUM);
	bitmap_andnot(old_domains->bits,
		      crtc->enabled_power_domains.mask.bits,
		      domains.bits,
		      POWER_DOMAIN_NUM);
2080

2081
	for_each_power_domain(domain, &new_domains)
2082 2083 2084
		intel_display_power_get_in_set(dev_priv,
					       &crtc->enabled_power_domains,
					       domain);
2085 2086
}

2087 2088
void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
					  struct intel_power_domain_mask *domains)
2089
{
2090 2091 2092
	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
					    &crtc->enabled_power_domains,
					    domains);
2093
}
2094

2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	if (intel_crtc_has_dp_encoder(crtc_state)) {
		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
					       &crtc_state->dp_m_n);
		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
					       &crtc_state->dp_m2_n2);
	}

	intel_set_transcoder_timings(crtc_state);

	i9xx_set_pipeconf(crtc_state);
}

2112 2113
static void valleyview_crtc_enable(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
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2114
{
2115 2116
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
2117 2118
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
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2119

2120
	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2121
		return;
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Mika Kahola committed
2122

2123
	i9xx_configure_cpu_transcoder(new_crtc_state);
2124

2125
	intel_set_pipe_src_size(new_crtc_state);
2126

2127 2128
	intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);

2129
	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2130 2131
		intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
			       CHV_BLEND_LEGACY);
2132
		intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0);
2133 2134
	}

2135
	crtc->active = true;
2136

2137
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2138

2139
	intel_encoders_pre_pll_enable(state, crtc);
2140

2141
	if (IS_CHERRYVIEW(dev_priv))
2142
		chv_enable_pll(new_crtc_state);
2143
	else
2144
		vlv_enable_pll(new_crtc_state);
2145

2146
	intel_encoders_pre_enable(state, crtc);
2147

2148
	i9xx_pfit_enable(new_crtc_state);
2149

2150
	intel_color_load_luts(new_crtc_state);
2151 2152
	intel_color_commit_noarm(new_crtc_state);
	intel_color_commit_arm(new_crtc_state);
2153
	/* update DSPCNTR to configure gamma for pipe bottom color */
2154
	intel_disable_primary_plane(new_crtc_state);
2155

2156
	intel_initial_watermarks(state, crtc);
2157
	intel_enable_transcoder(new_crtc_state);
2158

2159
	intel_crtc_vblank_on(new_crtc_state);
2160

2161
	intel_encoders_enable(state, crtc);
2162 2163
}

2164 2165
static void i9xx_crtc_enable(struct intel_atomic_state *state,
			     struct intel_crtc *crtc)
2166
{
2167 2168
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
2169 2170
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
2171

2172
	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2173
		return;
2174

2175
	i9xx_configure_cpu_transcoder(new_crtc_state);
2176

2177
	intel_set_pipe_src_size(new_crtc_state);
2178

2179
	crtc->active = true;
2180

2181
	if (DISPLAY_VER(dev_priv) != 2)
2182
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2183

2184
	intel_encoders_pre_enable(state, crtc);
2185

2186
	i9xx_enable_pll(new_crtc_state);
2187

2188
	i9xx_pfit_enable(new_crtc_state);
2189

2190
	intel_color_load_luts(new_crtc_state);
2191 2192
	intel_color_commit_noarm(new_crtc_state);
	intel_color_commit_arm(new_crtc_state);
2193
	/* update DSPCNTR to configure gamma for pipe bottom color */
2194
	intel_disable_primary_plane(new_crtc_state);
2195

2196
	if (!intel_initial_watermarks(state, crtc))
2197
		intel_update_watermarks(dev_priv);
2198
	intel_enable_transcoder(new_crtc_state);
2199

2200
	intel_crtc_vblank_on(new_crtc_state);
2201

2202
	intel_encoders_enable(state, crtc);
2203 2204

	/* prevents spurious underruns */
2205
	if (DISPLAY_VER(dev_priv) == 2)
2206
		intel_crtc_wait_for_next_vblank(crtc);
2207
}
2208

2209
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2210
{
2211
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2212
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2213

2214
	if (!old_crtc_state->gmch_pfit.control)
2215 2216
		return;

2217
	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2218

2219
	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2220 2221
		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
2222 2223
}

2224 2225
static void i9xx_crtc_disable(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
2226
{
2227 2228
	struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
2229 2230
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
2231 2232

	/*
2233 2234
	 * On gen2 planes are double buffered but the pipe isn't, so we must
	 * wait for planes to fully turn off before disabling the pipe.
2235
	 */
2236
	if (DISPLAY_VER(dev_priv) == 2)
2237
		intel_crtc_wait_for_next_vblank(crtc);
2238

2239
	intel_encoders_disable(state, crtc);
2240

2241
	intel_crtc_vblank_off(old_crtc_state);
2242

2243
	intel_disable_transcoder(old_crtc_state);
2244

2245
	i9xx_pfit_disable(old_crtc_state);
2246

2247
	intel_encoders_post_disable(state, crtc);
2248

2249
	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2250 2251 2252 2253 2254
		if (IS_CHERRYVIEW(dev_priv))
			chv_disable_pll(dev_priv, pipe);
		else if (IS_VALLEYVIEW(dev_priv))
			vlv_disable_pll(dev_priv, pipe);
		else
2255
			i9xx_disable_pll(old_crtc_state);
2256
	}
2257

2258
	intel_encoders_post_pll_disable(state, crtc);
2259

2260
	if (DISPLAY_VER(dev_priv) != 2)
2261
		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2262

2263
	if (!dev_priv->display.funcs.wm->initial_watermarks)
2264
		intel_update_watermarks(dev_priv);
2265 2266 2267 2268

	/* clock the pipe down to 640x480@60 to potentially save power */
	if (IS_I830(dev_priv))
		i830_enable_pipe(dev_priv, pipe);
2269 2270
}

2271
void intel_encoder_destroy(struct drm_encoder *encoder)
2272
{
2273
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2274 2275 2276

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
2277 2278
}

2279
static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2280
{
2281
	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2282

2283
	/* GDG double wide on either pipe, otherwise pipe A only */
2284
	return DISPLAY_VER(dev_priv) < 4 &&
2285
		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2286 2287
}

2288
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2289
{
2290
	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2291
	struct drm_rect src;
2292 2293 2294 2295 2296 2297

	/*
	 * We only use IF-ID interlacing. If we ever use
	 * PF-ID we'll need to adjust the pixel_rate here.
	 */

2298 2299
	if (!crtc_state->pch_pfit.enabled)
		return pixel_rate;
2300

2301
	drm_rect_init(&src, 0, 0,
2302 2303
		      drm_rect_width(&crtc_state->pipe_src) << 16,
		      drm_rect_height(&crtc_state->pipe_src) << 16);
2304

2305 2306
	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
				   pixel_rate);
2307 2308
}

2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329
static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
					 const struct drm_display_mode *timings)
{
	mode->hdisplay = timings->crtc_hdisplay;
	mode->htotal = timings->crtc_htotal;
	mode->hsync_start = timings->crtc_hsync_start;
	mode->hsync_end = timings->crtc_hsync_end;

	mode->vdisplay = timings->crtc_vdisplay;
	mode->vtotal = timings->crtc_vtotal;
	mode->vsync_start = timings->crtc_vsync_start;
	mode->vsync_end = timings->crtc_vsync_end;

	mode->flags = timings->flags;
	mode->type = DRM_MODE_TYPE_DRIVER;

	mode->clock = timings->crtc_clock;

	drm_mode_set_name(mode);
}

2330
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2331
{
2332
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2333

Rodrigo Vivi's avatar
Rodrigo Vivi committed
2334
	if (HAS_GMCH(dev_priv))
2335 2336
		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
		crtc_state->pixel_rate =
2337
			crtc_state->hw.pipe_mode.crtc_clock;
2338 2339 2340 2341
	else
		crtc_state->pixel_rate =
			ilk_pipe_pixel_rate(crtc_state);
}
2342

2343 2344
static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
					struct drm_display_mode *mode)
2345
{
2346
	int num_pipes = intel_joiner_num_pipes(crtc_state);
2347 2348

	if (num_pipes < 2)
2349 2350
		return;

2351 2352 2353 2354 2355 2356 2357
	mode->crtc_clock /= num_pipes;
	mode->crtc_hdisplay /= num_pipes;
	mode->crtc_hblank_start /= num_pipes;
	mode->crtc_hblank_end /= num_pipes;
	mode->crtc_hsync_start /= num_pipes;
	mode->crtc_hsync_end /= num_pipes;
	mode->crtc_htotal /= num_pipes;
2358 2359
}

2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
					  struct drm_display_mode *mode)
{
	int overlap = crtc_state->splitter.pixel_overlap;
	int n = crtc_state->splitter.link_count;

	if (!crtc_state->splitter.enable)
		return;

	/*
	 * eDP MSO uses segment timings from EDID for transcoder
	 * timings, but full mode for everything else.
	 *
	 * h_full = (h_segment - pixel_overlap) * link_count
	 */
	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
	mode->crtc_clock *= n;
}

2384 2385 2386
static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
{
	struct drm_display_mode *mode = &crtc_state->hw.mode;
2387
	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2388 2389
	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

2390 2391 2392 2393
	/*
	 * Start with the adjusted_mode crtc timings, which
	 * have been filled with the transcoder timings.
	 */
2394 2395
	drm_mode_copy(pipe_mode, adjusted_mode);

2396 2397
	/* Expand MSO per-segment transcoder timings to full */
	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2398

2399 2400 2401 2402 2403 2404
	/*
	 * We want the full numbers in adjusted_mode normal timings,
	 * adjusted_mode crtc timings are left with the raw transcoder
	 * timings.
	 */
	intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2405

2406 2407 2408
	/* Populate the "user" mode with full numbers */
	drm_mode_copy(mode, pipe_mode);
	intel_mode_from_crtc_timings(mode, mode);
2409
	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2410
		(intel_joiner_num_pipes(crtc_state) ?: 1);
2411
	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2412

2413 2414
	/* Derive per-pipe timings in case joiner is used */
	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2415 2416 2417
	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);

	intel_crtc_compute_pixel_rate(crtc_state);
2418 2419
}

2420 2421
void intel_encoder_get_config(struct intel_encoder *encoder,
			      struct intel_crtc_state *crtc_state)
2422 2423
{
	encoder->get_config(encoder, crtc_state);
2424 2425

	intel_crtc_readout_derived_state(crtc_state);
2426 2427
}

2428
static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2429
{
2430
	int num_pipes = intel_joiner_num_pipes(crtc_state);
2431 2432
	int width, height;

2433
	if (num_pipes < 2)
2434 2435 2436 2437 2438 2439
		return;

	width = drm_rect_width(&crtc_state->pipe_src);
	height = drm_rect_height(&crtc_state->pipe_src);

	drm_rect_init(&crtc_state->pipe_src, 0, 0,
2440
		      width / num_pipes, height);
2441 2442
}

2443 2444 2445 2446 2447
static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

2448
	intel_joiner_compute_pipe_src(crtc_state);
2449 2450 2451 2452 2453 2454 2455

	/*
	 * Pipe horizontal size must be even in:
	 * - DVO ganged mode
	 * - LVDS dual channel mode
	 * - Double wide pipe
	 */
2456
	if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475
		if (crtc_state->double_wide) {
			drm_dbg_kms(&i915->drm,
				    "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
				    crtc->base.base.id, crtc->base.name);
			return -EINVAL;
		}

		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
		    intel_is_dual_link_lvds(i915)) {
			drm_dbg_kms(&i915->drm,
				    "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
				    crtc->base.base.id, crtc->base.name);
			return -EINVAL;
		}
	}

	return 0;
}

2476
static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2477
{
2478
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2479
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2480
	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2481
	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2482
	int clock_limit = i915->display.cdclk.max_dotclk_freq;
2483

2484 2485 2486 2487 2488
	/*
	 * Start with the adjusted_mode crtc timings, which
	 * have been filled with the transcoder timings.
	 */
	drm_mode_copy(pipe_mode, adjusted_mode);
2489

2490
	/* Expand MSO per-segment transcoder timings to full */
2491
	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2492

2493 2494
	/* Derive per-pipe timings in case joiner is used */
	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2495 2496
	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);

2497
	if (DISPLAY_VER(i915) < 4) {
2498
		clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2499

2500 2501 2502 2503 2504
		/*
		 * Enable double wide mode when the dot clock
		 * is > 90% of the (display) core speed.
		 */
		if (intel_crtc_supports_double_wide(crtc) &&
2505
		    pipe_mode->crtc_clock > clock_limit) {
2506
			clock_limit = i915->display.cdclk.max_dotclk_freq;
2507
			crtc_state->double_wide = true;
2508
		}
2509 2510
	}

2511
	if (pipe_mode->crtc_clock > clock_limit) {
2512
		drm_dbg_kms(&i915->drm,
2513 2514
			    "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
			    crtc->base.base.id, crtc->base.name,
2515
			    pipe_mode->crtc_clock, clock_limit,
2516
			    str_yes_no(crtc_state->double_wide));
2517 2518
		return -EINVAL;
	}
2519

2520 2521 2522
	return 0;
}

2523 2524
static int intel_crtc_compute_config(struct intel_atomic_state *state,
				     struct intel_crtc *crtc)
2525
{
2526 2527
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
2528 2529
	int ret;

2530 2531 2532 2533
	ret = intel_dpll_crtc_compute_clock(state, crtc);
	if (ret)
		return ret;

2534 2535 2536 2537 2538 2539 2540 2541
	ret = intel_crtc_compute_pipe_src(crtc_state);
	if (ret)
		return ret;

	ret = intel_crtc_compute_pipe_mode(crtc_state);
	if (ret)
		return ret;

2542
	intel_crtc_compute_pixel_rate(crtc_state);
2543

2544 2545
	if (crtc_state->has_pch_encoder)
		return ilk_fdi_compute_config(crtc, crtc_state);
2546

2547
	return 0;
2548 2549
}

2550
static void
2551
intel_reduce_m_n_ratio(u32 *num, u32 *den)
2552
{
2553 2554
	while (*num > DATA_LINK_M_N_MASK ||
	       *den > DATA_LINK_M_N_MASK) {
2555 2556 2557 2558 2559
		*num >>= 1;
		*den >>= 1;
	}
}

2560 2561
static void compute_m_n(u32 *ret_m, u32 *ret_n,
			u32 m, u32 n, u32 constant_n)
2562
{
2563
	if (constant_n)
2564
		*ret_n = constant_n;
2565 2566
	else
		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2567

2568
	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2569 2570 2571
	intel_reduce_m_n_ratio(ret_m, ret_n);
}

2572
void
2573
intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2574
		       int pixel_clock, int link_clock,
2575 2576
		       int bw_overhead,
		       struct intel_link_m_n *m_n)
2577
{
2578
	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2579 2580
	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
						  bw_overhead);
2581
	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
2582

2583 2584 2585 2586 2587 2588 2589
	/*
	 * Windows/BIOS uses fixed M/N values always. Follow suit.
	 *
	 * Also several DP dongles in particular seem to be fussy
	 * about too large link M/N values. Presumably the 20bit
	 * value used by Windows/BIOS is acceptable to everyone.
	 */
2590
	m_n->tu = 64;
2591
	compute_m_n(&m_n->data_m, &m_n->data_n,
2592
		    data_m, data_n,
2593 2594 2595
		    0x8000000);

	compute_m_n(&m_n->link_m, &m_n->link_n,
2596
		    pixel_clock, link_symbol_clock,
2597
		    0x80000);
2598 2599
}

2600
void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2601 2602 2603 2604 2605 2606 2607 2608
{
	/*
	 * There may be no VBT; and if the BIOS enabled SSC we can
	 * just keep using it to avoid unnecessary flicker.  Whereas if the
	 * BIOS isn't using it, don't assume it will work even if the VBT
	 * indicates as much.
	 */
	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2609 2610
		bool bios_lvds_use_ssc = intel_de_read(dev_priv,
						       PCH_DREF_CONTROL) &
2611 2612
			DREF_SSC1_ENABLE;

2613
		if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2614 2615
			drm_dbg_kms(&dev_priv->drm,
				    "SSC %s by BIOS, overriding VBT which says %s\n",
2616
				    str_enabled_disabled(bios_lvds_use_ssc),
2617 2618
				    str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
			dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2619 2620 2621 2622
		}
	}
}

2623 2624 2625 2626 2627 2628 2629
void intel_zero_m_n(struct intel_link_m_n *m_n)
{
	/* corresponds to 0 register value */
	memset(m_n, 0, sizeof(*m_n));
	m_n->tu = 1;
}

2630 2631 2632 2633
void intel_set_m_n(struct drm_i915_private *i915,
		   const struct intel_link_m_n *m_n,
		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2634
{
2635 2636
	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
	intel_de_write(i915, data_n_reg, m_n->data_n);
2637
	intel_de_write(i915, link_m_reg, m_n->link_m);
2638 2639 2640 2641
	/*
	 * On BDW+ writing LINK_N arms the double buffered update
	 * of all the M/N registers, so it must be written last.
	 */
2642 2643 2644
	intel_de_write(i915, link_n_reg, m_n->link_n);
}

2645 2646
bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
				    enum transcoder transcoder)
2647 2648 2649 2650
{
	if (IS_HASWELL(dev_priv))
		return transcoder == TRANSCODER_EDP;

2651
	return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2652 2653
}

2654 2655
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
				    enum transcoder transcoder,
2656
				    const struct intel_link_m_n *m_n)
2657
{
2658
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2659
	enum pipe pipe = crtc->pipe;
2660

2661
	if (DISPLAY_VER(dev_priv) >= 5)
2662
		intel_set_m_n(dev_priv, m_n,
2663
			      PIPE_DATA_M1(dev_priv, transcoder),
2664
			      PIPE_DATA_N1(dev_priv, transcoder),
2665
			      PIPE_LINK_M1(dev_priv, transcoder),
2666
			      PIPE_LINK_N1(dev_priv, transcoder));
2667
	else
2668 2669 2670
		intel_set_m_n(dev_priv, m_n,
			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2671 2672
}

2673 2674
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
				    enum transcoder transcoder,
2675 2676 2677 2678
				    const struct intel_link_m_n *m_n)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

2679
	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2680 2681 2682
		return;

	intel_set_m_n(dev_priv, m_n,
2683
		      PIPE_DATA_M2(dev_priv, transcoder),
2684
		      PIPE_DATA_N2(dev_priv, transcoder),
2685
		      PIPE_LINK_M2(dev_priv, transcoder),
2686
		      PIPE_LINK_N2(dev_priv, transcoder));
2687 2688
}

2689
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2690
{
2691
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2692 2693 2694
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2695
	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2696
	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2697
	int vsyncshift = 0;
2698 2699 2700

	/* We need to be careful not to changed the adjusted mode, for otherwise
	 * the hw state checker will get angry at the mismatch. */
2701
	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2702
	crtc_vtotal = adjusted_mode->crtc_vtotal;
2703
	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2704
	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2705

2706
	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2707
		/* the chip adds 2 halflines automatically */
2708 2709
		crtc_vtotal -= 1;
		crtc_vblank_end -= 1;
2710

2711
		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2712 2713 2714 2715
			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
		else
			vsyncshift = adjusted_mode->crtc_hsync_start -
				adjusted_mode->crtc_htotal / 2;
2716 2717
		if (vsyncshift < 0)
			vsyncshift += adjusted_mode->crtc_htotal;
2718 2719
	}

2720 2721 2722 2723 2724
	/*
	 * VBLANK_START no longer works on ADL+, instead we must use
	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
	 */
	if (DISPLAY_VER(dev_priv) >= 13) {
2725 2726
		intel_de_write(dev_priv,
			       TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder),
2727 2728 2729 2730 2731 2732 2733 2734 2735
			       crtc_vblank_start - crtc_vdisplay);

		/*
		 * VBLANK_START not used by hw, just clear it
		 * to make it stand out in register dumps.
		 */
		crtc_vblank_start = 1;
	}

2736
	if (DISPLAY_VER(dev_priv) >= 4)
2737 2738
		intel_de_write(dev_priv,
			       TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
2739
			       vsyncshift);
2740

2741
	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
2742 2743
		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
		       HTOTAL(adjusted_mode->crtc_htotal - 1));
2744
	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
2745 2746
		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2747
	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
2748 2749
		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2750

2751
	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
2752
		       VACTIVE(crtc_vdisplay - 1) |
2753
		       VTOTAL(crtc_vtotal - 1));
2754
	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
2755
		       VBLANK_START(crtc_vblank_start - 1) |
2756
		       VBLANK_END(crtc_vblank_end - 1));
2757
	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
2758 2759
		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2760

2761 2762 2763 2764
	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
	 * bits. */
2765
	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2766
	    (pipe == PIPE_B || pipe == PIPE_C))
2767
		intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
2768 2769
			       VACTIVE(crtc_vdisplay - 1) |
			       VTOTAL(crtc_vtotal - 1));
2770 2771
}

2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;

	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
	crtc_vtotal = adjusted_mode->crtc_vtotal;
	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
	crtc_vblank_end = adjusted_mode->crtc_vblank_end;

	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);

	/*
	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
	 * But let's write it anyway to keep the state checker happy.
	 */
2791
	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
2792 2793 2794 2795 2796 2797
		       VBLANK_START(crtc_vblank_start - 1) |
		       VBLANK_END(crtc_vblank_end - 1));
	/*
	 * The double buffer latch point for TRANS_VTOTAL
	 * is the transcoder's undelayed vblank.
	 */
2798
	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
2799 2800 2801 2802
		       VACTIVE(crtc_vdisplay - 1) |
		       VTOTAL(crtc_vtotal - 1));
}

2803
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2804
{
2805
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2806
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2807 2808
	int width = drm_rect_width(&crtc_state->pipe_src);
	int height = drm_rect_height(&crtc_state->pipe_src);
2809
	enum pipe pipe = crtc->pipe;
2810

2811 2812 2813
	/* pipesrc controls the size that is scaled from, which should
	 * always be the user's requested size.
	 */
2814
	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
2815
		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2816 2817
}

2818 2819
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
{
2820
	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2821 2822
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

2823
	if (DISPLAY_VER(dev_priv) == 2)
2824 2825
		return false;

2826
	if (DISPLAY_VER(dev_priv) >= 9 ||
2827
	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2828 2829
		return intel_de_read(dev_priv,
				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2830
	else
2831 2832
		return intel_de_read(dev_priv,
				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2833 2834
}

2835 2836
static void intel_get_transcoder_timings(struct intel_crtc *crtc,
					 struct intel_crtc_state *pipe_config)
2837 2838
{
	struct drm_device *dev = crtc->base.dev;
2839
	struct drm_i915_private *dev_priv = to_i915(dev);
2840
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2841
	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2842
	u32 tmp;
2843

2844
	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
2845 2846
	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2847 2848

	if (!transcoder_is_dsi(cpu_transcoder)) {
2849 2850
		tmp = intel_de_read(dev_priv,
				    TRANS_HBLANK(dev_priv, cpu_transcoder));
2851 2852
		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2853
	}
2854

2855
	tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
2856 2857
	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2858

2859
	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
2860 2861
	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2862

2863
	/* FIXME TGL+ DSI transcoders have this! */
2864
	if (!transcoder_is_dsi(cpu_transcoder)) {
2865 2866
		tmp = intel_de_read(dev_priv,
				    TRANS_VBLANK(dev_priv, cpu_transcoder));
2867 2868
		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2869
	}
2870
	tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder));
2871 2872
	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2873

2874
	if (intel_pipe_is_interlaced(pipe_config)) {
2875 2876 2877
		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
		adjusted_mode->crtc_vtotal += 1;
		adjusted_mode->crtc_vblank_end += 1;
2878
	}
2879 2880 2881 2882

	if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
		adjusted_mode->crtc_vblank_start =
			adjusted_mode->crtc_vdisplay +
2883 2884
			intel_de_read(dev_priv,
				      TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
2885 2886
}

2887
static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2888 2889
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2890
	int num_pipes = intel_joiner_num_pipes(crtc_state);
2891
	enum pipe primary_pipe, pipe = crtc->pipe;
2892 2893 2894 2895 2896
	int width;

	if (num_pipes < 2)
		return;

2897
	primary_pipe = joiner_primary_pipe(crtc_state);
2898 2899 2900
	width = drm_rect_width(&crtc_state->pipe_src);

	drm_rect_translate_to(&crtc_state->pipe_src,
2901
			      (pipe - primary_pipe) * width, 0);
2902 2903
}

2904 2905 2906 2907
static void intel_get_pipe_src_size(struct intel_crtc *crtc,
				    struct intel_crtc_state *pipe_config)
{
	struct drm_device *dev = crtc->base.dev;
2908
	struct drm_i915_private *dev_priv = to_i915(dev);
2909
	u32 tmp;
2910

2911
	tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
2912 2913 2914 2915

	drm_rect_init(&pipe_config->pipe_src, 0, 0,
		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
		      REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2916

2917
	intel_joiner_adjust_pipe_src(pipe_config);
2918 2919
}

2920
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2921
{
2922
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2923
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2924 2925
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
	u32 val = 0;
2926

2927 2928 2929 2930 2931 2932
	/*
	 * - We keep both pipes enabled on 830
	 * - During modeset the pipe is still disabled and must remain so
	 * - During fastset the pipe is already enabled and must remain so
	 */
	if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2933
		val |= TRANSCONF_ENABLE;
2934

2935
	if (crtc_state->double_wide)
2936
		val |= TRANSCONF_DOUBLE_WIDE;
2937

2938
	/* only g4x and later have fancy bpc/dither controls */
2939 2940
	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
	    IS_CHERRYVIEW(dev_priv)) {
2941
		/* Bspec claims that we can't use dithering for 30bpp pipes. */
2942
		if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2943 2944
			val |= TRANSCONF_DITHER_EN |
				TRANSCONF_DITHER_TYPE_SP;
2945

2946
		switch (crtc_state->pipe_bpp) {
2947 2948 2949 2950
		default:
			/* Case prevented by intel_choose_pipe_bpp_dither. */
			MISSING_CASE(crtc_state->pipe_bpp);
			fallthrough;
2951
		case 18:
2952
			val |= TRANSCONF_BPC_6;
2953 2954
			break;
		case 24:
2955
			val |= TRANSCONF_BPC_8;
2956 2957
			break;
		case 30:
2958
			val |= TRANSCONF_BPC_10;
2959
			break;
2960 2961 2962
		}
	}

2963
	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2964
		if (DISPLAY_VER(dev_priv) < 4 ||
2965
		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2966
			val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2967
		else
2968
			val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2969
	} else {
2970
		val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2971
	}
2972

2973
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2974
	     crtc_state->limited_color_range)
2975
		val |= TRANSCONF_COLOR_RANGE_SELECT;
2976

2977
	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2978

2979 2980 2981
	if (crtc_state->wgc_enable)
		val |= TRANSCONF_WGC_ENABLE;

2982
	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2983

2984 2985
	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
2986 2987
}

2988 2989 2990 2991 2992
static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
{
	if (IS_I830(dev_priv))
		return false;

2993
	return DISPLAY_VER(dev_priv) >= 4 ||
2994 2995 2996
		IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
}

2997
static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2998
{
2999
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3000
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3001
	enum pipe pipe;
3002
	u32 tmp;
3003

3004
	if (!i9xx_has_pfit(dev_priv))
3005 3006
		return;

3007
	tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
3008 3009
	if (!(tmp & PFIT_ENABLE))
		return;
3010

3011
	/* Check whether the pfit is attached to our pipe. */
3012 3013 3014 3015 3016 3017 3018
	if (DISPLAY_VER(dev_priv) >= 4)
		pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
	else
		pipe = PIPE_B;

	if (pipe != crtc->pipe)
		return;
3019

3020 3021
	crtc_state->gmch_pfit.control = tmp;
	crtc_state->gmch_pfit.pgm_ratios =
3022
		intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
3023 3024
}

3025
static enum intel_output_format
3026
bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
3027 3028
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3029 3030
	u32 tmp;

3031
	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3032

3033
	if (tmp & PIPE_MISC_YUV420_ENABLE) {
3034
		/* We support 4:2:0 in full blend mode only */
3035
		drm_WARN_ON(&dev_priv->drm,
3036
			    (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3037

3038
		return INTEL_OUTPUT_FORMAT_YCBCR420;
3039
	} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3040 3041 3042 3043
		return INTEL_OUTPUT_FORMAT_YCBCR444;
	} else {
		return INTEL_OUTPUT_FORMAT_RGB;
	}
3044 3045
}

3046
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3047
				 struct intel_crtc_state *pipe_config)
3048
{
3049
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3050
	enum intel_display_power_domain power_domain;
3051
	intel_wakeref_t wakeref;
3052
	u32 tmp;
3053
	bool ret;
3054

3055
	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3056 3057
	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
3058 3059
		return false;

3060
	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3061
	pipe_config->sink_format = pipe_config->output_format;
3062
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3063
	pipe_config->shared_dpll = NULL;
3064

3065 3066
	ret = false;

3067 3068
	tmp = intel_de_read(dev_priv,
			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3069
	if (!(tmp & TRANSCONF_ENABLE))
3070
		goto out;
3071

3072 3073
	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
	    IS_CHERRYVIEW(dev_priv)) {
3074 3075
		switch (tmp & TRANSCONF_BPC_MASK) {
		case TRANSCONF_BPC_6:
3076 3077
			pipe_config->pipe_bpp = 18;
			break;
3078
		case TRANSCONF_BPC_8:
3079 3080
			pipe_config->pipe_bpp = 24;
			break;
3081
		case TRANSCONF_BPC_10:
3082 3083 3084
			pipe_config->pipe_bpp = 30;
			break;
		default:
3085
			MISSING_CASE(tmp);
3086 3087 3088 3089
			break;
		}
	}

3090
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3091
	    (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3092 3093
		pipe_config->limited_color_range = true;

3094
	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3095

3096
	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3097

3098 3099 3100 3101
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
	    (tmp & TRANSCONF_WGC_ENABLE))
		pipe_config->wgc_enable = true;

3102
	intel_color_get_config(pipe_config);
3103

3104
	if (DISPLAY_VER(dev_priv) < 4)
3105
		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3106

3107
	intel_get_transcoder_timings(crtc, pipe_config);
3108
	intel_get_pipe_src_size(crtc, pipe_config);
3109

3110
	i9xx_get_pfit_config(pipe_config);
3111

3112 3113
	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);

3114
	if (DISPLAY_VER(dev_priv) >= 4) {
3115
		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3116 3117 3118
		pipe_config->pixel_multiplier =
			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3119
	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3120
		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3121
		tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3122 3123 3124 3125 3126 3127 3128 3129 3130 3131
		pipe_config->pixel_multiplier =
			((tmp & SDVO_MULTIPLIER_MASK)
			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
	} else {
		/* Note that on i915G/GM the pixel multiplier is in the sdvo
		 * port and will be fixed up in the encoder->get_config
		 * function. */
		pipe_config->pixel_multiplier = 1;
	}

3132
	if (IS_CHERRYVIEW(dev_priv))
3133
		chv_crtc_clock_get(pipe_config);
3134
	else if (IS_VALLEYVIEW(dev_priv))
3135
		vlv_crtc_clock_get(pipe_config);
3136
	else
3137
		i9xx_crtc_clock_get(pipe_config);
3138

3139 3140 3141 3142 3143
	/*
	 * Normally the dotclock is filled in by the encoder .get_config()
	 * but in case the pipe is enabled w/o any ports we need a sane
	 * default.
	 */
3144
	pipe_config->hw.adjusted_mode.crtc_clock =
3145 3146
		pipe_config->port_clock / pipe_config->pixel_multiplier;

3147 3148 3149
	ret = true;

out:
3150
	intel_display_power_put(dev_priv, power_domain, wakeref);
3151 3152

	return ret;
3153 3154
}

3155
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3156
{
3157
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3158
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3159
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3160
	u32 val = 0;
3161

3162 3163 3164 3165 3166
	/*
	 * - During modeset the pipe is still disabled and must remain so
	 * - During fastset the pipe is already enabled and must remain so
	 */
	if (!intel_crtc_needs_modeset(crtc_state))
3167
		val |= TRANSCONF_ENABLE;
3168

3169
	switch (crtc_state->pipe_bpp) {
3170 3171 3172 3173
	default:
		/* Case prevented by intel_choose_pipe_bpp_dither. */
		MISSING_CASE(crtc_state->pipe_bpp);
		fallthrough;
3174
	case 18:
3175
		val |= TRANSCONF_BPC_6;
3176 3177
		break;
	case 24:
3178
		val |= TRANSCONF_BPC_8;
3179 3180
		break;
	case 30:
3181
		val |= TRANSCONF_BPC_10;
3182 3183
		break;
	case 36:
3184
		val |= TRANSCONF_BPC_12;
3185 3186 3187
		break;
	}

3188
	if (crtc_state->dither)
3189
		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3190

3191
	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3192
		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3193
	else
3194
		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3195

3196 3197 3198 3199
	/*
	 * This would end up with an odd purple hue over
	 * the entire display. Make sure we don't do it.
	 */
3200 3201
	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3202

3203 3204
	if (crtc_state->limited_color_range &&
	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3205
		val |= TRANSCONF_COLOR_RANGE_SELECT;
3206

3207
	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3208
		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3209

3210
	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3211

3212 3213
	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3214

3215 3216
	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
3217 3218
}

3219
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3220
{
3221
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3222 3223
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3224
	u32 val = 0;
3225

3226 3227 3228 3229 3230
	/*
	 * - During modeset the pipe is still disabled and must remain so
	 * - During fastset the pipe is already enabled and must remain so
	 */
	if (!intel_crtc_needs_modeset(crtc_state))
3231
		val |= TRANSCONF_ENABLE;
3232

3233
	if (IS_HASWELL(dev_priv) && crtc_state->dither)
3234
		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3235

3236
	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3237
		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3238
	else
3239
		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3240

3241 3242
	if (IS_HASWELL(dev_priv) &&
	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3243
		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3244

3245 3246
	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
3247 3248
}

3249
static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3250
{
3251
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3252 3253
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	u32 val = 0;
3254

3255 3256
	switch (crtc_state->pipe_bpp) {
	case 18:
3257
		val |= PIPE_MISC_BPC_6;
3258 3259
		break;
	case 24:
3260
		val |= PIPE_MISC_BPC_8;
3261 3262
		break;
	case 30:
3263
		val |= PIPE_MISC_BPC_10;
3264 3265
		break;
	case 36:
3266
		/* Port output 12BPC defined for ADLP+ */
3267
		if (DISPLAY_VER(dev_priv) >= 13)
3268
			val |= PIPE_MISC_BPC_12_ADLP;
3269 3270 3271 3272 3273
		break;
	default:
		MISSING_CASE(crtc_state->pipe_bpp);
		break;
	}
3274

3275
	if (crtc_state->dither)
3276
		val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3277

3278 3279
	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3280
		val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3281

3282
	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3283 3284
		val |= PIPE_MISC_YUV420_ENABLE |
			PIPE_MISC_YUV420_MODE_FULL_BLEND;
3285

3286
	if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3287
		val |= PIPE_MISC_HDR_MODE_PRECISION;
3288

3289
	if (DISPLAY_VER(dev_priv) >= 12)
3290
		val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3291

3292 3293 3294 3295
	/* allow PSR with sprite enabled */
	if (IS_BROADWELL(dev_priv))
		val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;

3296
	intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3297 3298
}

3299
int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3300 3301 3302 3303
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	u32 tmp;

3304
	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3305

3306 3307
	switch (tmp & PIPE_MISC_BPC_MASK) {
	case PIPE_MISC_BPC_6:
3308
		return 18;
3309
	case PIPE_MISC_BPC_8:
3310
		return 24;
3311
	case PIPE_MISC_BPC_10:
3312
		return 30;
3313 3314 3315 3316 3317 3318 3319 3320 3321 3322
	/*
	 * PORT OUTPUT 12 BPC defined for ADLP+.
	 *
	 * TODO:
	 * For previous platforms with DSI interface, bits 5:7
	 * are used for storing pipe_bpp irrespective of dithering.
	 * Since the value of 12 BPC is not defined for these bits
	 * on older platforms, need to find a workaround for 12 BPC
	 * MIPI DSI HW readout.
	 */
3323
	case PIPE_MISC_BPC_12_ADLP:
3324
		if (DISPLAY_VER(dev_priv) >= 13)
3325 3326
			return 36;
		fallthrough;
3327 3328 3329 3330 3331 3332
	default:
		MISSING_CASE(tmp);
		return 0;
	}
}

3333
int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3334 3335 3336 3337 3338 3339 3340
{
	/*
	 * Account for spread spectrum to avoid
	 * oversubscribing the link. Max center spread
	 * is 2.5%; use 5% for safety's sake.
	 */
	u32 bps = target_clock * bpp * 21 / 20;
3341
	return DIV_ROUND_UP(bps, link_bw * 8);
3342 3343
}

3344 3345 3346 3347
void intel_get_m_n(struct drm_i915_private *i915,
		   struct intel_link_m_n *m_n,
		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3348
{
3349 3350
	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3351 3352
	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3353
	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3354 3355
}

3356 3357 3358
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
				    enum transcoder transcoder,
				    struct intel_link_m_n *m_n)
3359
{
3360
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3361
	enum pipe pipe = crtc->pipe;
3362

3363
	if (DISPLAY_VER(dev_priv) >= 5)
3364
		intel_get_m_n(dev_priv, m_n,
3365
			      PIPE_DATA_M1(dev_priv, transcoder),
3366
			      PIPE_DATA_N1(dev_priv, transcoder),
3367
			      PIPE_LINK_M1(dev_priv, transcoder),
3368
			      PIPE_LINK_N1(dev_priv, transcoder));
3369
	else
3370 3371 3372
		intel_get_m_n(dev_priv, m_n,
			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3373 3374 3375 3376 3377 3378 3379 3380
}

void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
				    enum transcoder transcoder,
				    struct intel_link_m_n *m_n)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

3381
	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3382 3383 3384
		return;

	intel_get_m_n(dev_priv, m_n,
3385
		      PIPE_DATA_M2(dev_priv, transcoder),
3386
		      PIPE_DATA_N2(dev_priv, transcoder),
3387
		      PIPE_LINK_M2(dev_priv, transcoder),
3388
		      PIPE_LINK_N2(dev_priv, transcoder));
3389 3390
}

3391
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3392
{
3393 3394
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3395
	u32 ctl, pos, size;
3396
	enum pipe pipe;
3397

3398 3399
	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
	if ((ctl & PF_ENABLE) == 0)
3400
		return;
3401

3402 3403 3404 3405 3406
	if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
		pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
	else
		pipe = crtc->pipe;

3407
	crtc_state->pch_pfit.enabled = true;
3408 3409 3410 3411

	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));

3412
	drm_rect_init(&crtc_state->pch_pfit.dst,
3413 3414 3415 3416
		      REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
		      REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
		      REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
		      REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3417 3418 3419 3420 3421 3422

	/*
	 * We currently do not free assignements of panel fitters on
	 * ivb/hsw (since we don't use the higher upscaling modes which
	 * differentiates them) so just WARN about this case for now.
	 */
3423
	drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3424 3425
}

3426 3427
static bool ilk_get_pipe_config(struct intel_crtc *crtc,
				struct intel_crtc_state *pipe_config)
3428 3429
{
	struct drm_device *dev = crtc->base.dev;
3430
	struct drm_i915_private *dev_priv = to_i915(dev);
3431
	enum intel_display_power_domain power_domain;
3432
	intel_wakeref_t wakeref;
3433
	u32 tmp;
3434
	bool ret;
3435

3436
	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3437 3438
	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
	if (!wakeref)
3439 3440
		return false;

3441
	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3442
	pipe_config->shared_dpll = NULL;
3443

3444
	ret = false;
3445 3446
	tmp = intel_de_read(dev_priv,
			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3447
	if (!(tmp & TRANSCONF_ENABLE))
3448
		goto out;
3449

3450 3451
	switch (tmp & TRANSCONF_BPC_MASK) {
	case TRANSCONF_BPC_6:
3452 3453
		pipe_config->pipe_bpp = 18;
		break;
3454
	case TRANSCONF_BPC_8:
3455 3456
		pipe_config->pipe_bpp = 24;
		break;
3457
	case TRANSCONF_BPC_10:
3458 3459
		pipe_config->pipe_bpp = 30;
		break;
3460
	case TRANSCONF_BPC_12:
3461 3462 3463 3464 3465 3466
		pipe_config->pipe_bpp = 36;
		break;
	default:
		break;
	}

3467
	if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3468 3469
		pipe_config->limited_color_range = true;

3470 3471 3472
	switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
	case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
	case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3473 3474 3475 3476 3477 3478 3479
		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
		break;
	default:
		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
		break;
	}

3480 3481
	pipe_config->sink_format = pipe_config->output_format;

3482
	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3483

3484
	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3485

3486
	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3487

3488
	intel_color_get_config(pipe_config);
3489

3490
	pipe_config->pixel_multiplier = 1;
3491

3492
	ilk_pch_get_config(pipe_config);
3493

3494
	intel_get_transcoder_timings(crtc, pipe_config);
3495
	intel_get_pipe_src_size(crtc, pipe_config);
3496

3497
	ilk_get_pfit_config(pipe_config);
3498

3499 3500 3501
	ret = true;

out:
3502
	intel_display_power_put(dev_priv, power_domain, wakeref);
3503 3504

	return ret;
3505
}
3506

3507
static u8 joiner_pipes(struct drm_i915_private *i915)
3508
{
3509 3510
	u8 pipes;

3511
	if (DISPLAY_VER(i915) >= 12)
3512
		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3513
	else if (DISPLAY_VER(i915) >= 11)
3514
		pipes = BIT(PIPE_B) | BIT(PIPE_C);
3515
	else
3516 3517
		pipes = 0;

3518
	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3519 3520
}

3521 3522 3523 3524 3525 3526 3527 3528 3529 3530
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
					   enum transcoder cpu_transcoder)
{
	enum intel_display_power_domain power_domain;
	intel_wakeref_t wakeref;
	u32 tmp = 0;

	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);

	with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3531 3532
		tmp = intel_de_read(dev_priv,
				    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3533 3534 3535 3536

	return tmp & TRANS_DDI_FUNC_ENABLE;
}

3537
static void enabled_joiner_pipes(struct drm_i915_private *dev_priv,
3538
				 u8 *primary_pipes, u8 *secondary_pipes)
3539 3540 3541
{
	struct intel_crtc *crtc;

3542 3543
	*primary_pipes = 0;
	*secondary_pipes = 0;
3544

3545
	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3546
					 joiner_pipes(dev_priv)) {
3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557
		enum intel_display_power_domain power_domain;
		enum pipe pipe = crtc->pipe;
		intel_wakeref_t wakeref;

		power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));

			if (!(tmp & BIG_JOINER_ENABLE))
				continue;

3558 3559
			if (tmp & PRIMARY_BIG_JOINER_ENABLE)
				*primary_pipes |= BIT(pipe);
3560
			else
3561
				*secondary_pipes |= BIT(pipe);
3562 3563 3564 3565 3566 3567 3568 3569 3570
		}

		if (DISPLAY_VER(dev_priv) < 13)
			continue;

		power_domain = POWER_DOMAIN_PIPE(pipe);
		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
			u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));

3571 3572 3573 3574
			if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
				*primary_pipes |= BIT(pipe);
			if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
				*secondary_pipes |= BIT(pipe);
3575 3576 3577
		}
	}

3578 3579 3580 3581
	/* Joiner pipes should always be consecutive primary and secondary */
	drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,
		 "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n",
		 *primary_pipes, *secondary_pipes);
3582 3583
}

3584
static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
3585
{
3586
	if ((secondary_pipes & BIT(pipe)) == 0)
3587 3588 3589
		return pipe;

	/* ignore everything above our pipe */
3590
	primary_pipes &= ~GENMASK(7, pipe);
3591

3592 3593
	/* highest remaining bit should be our primary pipe */
	return fls(primary_pipes) - 1;
3594 3595
}

3596
static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes)
3597
{
3598
	enum pipe primary_pipe, next_primary_pipe;
3599

3600
	primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes);
3601

3602
	if ((primary_pipes & BIT(primary_pipe)) == 0)
3603 3604
		return 0;

3605 3606
	/* ignore our primary pipe and everything below it */
	primary_pipes &= ~GENMASK(primary_pipe, 0);
3607
	/* make sure a high bit is set for the ffs() */
3608 3609 3610
	primary_pipes |= BIT(7);
	/* lowest remaining bit should be the next primary pipe */
	next_primary_pipe = ffs(primary_pipes) - 1;
3611

3612
	return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe);
3613 3614
}

3615 3616 3617 3618 3619 3620 3621 3622 3623 3624
static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
{
	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);

	if (DISPLAY_VER(i915) >= 11)
		panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);

	return panel_transcoder_mask;
}

3625
static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3626 3627
{
	struct drm_device *dev = crtc->base.dev;
3628
	struct drm_i915_private *dev_priv = to_i915(dev);
3629
	u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3630
	enum transcoder cpu_transcoder;
3631
	u8 primary_pipes, secondary_pipes;
3632
	u8 enabled_transcoders = 0;
3633 3634 3635 3636 3637

	/*
	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
	 * consistency and less surprising code; it's in always on power).
	 */
3638
	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3639
				       panel_transcoder_mask) {
3640 3641
		enum intel_display_power_domain power_domain;
		intel_wakeref_t wakeref;
3642
		enum pipe trans_pipe;
3643
		u32 tmp = 0;
3644

3645 3646
		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3647 3648
			tmp = intel_de_read(dev_priv,
					    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
3649

3650
		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3651
			continue;
3652

3653 3654
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		default:
3655 3656
			drm_WARN(dev, 1,
				 "unknown pipe linked to transcoder %s\n",
3657
				 transcoder_name(cpu_transcoder));
3658
			fallthrough;
3659 3660
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
		case TRANS_DDI_EDP_INPUT_A_ON:
3661
			trans_pipe = PIPE_A;
3662 3663
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
3664
			trans_pipe = PIPE_B;
3665 3666
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
3667
			trans_pipe = PIPE_C;
3668
			break;
3669 3670 3671
		case TRANS_DDI_EDP_INPUT_D_ONOFF:
			trans_pipe = PIPE_D;
			break;
3672 3673
		}

3674 3675
		if (trans_pipe == crtc->pipe)
			enabled_transcoders |= BIT(cpu_transcoder);
3676 3677
	}

3678
	/* single pipe or joiner primary */
3679 3680 3681 3682
	cpu_transcoder = (enum transcoder) crtc->pipe;
	if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
		enabled_transcoders |= BIT(cpu_transcoder);

3683 3684 3685
	/* joiner secondary -> consider the primary pipe's transcoder as well */
	enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes);
	if (secondary_pipes & BIT(crtc->pipe)) {
3686
		cpu_transcoder = (enum transcoder)
3687
			get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);
3688 3689 3690 3691
		if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
			enabled_transcoders |= BIT(cpu_transcoder);
	}

3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742
	return enabled_transcoders;
}

static bool has_edp_transcoders(u8 enabled_transcoders)
{
	return enabled_transcoders & BIT(TRANSCODER_EDP);
}

static bool has_dsi_transcoders(u8 enabled_transcoders)
{
	return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
				      BIT(TRANSCODER_DSI_1));
}

static bool has_pipe_transcoders(u8 enabled_transcoders)
{
	return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
				       BIT(TRANSCODER_DSI_0) |
				       BIT(TRANSCODER_DSI_1));
}

static void assert_enabled_transcoders(struct drm_i915_private *i915,
				       u8 enabled_transcoders)
{
	/* Only one type of transcoder please */
	drm_WARN_ON(&i915->drm,
		    has_edp_transcoders(enabled_transcoders) +
		    has_dsi_transcoders(enabled_transcoders) +
		    has_pipe_transcoders(enabled_transcoders) > 1);

	/* Only DSI transcoders can be ganged */
	drm_WARN_ON(&i915->drm,
		    !has_dsi_transcoders(enabled_transcoders) &&
		    !is_power_of_2(enabled_transcoders));
}

static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
				     struct intel_crtc_state *pipe_config,
				     struct intel_display_power_domain_set *power_domain_set)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	unsigned long enabled_transcoders;
	u32 tmp;

	enabled_transcoders = hsw_enabled_transcoders(crtc);
	if (!enabled_transcoders)
		return false;

	assert_enabled_transcoders(dev_priv, enabled_transcoders);

3743
	/*
3744 3745 3746
	 * With the exception of DSI we should only ever have
	 * a single enabled transcoder. With DSI let's just
	 * pick the first one.
3747
	 */
3748
	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3749

3750 3751
	if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3752
		return false;
3753

3754
	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3755 3756
		tmp = intel_de_read(dev_priv,
				    TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));
3757 3758 3759 3760 3761

		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
			pipe_config->pch_pfit.force_thru = true;
	}

3762 3763
	tmp = intel_de_read(dev_priv,
			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3764

3765
	return tmp & TRANSCONF_ENABLE;
3766 3767
}

3768 3769
static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
					 struct intel_crtc_state *pipe_config,
3770
					 struct intel_display_power_domain_set *power_domain_set)
3771
{
3772 3773
	struct intel_display *display = to_intel_display(crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3774
	enum transcoder cpu_transcoder;
3775
	enum port port;
3776 3777 3778 3779 3780 3781 3782 3783
	u32 tmp;

	for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
		if (port == PORT_A)
			cpu_transcoder = TRANSCODER_DSI_A;
		else
			cpu_transcoder = TRANSCODER_DSI_C;

3784 3785
		if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
							       POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3786
			continue;
3787

3788 3789 3790 3791 3792 3793 3794
		/*
		 * The PLL needs to be enabled with a valid divider
		 * configuration, otherwise accessing DSI registers will hang
		 * the machine. See BSpec North Display Engine
		 * registers/MIPI[BXT]. We can break out here early, since we
		 * need the same DSI PLL to be enabled for both DSI ports.
		 */
3795
		if (!bxt_dsi_pll_is_enabled(dev_priv))
3796 3797
			break;

3798
		/* XXX: this works for video mode only */
3799
		tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3800 3801 3802
		if (!(tmp & DPI_ENABLE))
			continue;

3803
		tmp = intel_de_read(display, MIPI_CTRL(display, port));
3804 3805 3806 3807 3808 3809 3810
		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
			continue;

		pipe_config->cpu_transcoder = cpu_transcoder;
		break;
	}

3811
	return transcoder_is_dsi(pipe_config->cpu_transcoder);
3812 3813
}

3814
static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
3815 3816 3817
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3818
	u8 primary_pipes, secondary_pipes;
3819 3820
	enum pipe pipe = crtc->pipe;

3821
	enabled_joiner_pipes(i915, &primary_pipes, &secondary_pipes);
3822

3823
	if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0)
3824 3825
		return;

3826
	crtc_state->joiner_pipes =
3827 3828
		BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) |
		get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes);
3829 3830
}

3831 3832
static bool hsw_get_pipe_config(struct intel_crtc *crtc,
				struct intel_crtc_state *pipe_config)
3833
{
3834
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3835
	bool active;
3836
	u32 tmp;
3837

3838
	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3839
						       POWER_DOMAIN_PIPE(crtc->pipe)))
3840
		return false;
3841

3842
	pipe_config->shared_dpll = NULL;
3843

3844
	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3845

3846
	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3847
	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3848
		drm_WARN_ON(&dev_priv->drm, active);
3849
		active = true;
3850 3851
	}

3852 3853 3854
	if (!active)
		goto out;

3855
	intel_joiner_get_config(pipe_config);
3856
	intel_dsc_get_config(pipe_config);
3857

3858 3859
	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
	    DISPLAY_VER(dev_priv) >= 11)
3860
		intel_get_transcoder_timings(crtc, pipe_config);
3861

3862
	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3863
		intel_vrr_get_config(pipe_config);
3864

3865
	intel_get_pipe_src_size(crtc, pipe_config);
3866

3867
	if (IS_HASWELL(dev_priv)) {
3868
		u32 tmp = intel_de_read(dev_priv,
3869
					TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
3870

3871
		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3872 3873 3874 3875
			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
		else
			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
	} else {
3876
		pipe_config->output_format =
3877
			bdw_get_pipe_misc_output_format(crtc);
3878
	}
3879

3880 3881
	pipe_config->sink_format = pipe_config->output_format;

3882 3883
	intel_color_get_config(pipe_config);

3884 3885 3886 3887 3888 3889
	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
		pipe_config->ips_linetime =
			REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);

3890
	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3891
						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3892
		if (DISPLAY_VER(dev_priv) >= 9)
3893
			skl_scaler_get_config(pipe_config);
3894
		else
3895
			ilk_get_pfit_config(pipe_config);
3896
	}
3897

3898
	hsw_ips_get_config(pipe_config);
3899

3900
	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3901
	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3902
		pipe_config->pixel_multiplier =
3903
			intel_de_read(dev_priv,
3904
				      TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;
3905 3906 3907
	} else {
		pipe_config->pixel_multiplier = 1;
	}
3908

3909
	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3910
		tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
3911 3912 3913 3914 3915 3916 3917

		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
	} else {
		/* no idea if this is correct */
		pipe_config->framestart_delay = 1;
	}

3918
out:
3919
	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3920

3921
	return active;
3922 3923
}

3924
bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3925 3926 3927 3928
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

3929
	if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3930 3931 3932 3933
		return false;

	crtc_state->hw.active = true;

3934 3935
	intel_crtc_readout_derived_state(crtc_state);

3936
	return true;
3937 3938
}

3939 3940
int intel_dotclock_calculate(int link_freq,
			     const struct intel_link_m_n *m_n)
3941 3942
{
	/*
3943
	 * The calculation for the data clock -> pixel clock is:
3944
	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3945
	 * But we want to avoid losing precison if possible, so:
3946
	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3947
	 *
3948 3949 3950 3951 3952
	 * and for link freq (10kbs units) -> pixel clock it is:
	 * link_symbol_clock = link_freq * 10 / link_symbol_size
	 * pixel_clock = (m * link_symbol_clock) / n
	 *    or for more precision:
	 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
3953 3954
	 */

3955 3956
	if (!m_n->link_n)
		return 0;
3957

3958 3959
	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
				m_n->link_n * intel_dp_link_symbol_size(link_freq));
3960
}
3961

3962 3963 3964 3965 3966 3967 3968 3969
int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
{
	int dotclock;

	if (intel_crtc_has_dp_encoder(pipe_config))
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
						    &pipe_config->dp_m_n);
	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3970 3971
		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
					     pipe_config->pipe_bpp);
3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984
	else
		dotclock = pipe_config->port_clock;

	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
	    !intel_crtc_has_dp_encoder(pipe_config))
		dotclock *= 2;

	if (pipe_config->pixel_multiplier)
		dotclock /= pipe_config->pixel_multiplier;

	return dotclock;
}

3985 3986 3987
/* Returns the currently programmed mode of the given encoder. */
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder)
3988
{
3989 3990
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc_state *crtc_state;
3991
	struct drm_display_mode *mode;
3992 3993 3994 3995 3996 3997
	struct intel_crtc *crtc;
	enum pipe pipe;

	if (!encoder->get_hw_state(encoder, &pipe))
		return NULL;

3998
	crtc = intel_crtc_for_pipe(dev_priv, pipe);
3999 4000 4001 4002 4003

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

4004
	crtc_state = intel_crtc_state_alloc(crtc);
4005
	if (!crtc_state) {
4006 4007 4008 4009
		kfree(mode);
		return NULL;
	}

4010
	if (!intel_crtc_get_pipe_config(crtc_state)) {
4011
		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4012 4013 4014
		kfree(mode);
		return NULL;
	}
4015

4016
	intel_encoder_get_config(encoder, crtc_state);
4017

4018
	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4019

4020
	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4021

4022 4023 4024
	return mode;
}

4025 4026 4027 4028
static bool encoders_cloneable(const struct intel_encoder *a,
			       const struct intel_encoder *b)
{
	/* masks could be asymmetric, so check both ways */
4029 4030
	return a == b || (a->cloneable & BIT(b->type) &&
			  b->cloneable & BIT(a->type));
4031 4032
}

4033
static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4034 4035 4036 4037 4038 4039 4040 4041
					 struct intel_crtc *crtc,
					 struct intel_encoder *encoder)
{
	struct intel_encoder *source_encoder;
	struct drm_connector *connector;
	struct drm_connector_state *connector_state;
	int i;

4042
	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054
		if (connector_state->crtc != &crtc->base)
			continue;

		source_encoder =
			to_intel_encoder(connector_state->best_encoder);
		if (!encoders_cloneable(encoder, source_encoder))
			return false;
	}

	return true;
}

4055 4056 4057 4058 4059 4060 4061
static int icl_add_linked_planes(struct intel_atomic_state *state)
{
	struct intel_plane *plane, *linked;
	struct intel_plane_state *plane_state, *linked_plane_state;
	int i;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4062
		linked = plane_state->planar_linked_plane;
4063 4064 4065 4066 4067 4068 4069 4070

		if (!linked)
			continue;

		linked_plane_state = intel_atomic_get_plane_state(state, linked);
		if (IS_ERR(linked_plane_state))
			return PTR_ERR(linked_plane_state);

4071 4072 4073 4074
		drm_WARN_ON(state->base.dev,
			    linked_plane_state->planar_linked_plane != plane);
		drm_WARN_ON(state->base.dev,
			    linked_plane_state->planar_slave == plane_state->planar_slave);
4075 4076 4077 4078 4079
	}

	return 0;
}

4080 4081
static int icl_check_nv12_planes(struct intel_atomic_state *state,
				 struct intel_crtc *crtc)
4082
{
4083 4084 4085
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
4086 4087 4088 4089
	struct intel_plane *plane, *linked;
	struct intel_plane_state *plane_state;
	int i;

4090
	if (DISPLAY_VER(dev_priv) < 11)
4091 4092 4093 4094 4095 4096 4097
		return 0;

	/*
	 * Destroy all old plane links and make the slave plane invisible
	 * in the crtc_state->active_planes mask.
	 */
	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4098
		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4099 4100
			continue;

4101
		plane_state->planar_linked_plane = NULL;
4102
		if (plane_state->planar_slave && !plane_state->uapi.visible) {
4103
			crtc_state->enabled_planes &= ~BIT(plane->id);
4104
			crtc_state->active_planes &= ~BIT(plane->id);
4105
			crtc_state->update_planes |= BIT(plane->id);
4106
			crtc_state->data_rate[plane->id] = 0;
4107
			crtc_state->rel_data_rate[plane->id] = 0;
4108
		}
4109

4110
		plane_state->planar_slave = false;
4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123
	}

	if (!crtc_state->nv12_planes)
		return 0;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
		struct intel_plane_state *linked_state = NULL;

		if (plane->pipe != crtc->pipe ||
		    !(crtc_state->nv12_planes & BIT(plane->id)))
			continue;

		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4124
			if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137
				continue;

			if (crtc_state->active_planes & BIT(linked->id))
				continue;

			linked_state = intel_atomic_get_plane_state(state, linked);
			if (IS_ERR(linked_state))
				return PTR_ERR(linked_state);

			break;
		}

		if (!linked_state) {
4138 4139 4140
			drm_dbg_kms(&dev_priv->drm,
				    "Need %d free Y planes for planar YUV\n",
				    hweight8(crtc_state->nv12_planes));
4141 4142 4143 4144

			return -EINVAL;
		}

4145
		plane_state->planar_linked_plane = linked;
4146

4147 4148
		linked_state->planar_slave = true;
		linked_state->planar_linked_plane = plane;
4149
		crtc_state->enabled_planes |= BIT(linked->id);
4150
		crtc_state->active_planes |= BIT(linked->id);
4151
		crtc_state->update_planes |= BIT(linked->id);
4152 4153
		crtc_state->data_rate[linked->id] =
			crtc_state->data_rate_y[plane->id];
4154 4155
		crtc_state->rel_data_rate[linked->id] =
			crtc_state->rel_data_rate_y[plane->id];
4156 4157
		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
			    linked->base.name, plane->base.name);
4158 4159 4160 4161

		/* Copy parameters to slave plane */
		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
		linked_state->color_ctl = plane_state->color_ctl;
4162
		linked_state->view = plane_state->view;
4163
		linked_state->decrypt = plane_state->decrypt;
4164

4165
		intel_plane_copy_hw_state(linked_state, plane_state);
4166 4167 4168 4169
		linked_state->uapi.src = plane_state->uapi.src;
		linked_state->uapi.dst = plane_state->uapi.dst;

		if (icl_is_hdr_plane(dev_priv, plane->id)) {
4170
			if (linked->id == PLANE_7)
4171
				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4172
			else if (linked->id == PLANE_6)
4173
				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4174
			else if (linked->id == PLANE_5)
4175
				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4176
			else if (linked->id == PLANE_4)
4177
				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4178 4179 4180
			else
				MISSING_CASE(linked->id);
		}
4181 4182 4183 4184 4185
	}

	return 0;
}

4186 4187
static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
4188 4189
	const struct drm_display_mode *pipe_mode =
		&crtc_state->hw.pipe_mode;
4190
	int linetime_wm;
4191 4192 4193 4194

	if (!crtc_state->hw.enable)
		return 0;

4195 4196
	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
					pipe_mode->crtc_clock);
4197 4198

	return min(linetime_wm, 0x1ff);
4199 4200
}

4201 4202
static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
			       const struct intel_cdclk_state *cdclk_state)
4203
{
4204 4205
	const struct drm_display_mode *pipe_mode =
		&crtc_state->hw.pipe_mode;
4206
	int linetime_wm;
4207 4208 4209 4210

	if (!crtc_state->hw.enable)
		return 0;

4211
	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4212 4213 4214
					cdclk_state->logical.cdclk);

	return min(linetime_wm, 0x1ff);
4215 4216 4217 4218 4219 4220
}

static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
{
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4221 4222
	const struct drm_display_mode *pipe_mode =
		&crtc_state->hw.pipe_mode;
4223
	int linetime_wm;
4224 4225 4226 4227

	if (!crtc_state->hw.enable)
		return 0;

4228
	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4229 4230 4231
				   crtc_state->pixel_rate);

	/* Display WA #1135: BXT:ALL GLK:ALL */
4232
	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4233
	    skl_watermark_ipc_enabled(dev_priv))
4234 4235
		linetime_wm /= 2;

4236
	return min(linetime_wm, 0x1ff);
4237 4238
}

4239 4240 4241 4242 4243 4244 4245 4246
static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct intel_cdclk_state *cdclk_state;

4247
	if (DISPLAY_VER(dev_priv) >= 9)
4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264
		crtc_state->linetime = skl_linetime_wm(crtc_state);
	else
		crtc_state->linetime = hsw_linetime_wm(crtc_state);

	if (!hsw_crtc_supports_ips(crtc))
		return 0;

	cdclk_state = intel_atomic_get_cdclk_state(state);
	if (IS_ERR(cdclk_state))
		return PTR_ERR(cdclk_state);

	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
						       cdclk_state);

	return 0;
}

4265 4266
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
4267
{
4268 4269
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	struct intel_crtc_state *crtc_state =
4270 4271
		intel_atomic_get_new_crtc_state(state, crtc);
	int ret;
4272

4273
	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4274 4275
	    intel_crtc_needs_modeset(crtc_state) &&
	    !crtc_state->hw.active)
4276
		crtc_state->update_wm_post = true;
4277

4278
	if (intel_crtc_needs_modeset(crtc_state)) {
4279 4280 4281
		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
		if (ret)
			return ret;
4282 4283
	}

4284 4285 4286
	ret = intel_color_check(state, crtc);
	if (ret)
		return ret;
4287

4288 4289 4290 4291 4292
	ret = intel_compute_pipe_wm(state, crtc);
	if (ret) {
		drm_dbg_kms(&dev_priv->drm,
			    "Target pipe watermarks are invalid\n");
		return ret;
4293 4294
	}

4295 4296 4297 4298 4299 4300 4301 4302 4303 4304
	/*
	 * Calculate 'intermediate' watermarks that satisfy both the
	 * old state and the new state.  We can program these
	 * immediately.
	 */
	ret = intel_compute_intermediate_wm(state, crtc);
	if (ret) {
		drm_dbg_kms(&dev_priv->drm,
			    "No valid intermediate pipe watermarks are possible\n");
		return ret;
4305 4306
	}

4307
	if (DISPLAY_VER(dev_priv) >= 9) {
4308
		if (intel_crtc_needs_modeset(crtc_state) ||
4309
		    intel_crtc_needs_fastset(crtc_state)) {
4310
			ret = skl_update_scaler_crtc(crtc_state);
4311 4312 4313 4314 4315
			if (ret)
				return ret;
		}

		ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4316 4317
		if (ret)
			return ret;
4318 4319
	}

4320
	if (HAS_IPS(dev_priv)) {
4321
		ret = hsw_ips_compute_config(state, crtc);
4322 4323 4324 4325
		if (ret)
			return ret;
	}

4326
	if (DISPLAY_VER(dev_priv) >= 9 ||
4327 4328 4329 4330
	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
		ret = hsw_compute_linetime_wm(state, crtc);
		if (ret)
			return ret;
4331

4332 4333
	}

4334 4335 4336
	ret = intel_psr2_sel_fetch_update(state, crtc);
	if (ret)
		return ret;
4337

4338
	return 0;
4339 4340
}

4341
static int
4342
compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4343
		      struct intel_crtc_state *crtc_state)
4344
{
4345
	struct drm_connector *connector = conn_state->connector;
4346
	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4347
	const struct drm_display_info *info = &connector->display_info;
4348
	int bpp;
4349

4350 4351 4352 4353 4354 4355 4356 4357 4358 4359
	switch (conn_state->max_bpc) {
	case 6 ... 7:
		bpp = 6 * 3;
		break;
	case 8 ... 9:
		bpp = 8 * 3;
		break;
	case 10 ... 11:
		bpp = 10 * 3;
		break;
4360
	case 12 ... 16:
4361 4362 4363
		bpp = 12 * 3;
		break;
	default:
4364
		MISSING_CASE(conn_state->max_bpc);
4365
		return -EINVAL;
4366 4367
	}

4368
	if (bpp < crtc_state->pipe_bpp) {
4369
		drm_dbg_kms(&i915->drm,
4370 4371
			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4372 4373 4374
			    connector->base.id, connector->name,
			    bpp, 3 * info->bpc,
			    3 * conn_state->max_requested_bpc,
4375
			    crtc_state->pipe_bpp);
4376

4377
		crtc_state->pipe_bpp = bpp;
4378
	}
4379

4380
	return 0;
4381 4382
}

4383
static int
4384 4385
compute_baseline_pipe_bpp(struct intel_atomic_state *state,
			  struct intel_crtc *crtc)
4386
{
4387
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4388
	struct intel_crtc_state *crtc_state =
4389
		intel_atomic_get_new_crtc_state(state, crtc);
4390 4391
	struct drm_connector *connector;
	struct drm_connector_state *connector_state;
4392
	int bpp, i;
4393

4394 4395
	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
	    IS_CHERRYVIEW(dev_priv)))
4396
		bpp = 10*3;
4397
	else if (DISPLAY_VER(dev_priv) >= 5)
4398 4399 4400 4401
		bpp = 12*3;
	else
		bpp = 8*3;

4402
	crtc_state->pipe_bpp = bpp;
4403

4404
	/* Clamp display bpp to connector max bpp */
4405
	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4406 4407
		int ret;

4408
		if (connector_state->crtc != &crtc->base)
4409 4410
			continue;

4411
		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4412 4413
		if (ret)
			return ret;
4414 4415
	}

4416
	return 0;
4417 4418
}

4419
static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4420
{
4421
	struct drm_device *dev = state->base.dev;
4422
	struct drm_connector *connector;
4423
	struct drm_connector_list_iter conn_iter;
4424
	unsigned int used_ports = 0;
4425
	unsigned int used_mst_ports = 0;
4426
	bool ret = true;
4427

4428 4429 4430 4431 4432 4433
	/*
	 * We're going to peek into connector->state,
	 * hence connection_mutex must be held.
	 */
	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);

4434 4435 4436 4437 4438
	/*
	 * Walk the connector list instead of the encoder
	 * list to detect the problem on ddi platforms
	 * where there's just one encoder per digital port.
	 */
4439 4440
	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
4441 4442 4443
		struct drm_connector_state *connector_state;
		struct intel_encoder *encoder;

4444 4445 4446
		connector_state =
			drm_atomic_get_new_connector_state(&state->base,
							   connector);
4447 4448 4449
		if (!connector_state)
			connector_state = connector->state;

4450
		if (!connector_state->best_encoder)
4451 4452
			continue;

4453 4454
		encoder = to_intel_encoder(connector_state->best_encoder);

4455
		drm_WARN_ON(dev, !connector_state->crtc);
4456 4457

		switch (encoder->type) {
4458
		case INTEL_OUTPUT_DDI:
4459
			if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4460
				break;
4461
			fallthrough;
4462
		case INTEL_OUTPUT_DP:
4463 4464 4465
		case INTEL_OUTPUT_HDMI:
		case INTEL_OUTPUT_EDP:
			/* the same port mustn't appear more than once */
4466
			if (used_ports & BIT(encoder->port))
4467
				ret = false;
4468

4469
			used_ports |= BIT(encoder->port);
4470 4471 4472
			break;
		case INTEL_OUTPUT_DP_MST:
			used_mst_ports |=
4473
				1 << encoder->port;
4474
			break;
4475 4476 4477 4478
		default:
			break;
		}
	}
4479
	drm_connector_list_iter_end(&conn_iter);
4480

4481 4482 4483 4484
	/* can't mix MST and SST/HDMI on the same port */
	if (used_ports & used_mst_ports)
		return false;

4485
	return ret;
4486 4487
}

4488
static void
4489
intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4490
					   struct intel_crtc *crtc)
4491
{
4492 4493
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
4494

4495
	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4496

4497 4498 4499 4500 4501 4502
	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
				  crtc_state->uapi.degamma_lut);
	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
				  crtc_state->uapi.gamma_lut);
	drm_property_replace_blob(&crtc_state->hw.ctm,
				  crtc_state->uapi.ctm);
4503 4504 4505
}

static void
4506 4507
intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
					 struct intel_crtc *crtc)
4508
{
4509 4510 4511
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);

4512
	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4513

4514 4515
	crtc_state->hw.enable = crtc_state->uapi.enable;
	crtc_state->hw.active = crtc_state->uapi.active;
4516 4517 4518 4519
	drm_mode_copy(&crtc_state->hw.mode,
		      &crtc_state->uapi.mode);
	drm_mode_copy(&crtc_state->hw.adjusted_mode,
		      &crtc_state->uapi.adjusted_mode);
4520
	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4521

4522
	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4523 4524
}

4525
static void
4526
copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4527
				 struct intel_crtc *secondary_crtc)
4528
{
4529 4530 4531 4532 4533
	struct intel_crtc_state *secondary_crtc_state =
		intel_atomic_get_new_crtc_state(state, secondary_crtc);
	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
	const struct intel_crtc_state *primary_crtc_state =
		intel_atomic_get_new_crtc_state(state, primary_crtc);
4534

4535 4536 4537 4538 4539 4540
	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,
				  primary_crtc_state->hw.degamma_lut);
	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,
				  primary_crtc_state->hw.gamma_lut);
	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
				  primary_crtc_state->hw.ctm);
4541

4542
	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4543 4544
}

4545
static int
4546
copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4547
			       struct intel_crtc *secondary_crtc)
4548
{
4549 4550 4551 4552 4553
	struct intel_crtc_state *secondary_crtc_state =
		intel_atomic_get_new_crtc_state(state, secondary_crtc);
	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
	const struct intel_crtc_state *primary_crtc_state =
		intel_atomic_get_new_crtc_state(state, primary_crtc);
4554 4555
	struct intel_crtc_state *saved_state;

4556 4557
	WARN_ON(primary_crtc_state->joiner_pipes !=
		secondary_crtc_state->joiner_pipes);
4558

4559
	saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4560 4561 4562
	if (!saved_state)
		return -ENOMEM;

4563
	/* preserve some things from the slave's original crtc state */
4564 4565 4566 4567 4568 4569 4570 4571 4572
	saved_state->uapi = secondary_crtc_state->uapi;
	saved_state->scaler_state = secondary_crtc_state->scaler_state;
	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;

	intel_crtc_free_hw_state(secondary_crtc_state);
	if (secondary_crtc_state->dp_tunnel_ref.tunnel)
		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);
	memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
4573 4574 4575
	kfree(saved_state);

	/* Re-init hw state */
4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598
	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
	drm_mode_copy(&secondary_crtc_state->hw.mode,
		      &primary_crtc_state->hw.mode);
	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,
		      &primary_crtc_state->hw.pipe_mode);
	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,
		      &primary_crtc_state->hw.adjusted_mode);
	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;

	if (primary_crtc_state->dp_tunnel_ref.tunnel)
		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,
				      &secondary_crtc_state->dp_tunnel_ref);

	copy_joiner_crtc_state_nomodeset(state, secondary_crtc);

	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;

	WARN_ON(primary_crtc_state->joiner_pipes !=
		secondary_crtc_state->joiner_pipes);
4599

4600 4601 4602
	return 0;
}

4603
static int
4604
intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4605
				 struct intel_crtc *crtc)
4606
{
4607 4608
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
4609
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4610 4611
	struct intel_crtc_state *saved_state;

4612
	saved_state = intel_crtc_state_alloc(crtc);
4613 4614
	if (!saved_state)
		return -ENOMEM;
4615

4616 4617 4618
	/* free the old crtc_state->hw members */
	intel_crtc_free_hw_state(crtc_state);

4619 4620
	intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);

4621 4622 4623 4624 4625
	/* FIXME: before the switch to atomic started, a new pipe_config was
	 * kzalloc'd. Code that depends on any field being zero should be
	 * fixed, so that the crtc_state can be safely duplicated. For now,
	 * only fields that are know to not cause problems are preserved. */

4626
	saved_state->uapi = crtc_state->uapi;
4627
	saved_state->inherited = crtc_state->inherited;
4628 4629 4630
	saved_state->scaler_state = crtc_state->scaler_state;
	saved_state->shared_dpll = crtc_state->shared_dpll;
	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4631 4632
	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
	       sizeof(saved_state->icl_port_dplls));
4633
	saved_state->crc_enabled = crtc_state->crc_enabled;
4634 4635
	if (IS_G4X(dev_priv) ||
	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4636
		saved_state->wm = crtc_state->wm;
4637

4638
	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4639
	kfree(saved_state);
4640

4641
	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4642

4643
	return 0;
4644 4645
}

4646
static int
4647
intel_modeset_pipe_config(struct intel_atomic_state *state,
4648 4649
			  struct intel_crtc *crtc,
			  const struct intel_link_bw_limits *limits)
4650
{
4651
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4652
	struct intel_crtc_state *crtc_state =
4653
		intel_atomic_get_new_crtc_state(state, crtc);
4654
	struct drm_connector *connector;
4655
	struct drm_connector_state *connector_state;
4656
	int pipe_src_w, pipe_src_h;
4657
	int base_bpp, ret, i;
4658

4659
	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4660

4661
	crtc_state->framestart_delay = 1;
4662

4663 4664 4665 4666 4667
	/*
	 * Sanitize sync polarity flags based on requested ones. If neither
	 * positive or negative polarity is requested, treat this as meaning
	 * negative polarity.
	 */
4668
	if (!(crtc_state->hw.adjusted_mode.flags &
4669
	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4670
		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4671

4672
	if (!(crtc_state->hw.adjusted_mode.flags &
4673
	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4674
		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4675

4676
	ret = compute_baseline_pipe_bpp(state, crtc);
4677 4678 4679
	if (ret)
		return ret;

4680
	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4681 4682
	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];

4683
	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
4684
		drm_dbg_kms(&i915->drm,
4685
			    "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4686
			    crtc->base.base.id, crtc->base.name,
4687
			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4688
		crtc_state->bw_constrained = true;
4689 4690
	}

4691
	base_bpp = crtc_state->pipe_bpp;
4692

4693 4694 4695 4696 4697 4698 4699 4700
	/*
	 * Determine the real pipe dimensions. Note that stereo modes can
	 * increase the actual pipe size due to the frame doubling and
	 * insertion of additional space for blanks between the frame. This
	 * is stored in the crtc timings. We use the requested mode to do this
	 * computation to clearly distinguish it from the adjusted mode, which
	 * can be changed by the connectors in the below retry loop.
	 */
4701
	drm_mode_get_hv_timing(&crtc_state->hw.mode,
4702
			       &pipe_src_w, &pipe_src_h);
4703
	drm_rect_init(&crtc_state->pipe_src, 0, 0,
4704
		      pipe_src_w, pipe_src_h);
4705

4706
	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4707 4708 4709
		struct intel_encoder *encoder =
			to_intel_encoder(connector_state->best_encoder);

4710
		if (connector_state->crtc != &crtc->base)
4711 4712
			continue;

4713
		if (!check_single_encoder_cloning(state, crtc, encoder)) {
4714
			drm_dbg_kms(&i915->drm,
4715 4716
				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
				    encoder->base.base.id, encoder->base.name);
4717
			return -EINVAL;
4718 4719
		}

4720 4721 4722 4723
		/*
		 * Determine output_types before calling the .compute_config()
		 * hooks so that the hooks can use this information safely.
		 */
4724
		if (encoder->compute_output_type)
4725 4726
			crtc_state->output_types |=
				BIT(encoder->compute_output_type(encoder, crtc_state,
4727 4728
								 connector_state));
		else
4729
			crtc_state->output_types |= BIT(encoder->type);
4730 4731
	}

4732
	/* Ensure the port clock defaults are reset when retrying. */
4733 4734
	crtc_state->port_clock = 0;
	crtc_state->pixel_multiplier = 1;
4735

4736
	/* Fill in default crtc timings, allow encoders to overwrite them. */
4737
	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4738
			      CRTC_STEREO_DOUBLE);
4739

4740 4741 4742
	/* Pass our mode to the connectors and the CRTC to give them a chance to
	 * adjust it according to limitations or connector properties, and also
	 * a chance to reject the mode entirely.
4743
	 */
4744
	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4745 4746 4747
		struct intel_encoder *encoder =
			to_intel_encoder(connector_state->best_encoder);

4748
		if (connector_state->crtc != &crtc->base)
4749
			continue;
4750

4751
		ret = encoder->compute_config(encoder, crtc_state,
4752
					      connector_state);
4753 4754
		if (ret == -EDEADLK)
			return ret;
4755
		if (ret < 0) {
4756 4757
			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
				    encoder->base.base.id, encoder->base.name, ret);
4758
			return ret;
4759
		}
4760
	}
4761

4762 4763
	/* Set default port clock if not overwritten by the encoder. Needs to be
	 * done afterwards in case the encoder adjusts the mode. */
4764 4765 4766
	if (!crtc_state->port_clock)
		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
			* crtc_state->pixel_multiplier;
4767

4768
	ret = intel_crtc_compute_config(state, crtc);
4769
	if (ret == -EDEADLK)
4770
		return ret;
4771
	if (ret < 0) {
4772 4773
		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
			    crtc->base.base.id, crtc->base.name, ret);
4774 4775
		return ret;
	}
4776

4777
	/* Dithering seems to not pass-through bits correctly when it should, so
4778 4779 4780
	 * only enable it on 6bpc panels and when its not a compliance
	 * test requesting 6bpc video pattern.
	 */
4781 4782
	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
		!crtc_state->dither_force_disable;
4783
	drm_dbg_kms(&i915->drm,
4784 4785
		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
		    crtc->base.base.id, crtc->base.name,
4786
		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4787

4788
	return 0;
4789
}
4790

4791
static int
4792 4793
intel_modeset_pipe_config_late(struct intel_atomic_state *state,
			       struct intel_crtc *crtc)
4794
{
4795 4796
	struct intel_crtc_state *crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819
	struct drm_connector_state *conn_state;
	struct drm_connector *connector;
	int i;

	for_each_new_connector_in_state(&state->base, connector,
					conn_state, i) {
		struct intel_encoder *encoder =
			to_intel_encoder(conn_state->best_encoder);
		int ret;

		if (conn_state->crtc != &crtc->base ||
		    !encoder->compute_config_late)
			continue;

		ret = encoder->compute_config_late(encoder, crtc_state,
						   conn_state);
		if (ret)
			return ret;
	}

	return 0;
}

4820
bool intel_fuzzy_clock_check(int clock1, int clock2)
4821
{
4822
	int diff;
4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837

	if (clock1 == clock2)
		return true;

	if (!clock1 || !clock2)
		return false;

	diff = abs(clock1 - clock2);

	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
		return true;

	return false;
}

4838 4839
static bool
intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4840
		       const struct intel_link_m_n *m2_n2)
4841 4842
{
	return m_n->tu == m2_n2->tu &&
4843 4844 4845 4846
		m_n->data_m == m2_n2->data_m &&
		m_n->data_n == m2_n2->data_n &&
		m_n->link_m == m2_n2->link_m &&
		m_n->link_n == m2_n2->link_n;
4847 4848
}

4849 4850 4851 4852 4853 4854 4855
static bool
intel_compare_infoframe(const union hdmi_infoframe *a,
			const union hdmi_infoframe *b)
{
	return memcmp(a, b, sizeof(*a)) == 0;
}

4856 4857 4858 4859
static bool
intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
			 const struct drm_dp_vsc_sdp *b)
{
4860 4861 4862 4863 4864
	return a->pixelformat == b->pixelformat &&
		a->colorimetry == b->colorimetry &&
		a->bpc == b->bpc &&
		a->dynamic_range == b->dynamic_range &&
		a->content_type == b->content_type;
4865 4866
}

4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877
static bool
intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
			const struct drm_dp_as_sdp *b)
{
	return a->vtotal == b->vtotal &&
		a->target_rr == b->target_rr &&
		a->duration_incr_ms == b->duration_incr_ms &&
		a->duration_decr_ms == b->duration_decr_ms &&
		a->mode == b->mode;
}

4878 4879 4880 4881 4882 4883
static bool
intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
{
	return memcmp(a, b, len) == 0;
}

4884 4885 4886
static void __printf(5, 6)
pipe_config_mismatch(struct drm_printer *p, bool fastset,
		     const struct intel_crtc *crtc,
4887 4888 4889 4890 4891 4892 4893 4894 4895 4896
		     const char *name, const char *format, ...)
{
	struct va_format vaf;
	va_list args;

	va_start(args, format);
	vaf.fmt = format;
	vaf.va = &args;

	if (fastset)
4897 4898
		drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
			   crtc->base.base.id, crtc->base.name, name, &vaf);
4899
	else
4900 4901
		drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n",
			   crtc->base.base.id, crtc->base.name, name, &vaf);
4902 4903 4904 4905

	va_end(args);
}

4906
static void
4907 4908
pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
			       const struct intel_crtc *crtc,
4909
			       const char *name,
4910 4911
			       const union hdmi_infoframe *a,
			       const union hdmi_infoframe *b)
4912
{
4913 4914
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
	const char *loglevel;
4915

4916
	if (fastset) {
4917
		if (!drm_debug_enabled(DRM_UT_KMS))
4918 4919
			return;

4920
		loglevel = KERN_DEBUG;
4921
	} else {
4922
		loglevel = KERN_ERR;
4923
	}
4924

4925
	pipe_config_mismatch(p, fastset, crtc, name, "infoframe");
4926

4927
	drm_printf(p, "expected:\n");
4928
	hdmi_infoframe_log(loglevel, i915->drm.dev, a);
4929
	drm_printf(p, "found:\n");
4930
	hdmi_infoframe_log(loglevel, i915->drm.dev, b);
4931 4932
}

4933
static void
4934 4935
pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
				const struct intel_crtc *crtc,
4936
				const char *name,
4937 4938 4939
				const struct drm_dp_vsc_sdp *a,
				const struct drm_dp_vsc_sdp *b)
{
4940
	pipe_config_mismatch(p, fastset, crtc, name, "dp sdp");
4941

4942 4943 4944 4945
	drm_printf(p, "expected:\n");
	drm_dp_vsc_sdp_log(p, a);
	drm_printf(p, "found:\n");
	drm_dp_vsc_sdp_log(p, b);
4946 4947
}

4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971
static void
pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
			       bool fastset, const char *name,
			       const struct drm_dp_as_sdp *a,
			       const struct drm_dp_as_sdp *b)
{
	struct drm_printer p;

	if (fastset) {
		p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);

		drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name);
	} else {
		p = drm_err_printer(&i915->drm, NULL);

		drm_printf(&p, "mismatch in %s dp sdp\n", name);
	}

	drm_printf(&p, "expected:\n");
	drm_dp_as_sdp_log(&p, a);
	drm_printf(&p, "found:\n");
	drm_dp_as_sdp_log(&p, b);
}

4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985
/* Returns the length up to and including the last differing byte */
static size_t
memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
{
	int i;

	for (i = len - 1; i >= 0; i--) {
		if (a[i] != b[i])
			return i + 1;
	}

	return 0;
}

4986
static void
4987 4988
pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
			    const struct intel_crtc *crtc,
4989
			    const char *name,
4990 4991
			    const u8 *a, const u8 *b, size_t len)
{
4992
	const char *loglevel;
4993

4994 4995 4996 4997
	if (fastset) {
		if (!drm_debug_enabled(DRM_UT_KMS))
			return;

4998
		loglevel = KERN_DEBUG;
4999
	} else {
5000
		loglevel = KERN_ERR;
5001
	}
5002

5003
	pipe_config_mismatch(p, fastset, crtc, name, "buffer");
5004

5005 5006 5007 5008 5009 5010 5011
	/* only dump up to the last difference */
	len = memcmp_diff_len(a, b, len);

	print_hex_dump(loglevel, "expected: ", DUMP_PREFIX_NONE,
		       16, 0, a, len, false);
	print_hex_dump(loglevel, "found: ", DUMP_PREFIX_NONE,
		       16, 0, b, len, false);
5012 5013
}

5014
static void
5015
pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
5016 5017 5018 5019
			 const struct intel_crtc *crtc,
			 const char *name,
			 const struct intel_dpll_hw_state *a,
			 const struct intel_dpll_hw_state *b)
5020
{
5021
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5022

5023
	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
5024

5025 5026 5027 5028
	drm_printf(p, "expected:\n");
	intel_dpll_dump_hw_state(i915, p, a);
	drm_printf(p, "found:\n");
	intel_dpll_dump_hw_state(i915, p, b);
5029 5030
}

5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048
static void
pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
			    const struct intel_crtc *crtc,
			    const char *name,
			    const struct intel_cx0pll_state *a,
			    const struct intel_cx0pll_state *b)
{
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
	char *chipname = a->use_c10 ? "C10" : "C20";

	pipe_config_mismatch(p, fastset, crtc, name, chipname);

	drm_printf(p, "expected:\n");
	intel_cx0pll_dump_hw_state(i915, a);
	drm_printf(p, "found:\n");
	intel_cx0pll_dump_hw_state(i915, b);
}

5049
bool
5050 5051
intel_pipe_config_compare(const struct intel_crtc_state *current_config,
			  const struct intel_crtc_state *pipe_config,
5052
			  bool fastset)
5053
{
5054 5055
	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5056
	struct drm_printer p;
5057
	bool ret = true;
5058

5059 5060 5061 5062 5063
	if (fastset)
		p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);
	else
		p = drm_err_printer(&dev_priv->drm, NULL);

5064
#define PIPE_CONF_CHECK_X(name) do { \
5065
	if (current_config->name != pipe_config->name) { \
5066 5067
		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
				 __stringify(name) " is bool");	\
5068
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5069
				     "(expected 0x%08x, found 0x%08x)", \
5070 5071
				     current_config->name, \
				     pipe_config->name); \
5072
		ret = false; \
5073 5074
	} \
} while (0)
5075

5076 5077
#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5078 5079
		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
				 __stringify(name) " is bool");	\
5080
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5081 5082 5083 5084 5085 5086 5087
				     "(expected 0x%08x, found 0x%08x)", \
				     current_config->name & (mask), \
				     pipe_config->name & (mask)); \
		ret = false; \
	} \
} while (0)

5088
#define PIPE_CONF_CHECK_I(name) do { \
5089
	if (current_config->name != pipe_config->name) { \
5090 5091
		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
				 __stringify(name) " is bool");	\
5092
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5093
				     "(expected %i, found %i)", \
5094 5095
				     current_config->name, \
				     pipe_config->name); \
5096
		ret = false; \
5097 5098
	} \
} while (0)
5099

5100 5101 5102 5103 5104 5105 5106 5107 5108 5109
#define PIPE_CONF_CHECK_LLI(name) do { \
	if (current_config->name != pipe_config->name) { \
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
				     "(expected %lli, found %lli)", \
				     current_config->name, \
				     pipe_config->name); \
		ret = false; \
	} \
} while (0)

5110
#define PIPE_CONF_CHECK_BOOL(name) do { \
5111
	if (current_config->name != pipe_config->name) { \
5112 5113
		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
				 __stringify(name) " is not bool");	\
5114
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5115
				     "(expected %s, found %s)", \
5116 5117
				     str_yes_no(current_config->name), \
				     str_yes_no(pipe_config->name)); \
5118
		ret = false; \
5119 5120
	} \
} while (0)
5121

5122
#define PIPE_CONF_CHECK_P(name) do { \
5123
	if (current_config->name != pipe_config->name) { \
5124
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5125
				     "(expected %p, found %p)", \
5126 5127
				     current_config->name, \
				     pipe_config->name); \
5128
		ret = false; \
5129 5130
	} \
} while (0)
5131

5132
#define PIPE_CONF_CHECK_M_N(name) do { \
5133
	if (!intel_compare_link_m_n(&current_config->name, \
5134
				    &pipe_config->name)) { \
5135
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5136 5137
				     "(expected tu %i data %i/%i link %i/%i, " \
				     "found tu %i, data %i/%i link %i/%i)", \
5138
				     current_config->name.tu, \
5139 5140
				     current_config->name.data_m, \
				     current_config->name.data_n, \
5141 5142 5143
				     current_config->name.link_m, \
				     current_config->name.link_n, \
				     pipe_config->name.tu, \
5144 5145
				     pipe_config->name.data_m, \
				     pipe_config->name.data_n, \
5146 5147
				     pipe_config->name.link_m, \
				     pipe_config->name.link_n); \
5148
		ret = false; \
5149 5150
	} \
} while (0)
5151

5152 5153 5154
#define PIPE_CONF_CHECK_PLL(name) do { \
	if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
					 &pipe_config->name)) { \
5155
		pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5156 5157 5158 5159 5160 5161
					 &current_config->name, \
					 &pipe_config->name); \
		ret = false; \
	} \
} while (0)

5162 5163 5164 5165 5166 5167 5168 5169 5170 5171
#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
					   &pipe_config->name)) { \
		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
					    &current_config->name, \
					    &pipe_config->name); \
		ret = false; \
	} \
} while (0)

5172
#define PIPE_CONF_CHECK_TIMINGS(name) do {     \
5173 5174 5175 5176 5177 5178 5179 5180 5181 5182
	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
	PIPE_CONF_CHECK_I(name.crtc_htotal); \
	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5183 5184 5185 5186
	if (!fastset || !pipe_config->update_lrr) { \
		PIPE_CONF_CHECK_I(name.crtc_vtotal); \
		PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
	} \
5187 5188
} while (0)

5189 5190 5191 5192 5193 5194 5195
#define PIPE_CONF_CHECK_RECT(name) do { \
	PIPE_CONF_CHECK_I(name.x1); \
	PIPE_CONF_CHECK_I(name.x2); \
	PIPE_CONF_CHECK_I(name.y1); \
	PIPE_CONF_CHECK_I(name.y2); \
} while (0)

5196
#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5197
	if ((current_config->name ^ pipe_config->name) & (mask)) { \
5198
		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5199
				     "(%x) (expected %i, found %i)", \
5200 5201 5202
				     (mask), \
				     current_config->name & (mask), \
				     pipe_config->name & (mask)); \
5203
		ret = false; \
5204 5205
	} \
} while (0)
5206

5207 5208 5209
#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
	if (!intel_compare_infoframe(&current_config->infoframes.name, \
				     &pipe_config->infoframes.name)) { \
5210
		pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5211 5212
					       &current_config->infoframes.name, \
					       &pipe_config->infoframes.name); \
5213 5214 5215 5216
		ret = false; \
	} \
} while (0)

5217
#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5218
	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5219
				      &pipe_config->infoframes.name)) { \
5220
		pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5221 5222 5223 5224 5225 5226
						&current_config->infoframes.name, \
						&pipe_config->infoframes.name); \
		ret = false; \
	} \
} while (0)

5227 5228 5229 5230 5231 5232 5233 5234 5235 5236
#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
				      &pipe_config->infoframes.name)) { \
		pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
						&current_config->infoframes.name, \
						&pipe_config->infoframes.name); \
		ret = false; \
	} \
} while (0)

5237 5238 5239 5240
#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5241
		pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5242 5243 5244 5245 5246 5247 5248
					    current_config->name, \
					    pipe_config->name, \
					    (len)); \
		ret = false; \
	} \
} while (0)

5249 5250 5251 5252 5253
#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
	if (current_config->gamma_mode == pipe_config->gamma_mode && \
	    !intel_color_lut_equal(current_config, \
				   current_config->lut, pipe_config->lut, \
				   is_pre_csc_lut)) {	\
5254
		pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5255 5256
				     "hw_state doesn't match sw_state"); \
		ret = false; \
5257 5258 5259
	} \
} while (0)

5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277
#define PIPE_CONF_CHECK_CSC(name) do { \
	PIPE_CONF_CHECK_X(name.preoff[0]); \
	PIPE_CONF_CHECK_X(name.preoff[1]); \
	PIPE_CONF_CHECK_X(name.preoff[2]); \
	PIPE_CONF_CHECK_X(name.coeff[0]); \
	PIPE_CONF_CHECK_X(name.coeff[1]); \
	PIPE_CONF_CHECK_X(name.coeff[2]); \
	PIPE_CONF_CHECK_X(name.coeff[3]); \
	PIPE_CONF_CHECK_X(name.coeff[4]); \
	PIPE_CONF_CHECK_X(name.coeff[5]); \
	PIPE_CONF_CHECK_X(name.coeff[6]); \
	PIPE_CONF_CHECK_X(name.coeff[7]); \
	PIPE_CONF_CHECK_X(name.coeff[8]); \
	PIPE_CONF_CHECK_X(name.postoff[0]); \
	PIPE_CONF_CHECK_X(name.postoff[1]); \
	PIPE_CONF_CHECK_X(name.postoff[2]); \
} while (0)

5278
#define PIPE_CONF_QUIRK(quirk) \
5279 5280
	((current_config->quirks | pipe_config->quirks) & (quirk))

5281 5282
	PIPE_CONF_CHECK_BOOL(hw.enable);
	PIPE_CONF_CHECK_BOOL(hw.active);
5283

5284
	PIPE_CONF_CHECK_I(cpu_transcoder);
5285
	PIPE_CONF_CHECK_I(mst_master_transcoder);
5286

5287
	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5288
	PIPE_CONF_CHECK_I(fdi_lanes);
5289
	PIPE_CONF_CHECK_M_N(fdi_m_n);
5290

5291
	PIPE_CONF_CHECK_I(lane_count);
5292
	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5293

5294
	if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5295
		if (!fastset || !pipe_config->update_m_n)
5296
			PIPE_CONF_CHECK_M_N(dp_m_n);
5297 5298 5299 5300
	} else {
		PIPE_CONF_CHECK_M_N(dp_m_n);
		PIPE_CONF_CHECK_M_N(dp_m2_n2);
	}
5301

5302
	PIPE_CONF_CHECK_X(output_types);
5303

5304
	PIPE_CONF_CHECK_I(framestart_delay);
5305
	PIPE_CONF_CHECK_I(msa_timing_delay);
5306

5307 5308
	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5309 5310 5311 5312 5313 5314 5315

	PIPE_CONF_CHECK_I(pixel_multiplier);

	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
			      DRM_MODE_FLAG_INTERLACE);

	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5316
		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5317 5318 5319 5320 5321 5322 5323
				      DRM_MODE_FLAG_PHSYNC);
		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
				      DRM_MODE_FLAG_NHSYNC);
		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
				      DRM_MODE_FLAG_PVSYNC);
		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
				      DRM_MODE_FLAG_NVSYNC);
5324 5325
	}

5326
	PIPE_CONF_CHECK_I(output_format);
5327
	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5328
	if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5329
	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5330
		PIPE_CONF_CHECK_BOOL(limited_color_range);
5331

5332 5333
	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5334
	PIPE_CONF_CHECK_BOOL(has_infoframe);
5335
	PIPE_CONF_CHECK_BOOL(enhanced_framing);
5336
	PIPE_CONF_CHECK_BOOL(fec_enable);
5337

5338 5339 5340 5341
	if (!fastset) {
		PIPE_CONF_CHECK_BOOL(has_audio);
		PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
	}
5342

5343
	PIPE_CONF_CHECK_X(gmch_pfit.control);
5344
	/* pfit ratios are autocomputed by the hw on gen4+ */
5345
	if (DISPLAY_VER(dev_priv) < 4)
5346
		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5347
	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5348

5349 5350 5351 5352
	/*
	 * Changing the EDP transcoder input mux
	 * (A_ONOFF vs. A_ON) requires a full modeset.
	 */
5353
	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5354

5355
	if (!fastset) {
5356
		PIPE_CONF_CHECK_RECT(pipe_src);
5357

5358
		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5359
		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5360

5361
		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5362
		PIPE_CONF_CHECK_I(pixel_rate);
5363 5364

		PIPE_CONF_CHECK_X(gamma_mode);
5365 5366 5367 5368
		if (IS_CHERRYVIEW(dev_priv))
			PIPE_CONF_CHECK_X(cgm_mode);
		else
			PIPE_CONF_CHECK_X(csc_mode);
5369
		PIPE_CONF_CHECK_BOOL(gamma_enable);
5370
		PIPE_CONF_CHECK_BOOL(csc_enable);
5371
		PIPE_CONF_CHECK_BOOL(wgc_enable);
5372

5373 5374 5375
		PIPE_CONF_CHECK_I(linetime);
		PIPE_CONF_CHECK_I(ips_linetime);

5376 5377
		PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
		PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5378

5379 5380
		PIPE_CONF_CHECK_CSC(csc);
		PIPE_CONF_CHECK_CSC(output_csc);
5381
	}
5382

5383 5384 5385 5386
	/*
	 * Panel replay has to be enabled before link training. PSR doesn't have
	 * this requirement -> check these only if using panel replay
	 */
5387 5388 5389
	if (current_config->active_planes &&
	    (current_config->has_panel_replay ||
	     pipe_config->has_panel_replay)) {
5390
		PIPE_CONF_CHECK_BOOL(has_psr);
5391
		PIPE_CONF_CHECK_BOOL(has_sel_update);
5392 5393 5394 5395 5396
		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
		PIPE_CONF_CHECK_BOOL(has_panel_replay);
	}

5397
	PIPE_CONF_CHECK_BOOL(double_wide);
5398

5399
	if (dev_priv->display.dpll.mgr)
5400
		PIPE_CONF_CHECK_P(shared_dpll);
5401

5402
	/* FIXME convert everything over the dpll_mgr */
5403 5404
	if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
		PIPE_CONF_CHECK_PLL(dpll_hw_state);
5405

5406 5407 5408 5409
	/* FIXME convert MTL+ platforms over to dpll_mgr */
	if (DISPLAY_VER(dev_priv) >= 14)
		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);

5410 5411
	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
	PIPE_CONF_CHECK_X(dsi_pll.div);
5412

5413 5414
	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
		PIPE_CONF_CHECK_I(pipe_bpp);
5415

5416
	if (!fastset || !pipe_config->update_m_n) {
5417 5418 5419
		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
	}
5420
	PIPE_CONF_CHECK_I(port_clock);
5421

5422
	PIPE_CONF_CHECK_I(min_voltage_level);
5423

5424
	if (current_config->has_psr || pipe_config->has_psr)
5425 5426 5427 5428 5429
		PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
					    ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
	else
		PIPE_CONF_CHECK_X(infoframes.enable);

5430 5431 5432 5433
	PIPE_CONF_CHECK_X(infoframes.gcp);
	PIPE_CONF_CHECK_INFOFRAME(avi);
	PIPE_CONF_CHECK_INFOFRAME(spd);
	PIPE_CONF_CHECK_INFOFRAME(hdmi);
5434
	PIPE_CONF_CHECK_INFOFRAME(drm);
5435
	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5436
	PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5437

5438
	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5439
	PIPE_CONF_CHECK_I(master_transcoder);
5440
	PIPE_CONF_CHECK_X(joiner_pipes);
5441

5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472
	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
	PIPE_CONF_CHECK_I(dsc.config.pic_width);
	PIPE_CONF_CHECK_I(dsc.config.pic_height);
	PIPE_CONF_CHECK_I(dsc.config.slice_width);
	PIPE_CONF_CHECK_I(dsc.config.slice_height);
	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
	PIPE_CONF_CHECK_I(dsc.config.final_offset);
	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);

5473 5474
	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
5475
	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5476

5477 5478 5479 5480
	PIPE_CONF_CHECK_BOOL(splitter.enable);
	PIPE_CONF_CHECK_I(splitter.link_count);
	PIPE_CONF_CHECK_I(splitter.pixel_overlap);

5481
	if (!fastset) {
5482
		PIPE_CONF_CHECK_BOOL(vrr.enable);
5483 5484 5485 5486 5487
		PIPE_CONF_CHECK_I(vrr.vmin);
		PIPE_CONF_CHECK_I(vrr.vmax);
		PIPE_CONF_CHECK_I(vrr.flipline);
		PIPE_CONF_CHECK_I(vrr.pipeline_full);
		PIPE_CONF_CHECK_I(vrr.guardband);
5488 5489
		PIPE_CONF_CHECK_I(vrr.vsync_start);
		PIPE_CONF_CHECK_I(vrr.vsync_end);
5490 5491
		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5492
		PIPE_CONF_CHECK_BOOL(cmrr.enable);
5493
	}
5494

5495
#undef PIPE_CONF_CHECK_X
5496
#undef PIPE_CONF_CHECK_I
5497
#undef PIPE_CONF_CHECK_LLI
5498
#undef PIPE_CONF_CHECK_BOOL
5499
#undef PIPE_CONF_CHECK_P
5500
#undef PIPE_CONF_CHECK_FLAGS
5501
#undef PIPE_CONF_CHECK_COLOR_LUT
5502
#undef PIPE_CONF_CHECK_TIMINGS
5503
#undef PIPE_CONF_CHECK_RECT
5504
#undef PIPE_CONF_QUIRK
5505

5506
	return ret;
5507 5508
}

5509 5510 5511 5512 5513 5514 5515 5516 5517
static void
intel_verify_planes(struct intel_atomic_state *state)
{
	struct intel_plane *plane;
	const struct intel_plane_state *plane_state;
	int i;

	for_each_new_intel_plane_in_state(state, plane,
					  plane_state, i)
5518
		assert_plane(plane, plane_state->planar_slave ||
5519
			     plane_state->uapi.visible);
5520 5521
}

5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537
static int intel_modeset_pipe(struct intel_atomic_state *state,
			      struct intel_crtc_state *crtc_state,
			      const char *reason)
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
	int ret;

	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
		    crtc->base.base.id, crtc->base.name, reason);

	ret = drm_atomic_add_affected_connectors(&state->base,
						 &crtc->base);
	if (ret)
		return ret;

5538 5539 5540 5541
	ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
	if (ret)
		return ret;

5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592
	ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
	if (ret)
		return ret;

	ret = intel_atomic_add_affected_planes(state, crtc);
	if (ret)
		return ret;

	crtc_state->uapi.mode_changed = true;

	return 0;
}

/**
 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
 * @state: intel atomic state
 * @reason: the reason for the full modeset
 * @mask: mask of pipes to modeset
 *
 * Add pipes in @mask to @state and force a full modeset on the enabled ones
 * due to the description in @reason.
 * This function can be called only before new plane states are computed.
 *
 * Returns 0 in case of success, negative error code otherwise.
 */
int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
				      const char *reason, u8 mask)
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	struct intel_crtc *crtc;

	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
		struct intel_crtc_state *crtc_state;
		int ret;

		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
		if (IS_ERR(crtc_state))
			return PTR_ERR(crtc_state);

		if (!crtc_state->hw.enable ||
		    intel_crtc_needs_modeset(crtc_state))
			continue;

		ret = intel_modeset_pipe(state, crtc_state, reason);
		if (ret)
			return ret;
	}

	return 0;
}

5593 5594 5595 5596 5597 5598 5599 5600 5601 5602
static void
intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
{
	crtc_state->uapi.mode_changed = true;

	crtc_state->update_pipe = false;
	crtc_state->update_m_n = false;
	crtc_state->update_lrr = false;
}

5603
/**
5604
 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5605 5606 5607 5608 5609 5610 5611 5612 5613
 * @state: intel atomic state
 * @reason: the reason for the full modeset
 *
 * Add all pipes to @state and force a full modeset on the active ones due to
 * the description in @reason.
 * This function can be called only after new plane states are computed already.
 *
 * Returns 0 in case of success, negative error code otherwise.
 */
5614 5615
int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
				 const char *reason)
5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_crtc *crtc;

	for_each_intel_crtc(&dev_priv->drm, crtc) {
		struct intel_crtc_state *crtc_state;
		int ret;

		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
		if (IS_ERR(crtc_state))
			return PTR_ERR(crtc_state);

		if (!crtc_state->hw.active ||
5629
		    intel_crtc_needs_modeset(crtc_state))
5630 5631
			continue;

5632 5633 5634
		ret = intel_modeset_pipe(state, crtc_state, reason);
		if (ret)
			return ret;
5635

5636 5637
		intel_crtc_flag_modeset(crtc_state);

5638
		crtc_state->update_planes |= crtc_state->active_planes;
5639 5640
		crtc_state->async_flip_planes = 0;
		crtc_state->do_async_flip = false;
5641 5642 5643 5644 5645
	}

	return 0;
}

5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679
int intel_modeset_commit_pipes(struct drm_i915_private *i915,
			       u8 pipe_mask,
			       struct drm_modeset_acquire_ctx *ctx)
{
	struct drm_atomic_state *state;
	struct intel_crtc *crtc;
	int ret;

	state = drm_atomic_state_alloc(&i915->drm);
	if (!state)
		return -ENOMEM;

	state->acquire_ctx = ctx;
	to_intel_atomic_state(state)->internal = true;

	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
		struct intel_crtc_state *crtc_state =
			intel_atomic_get_crtc_state(state, crtc);

		if (IS_ERR(crtc_state)) {
			ret = PTR_ERR(crtc_state);
			goto out;
		}

		crtc_state->uapi.connectors_changed = true;
	}

	ret = drm_atomic_commit(state);
out:
	drm_atomic_state_put(state);

	return ret;
}

5680 5681 5682 5683 5684 5685
/*
 * This implements the workaround described in the "notes" section of the mode
 * set sequence documentation. When going from no pipes or single pipe to
 * multiple pipes, and planes are enabled after the pipe, we need to wait at
 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
 */
5686
static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5687
{
5688 5689
	struct intel_crtc_state *crtc_state;
	struct intel_crtc *crtc;
5690 5691 5692 5693 5694 5695
	struct intel_crtc_state *first_crtc_state = NULL;
	struct intel_crtc_state *other_crtc_state = NULL;
	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
	int i;

	/* look at all crtc's that are going to be enabled in during modeset */
5696
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5697
		if (!crtc_state->hw.active ||
5698
		    !intel_crtc_needs_modeset(crtc_state))
5699 5700 5701
			continue;

		if (first_crtc_state) {
5702
			other_crtc_state = crtc_state;
5703 5704
			break;
		} else {
5705 5706
			first_crtc_state = crtc_state;
			first_pipe = crtc->pipe;
5707 5708 5709 5710 5711 5712 5713 5714
		}
	}

	/* No workaround needed? */
	if (!first_crtc_state)
		return 0;

	/* w/a possibly needed, check how many crtc's are already enabled. */
5715 5716 5717 5718
	for_each_intel_crtc(state->base.dev, crtc) {
		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
		if (IS_ERR(crtc_state))
			return PTR_ERR(crtc_state);
5719

5720
		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5721

5722
		if (!crtc_state->hw.active ||
5723
		    intel_crtc_needs_modeset(crtc_state))
5724 5725 5726 5727 5728 5729
			continue;

		/* 2 or more enabled crtcs means no need for w/a */
		if (enabled_pipe != INVALID_PIPE)
			return 0;

5730
		enabled_pipe = crtc->pipe;
5731 5732 5733 5734 5735 5736 5737 5738 5739 5740
	}

	if (enabled_pipe != INVALID_PIPE)
		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
	else if (other_crtc_state)
		other_crtc_state->hsw_workaround_pipe = first_pipe;

	return 0;
}

5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757
u8 intel_calc_active_pipes(struct intel_atomic_state *state,
			   u8 active_pipes)
{
	const struct intel_crtc_state *crtc_state;
	struct intel_crtc *crtc;
	int i;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
		if (crtc_state->hw.active)
			active_pipes |= BIT(crtc->pipe);
		else
			active_pipes &= ~BIT(crtc->pipe);
	}

	return active_pipes;
}

5758
static int intel_modeset_checks(struct intel_atomic_state *state)
5759
{
5760
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5761

5762
	state->modeset = true;
5763

5764
	if (IS_HASWELL(dev_priv))
5765
		return hsw_mode_set_planes_workaround(state);
5766

5767
	return 0;
5768 5769
}

5770
static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5771 5772
				     struct intel_crtc_state *new_crtc_state)
{
5773 5774
	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5775

5776 5777 5778 5779
	/* only allow LRR when the timings stay within the VRR range */
	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
		new_crtc_state->update_lrr = false;

5780
	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5781 5782
		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
			    crtc->base.base.id, crtc->base.name);
5783 5784
	else
		new_crtc_state->uapi.mode_changed = false;
5785

5786
	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5787
				   &new_crtc_state->dp_m_n))
5788
		new_crtc_state->update_m_n = false;
5789

5790
	if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5791 5792 5793
	     old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
		new_crtc_state->update_lrr = false;

5794 5795 5796
	if (intel_crtc_needs_modeset(new_crtc_state))
		intel_crtc_flag_modeset(new_crtc_state);
	else
5797
		new_crtc_state->update_pipe = true;
5798
}
5799

5800 5801 5802
static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
					  struct intel_crtc *crtc,
					  u8 plane_ids_mask)
5803
{
5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_plane *plane;

	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
		struct intel_plane_state *plane_state;

		if ((plane_ids_mask & BIT(plane->id)) == 0)
			continue;

		plane_state = intel_atomic_get_plane_state(state, plane);
		if (IS_ERR(plane_state))
			return PTR_ERR(plane_state);
	}

	return 0;
}

5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833
int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
				     struct intel_crtc *crtc)
{
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);

	return intel_crtc_add_planes_to_state(state, crtc,
					      old_crtc_state->enabled_planes |
					      new_crtc_state->enabled_planes);
}

5834 5835 5836 5837 5838
static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
{
	/* See {hsw,vlv,ivb}_plane_ratio() */
	return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
		IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5839
		IS_IVYBRIDGE(dev_priv);
5840 5841
}

5842 5843 5844
static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state,
					struct intel_crtc *crtc,
					struct intel_crtc *other)
5845
{
5846
	const struct intel_plane_state __maybe_unused *plane_state;
5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858
	struct intel_plane *plane;
	u8 plane_ids = 0;
	int i;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
		if (plane->pipe == crtc->pipe)
			plane_ids |= BIT(plane->id);
	}

	return intel_crtc_add_planes_to_state(state, other, plane_ids);
}

5859
static int intel_joiner_add_affected_planes(struct intel_atomic_state *state)
5860
{
5861
	struct drm_i915_private *i915 = to_i915(state->base.dev);
5862 5863 5864 5865 5866
	const struct intel_crtc_state *crtc_state;
	struct intel_crtc *crtc;
	int i;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5867
		struct intel_crtc *other;
5868

5869
		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5870
						 crtc_state->joiner_pipes) {
5871
			int ret;
5872

5873 5874 5875
			if (crtc == other)
				continue;

5876
			ret = intel_crtc_add_joiner_planes(state, crtc, other);
5877 5878 5879
			if (ret)
				return ret;
		}
5880 5881 5882 5883 5884
	}

	return 0;
}

5885
static int intel_atomic_check_planes(struct intel_atomic_state *state)
5886 5887 5888
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5889
	struct intel_plane_state __maybe_unused *plane_state;
5890
	struct intel_plane *plane;
5891
	struct intel_crtc *crtc;
5892 5893
	int i, ret;

5894 5895 5896 5897
	ret = icl_add_linked_planes(state);
	if (ret)
		return ret;

5898
	ret = intel_joiner_add_affected_planes(state);
5899 5900 5901
	if (ret)
		return ret;

5902 5903 5904
	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
		ret = intel_plane_atomic_check(state, plane);
		if (ret) {
5905 5906 5907
			drm_dbg_atomic(&dev_priv->drm,
				       "[PLANE:%d:%s] atomic driver check failed\n",
				       plane->base.base.id, plane->base.name);
5908 5909 5910 5911
			return ret;
		}
	}

5912 5913 5914 5915
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
		u8 old_active_planes, new_active_planes;

5916
		ret = icl_check_nv12_planes(state, crtc);
5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930
		if (ret)
			return ret;

		/*
		 * On some platforms the number of active planes affects
		 * the planes' minimum cdclk calculation. Add such planes
		 * to the state before we compute the minimum cdclk.
		 */
		if (!active_planes_affects_min_cdclk(dev_priv))
			continue;

		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);

5931
		if (hweight8(old_active_planes) == hweight8(new_active_planes))
5932 5933 5934 5935 5936 5937 5938
			continue;

		ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
		if (ret)
			return ret;
	}

5939 5940 5941
	return 0;
}

5942 5943
static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
{
5944
	struct intel_crtc_state __maybe_unused *crtc_state;
5945 5946 5947 5948
	struct intel_crtc *crtc;
	int i;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5949
		struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5950 5951 5952
		int ret;

		ret = intel_crtc_atomic_check(state, crtc);
5953
		if (ret) {
5954 5955 5956
			drm_dbg_atomic(&i915->drm,
				       "[CRTC:%d:%s] atomic driver check failed\n",
				       crtc->base.base.id, crtc->base.name);
5957 5958 5959 5960 5961 5962 5963
			return ret;
		}
	}

	return 0;
}

5964 5965
static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
					       u8 transcoders)
5966
{
5967
	const struct intel_crtc_state *new_crtc_state;
5968 5969 5970
	struct intel_crtc *crtc;
	int i;

5971 5972 5973
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (new_crtc_state->hw.enable &&
		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5974
		    intel_crtc_needs_modeset(new_crtc_state))
5975 5976
			return true;
	}
5977 5978 5979 5980

	return false;
}

5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997
static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
				     u8 pipes)
{
	const struct intel_crtc_state *new_crtc_state;
	struct intel_crtc *crtc;
	int i;

	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (new_crtc_state->hw.enable &&
		    pipes & BIT(crtc->pipe) &&
		    intel_crtc_needs_modeset(new_crtc_state))
			return true;
	}

	return false;
}

5998
static int intel_atomic_check_joiner(struct intel_atomic_state *state,
5999
				     struct intel_crtc *primary_crtc)
6000
{
6001
	struct drm_i915_private *i915 = to_i915(state->base.dev);
6002 6003 6004
	struct intel_crtc_state *primary_crtc_state =
		intel_atomic_get_new_crtc_state(state, primary_crtc);
	struct intel_crtc *secondary_crtc;
6005

6006
	if (!primary_crtc_state->joiner_pipes)
6007 6008
		return 0;

6009 6010
	/* sanity check */
	if (drm_WARN_ON(&i915->drm,
6011
			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
6012
		return -EINVAL;
6013

6014
	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {
6015
		drm_dbg_kms(&i915->drm,
6016
			    "[CRTC:%d:%s] Cannot act as joiner primary "
6017
			    "(need 0x%x as pipes, only 0x%x possible)\n",
6018 6019
			    primary_crtc->base.base.id, primary_crtc->base.name,
			    primary_crtc_state->joiner_pipes, joiner_pipes(i915));
6020 6021 6022
		return -EINVAL;
	}

6023 6024 6025
	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
		struct intel_crtc_state *secondary_crtc_state;
6026
		int ret;
6027

6028 6029 6030
		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);
		if (IS_ERR(secondary_crtc_state))
			return PTR_ERR(secondary_crtc_state);
6031

6032 6033
		/* primary being enabled, secondary was already configured? */
		if (secondary_crtc_state->uapi.enable) {
6034
			drm_dbg_kms(&i915->drm,
6035
				    "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
6036
				    "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
6037 6038
				    secondary_crtc->base.base.id, secondary_crtc->base.name,
				    primary_crtc->base.base.id, primary_crtc->base.name);
6039 6040
			return -EINVAL;
		}
6041

6042
		/*
6043 6044
		 * The state copy logic assumes the primary crtc gets processed
		 * before the secondary crtc during the main compute_config loop.
6045
		 * This works because the crtcs are created in pipe order,
6046
		 * and the hardware requires primary pipe < secondary pipe as well.
6047 6048
		 * Should that change we need to rethink the logic.
		 */
6049 6050
		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
			    drm_crtc_index(&secondary_crtc->base)))
6051
			return -EINVAL;
6052

6053
		drm_dbg_kms(&i915->drm,
6054 6055 6056
			    "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
			    secondary_crtc->base.base.id, secondary_crtc->base.name,
			    primary_crtc->base.base.id, primary_crtc->base.name);
6057

6058 6059
		secondary_crtc_state->joiner_pipes =
			primary_crtc_state->joiner_pipes;
6060

6061
		ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
6062 6063 6064
		if (ret)
			return ret;
	}
6065

6066
	return 0;
6067 6068
}

6069 6070
static void kill_joiner_secondaries(struct intel_atomic_state *state,
				    struct intel_crtc *primary_crtc)
6071
{
6072
	struct drm_i915_private *i915 = to_i915(state->base.dev);
6073 6074 6075
	struct intel_crtc_state *primary_crtc_state =
		intel_atomic_get_new_crtc_state(state, primary_crtc);
	struct intel_crtc *secondary_crtc;
6076

6077 6078 6079 6080
	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
		struct intel_crtc_state *secondary_crtc_state =
			intel_atomic_get_new_crtc_state(state, secondary_crtc);
6081

6082
		secondary_crtc_state->joiner_pipes = 0;
6083

6084
		intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc);
6085 6086
	}

6087
	primary_crtc_state->joiner_pipes = 0;
6088 6089
}

6090 6091 6092 6093 6094 6095 6096 6097
/**
 * DOC: asynchronous flip implementation
 *
 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
 * Correspondingly, support is currently added for primary plane only.
 *
 * Async flip can only change the plane surface address, so anything else
6098
 * changing is rejected from the intel_async_flip_check_hw() function.
6099
 * Once this check is cleared, flip done interrupt is enabled using
6100
 * the intel_crtc_enable_flip_done() function.
6101 6102 6103 6104 6105 6106 6107
 *
 * As soon as the surface address register is written, flip done interrupt is
 * generated and the requested events are sent to the usersapce in the interrupt
 * handler itself. The timestamp and sequence sent during the flip done event
 * correspond to the last vblank and have no relation to the actual time when
 * the flip done event was sent.
 */
6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135
static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
				       struct intel_crtc *crtc)
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
	const struct intel_plane_state *old_plane_state;
	struct intel_plane_state *new_plane_state;
	struct intel_plane *plane;
	int i;

	if (!new_crtc_state->uapi.async_flip)
		return 0;

	if (!new_crtc_state->uapi.active) {
		drm_dbg_kms(&i915->drm,
			    "[CRTC:%d:%s] not active\n",
			    crtc->base.base.id, crtc->base.name);
		return -EINVAL;
	}

	if (intel_crtc_needs_modeset(new_crtc_state)) {
		drm_dbg_kms(&i915->drm,
			    "[CRTC:%d:%s] modeset required\n",
			    crtc->base.base.id, crtc->base.name);
		return -EINVAL;
	}

6136
	/*
6137
	 * FIXME: joiner+async flip is busted currently.
6138 6139
	 * Remove this check once the issues are fixed.
	 */
6140
	if (new_crtc_state->joiner_pipes) {
6141
		drm_dbg_kms(&i915->drm,
6142
			    "[CRTC:%d:%s] async flip disallowed with joiner\n",
6143 6144 6145 6146
			    crtc->base.base.id, crtc->base.name);
		return -EINVAL;
	}

6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177
	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
					     new_plane_state, i) {
		if (plane->pipe != crtc->pipe)
			continue;

		/*
		 * TODO: Async flip is only supported through the page flip IOCTL
		 * as of now. So support currently added for primary plane only.
		 * Support for other planes on platforms on which supports
		 * this(vlv/chv and icl+) should be added when async flip is
		 * enabled in the atomic IOCTL path.
		 */
		if (!plane->async_flip) {
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] async flip not supported\n",
				    plane->base.base.id, plane->base.name);
			return -EINVAL;
		}

		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] no old or new framebuffer\n",
				    plane->base.base.id, plane->base.name);
			return -EINVAL;
		}
	}

	return 0;
}

static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6178 6179 6180 6181 6182 6183 6184
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
	const struct intel_plane_state *new_plane_state, *old_plane_state;
	struct intel_plane *plane;
	int i;

6185 6186
	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6187

6188 6189 6190
	if (!new_crtc_state->uapi.async_flip)
		return 0;

6191 6192 6193 6194
	if (!new_crtc_state->hw.active) {
		drm_dbg_kms(&i915->drm,
			    "[CRTC:%d:%s] not active\n",
			    crtc->base.base.id, crtc->base.name);
6195 6196 6197
		return -EINVAL;
	}

6198 6199 6200 6201
	if (intel_crtc_needs_modeset(new_crtc_state)) {
		drm_dbg_kms(&i915->drm,
			    "[CRTC:%d:%s] modeset required\n",
			    crtc->base.base.id, crtc->base.name);
6202 6203
		return -EINVAL;
	}
6204

6205 6206
	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
		drm_dbg_kms(&i915->drm,
6207 6208
			    "[CRTC:%d:%s] Active planes cannot be in async flip\n",
			    crtc->base.base.id, crtc->base.name);
6209
		return -EINVAL;
6210 6211 6212 6213
	}

	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
					     new_plane_state, i) {
6214 6215 6216
		if (plane->pipe != crtc->pipe)
			continue;

6217
		/*
6218 6219 6220
		 * Only async flip capable planes should be in the state
		 * if we're really about to ask the hardware to perform
		 * an async flip. We should never get this far otherwise.
6221
		 */
6222 6223
		if (drm_WARN_ON(&i915->drm,
				new_crtc_state->do_async_flip && !plane->async_flip))
6224 6225
			return -EINVAL;

6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236
		/*
		 * Only check async flip capable planes other planes
		 * may be involved in the initial commit due to
		 * the wm0/ddb optimization.
		 *
		 * TODO maybe should track which planes actually
		 * were requested to do the async flip...
		 */
		if (!plane->async_flip)
			continue;

6237 6238
		/*
		 * FIXME: This check is kept generic for all platforms.
6239
		 * Need to verify this for all gen9 platforms to enable
6240 6241 6242
		 * this selectively if required.
		 */
		switch (new_plane_state->hw.fb->modifier) {
6243 6244 6245 6246 6247 6248 6249 6250 6251
		case DRM_FORMAT_MOD_LINEAR:
			/*
			 * FIXME: Async on Linear buffer is supported on ICL as
			 * but with additional alignment and fbc restrictions
			 * need to be taken care of. These aren't applicable for
			 * gen12+.
			 */
			if (DISPLAY_VER(i915) < 12) {
				drm_dbg_kms(&i915->drm,
6252 6253 6254
					    "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
					    plane->base.base.id, plane->base.name,
					    new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6255 6256
				return -EINVAL;
			}
6257
			break;
6258

6259 6260 6261
		case I915_FORMAT_MOD_X_TILED:
		case I915_FORMAT_MOD_Y_TILED:
		case I915_FORMAT_MOD_Yf_TILED:
6262
		case I915_FORMAT_MOD_4_TILED:
6263 6264
		case I915_FORMAT_MOD_4_TILED_BMG_CCS:
		case I915_FORMAT_MOD_4_TILED_LNL_CCS:
6265 6266 6267
			break;
		default:
			drm_dbg_kms(&i915->drm,
6268 6269 6270
				    "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
				    plane->base.base.id, plane->base.name,
				    new_plane_state->hw.fb->modifier);
6271 6272 6273
			return -EINVAL;
		}

6274 6275
		if (new_plane_state->hw.fb->format->num_planes > 1) {
			drm_dbg_kms(&i915->drm,
6276 6277
				    "[PLANE:%d:%s] Planar formats do not support async flips\n",
				    plane->base.base.id, plane->base.name);
6278 6279 6280
			return -EINVAL;
		}

6281 6282 6283 6284 6285 6286 6287
		/*
		 * We turn the first async flip request into a sync flip
		 * so that we can reconfigure the plane (eg. change modifier).
		 */
		if (!new_crtc_state->do_async_flip)
			continue;

6288 6289
		if (old_plane_state->view.color_plane[0].mapping_stride !=
		    new_plane_state->view.color_plane[0].mapping_stride) {
6290 6291 6292
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6293 6294 6295 6296 6297 6298
			return -EINVAL;
		}

		if (old_plane_state->hw.fb->modifier !=
		    new_plane_state->hw.fb->modifier) {
			drm_dbg_kms(&i915->drm,
6299 6300
				    "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6301 6302 6303 6304 6305 6306
			return -EINVAL;
		}

		if (old_plane_state->hw.fb->format !=
		    new_plane_state->hw.fb->format) {
			drm_dbg_kms(&i915->drm,
6307 6308
				    "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6309 6310 6311 6312 6313
			return -EINVAL;
		}

		if (old_plane_state->hw.rotation !=
		    new_plane_state->hw.rotation) {
6314 6315 6316
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6317 6318 6319 6320 6321 6322
			return -EINVAL;
		}

		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
			drm_dbg_kms(&i915->drm,
6323 6324
				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6325 6326 6327 6328
			return -EINVAL;
		}

		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6329 6330 6331
			drm_dbg_kms(&i915->drm,
				    "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6332 6333 6334 6335 6336 6337
			return -EINVAL;
		}

		if (old_plane_state->hw.pixel_blend_mode !=
		    new_plane_state->hw.pixel_blend_mode) {
			drm_dbg_kms(&i915->drm,
6338 6339
				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6340 6341 6342 6343 6344
			return -EINVAL;
		}

		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
			drm_dbg_kms(&i915->drm,
6345 6346
				    "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6347 6348 6349 6350
			return -EINVAL;
		}

		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6351 6352 6353
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6354 6355
			return -EINVAL;
		}
6356 6357

		/* plane decryption is allow to change only in synchronous flips */
6358 6359 6360 6361
		if (old_plane_state->decrypt != new_plane_state->decrypt) {
			drm_dbg_kms(&i915->drm,
				    "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
				    plane->base.base.id, plane->base.name);
6362
			return -EINVAL;
6363
		}
6364 6365 6366 6367 6368
	}

	return 0;
}

6369
static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6370
{
6371
	struct drm_i915_private *i915 = to_i915(state->base.dev);
6372
	struct intel_crtc_state *crtc_state;
6373
	struct intel_crtc *crtc;
6374 6375
	u8 affected_pipes = 0;
	u8 modeset_pipes = 0;
6376 6377 6378
	int i;

	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6379
		affected_pipes |= crtc_state->joiner_pipes;
6380
		if (intel_crtc_needs_modeset(crtc_state))
6381
			modeset_pipes |= crtc_state->joiner_pipes;
6382
	}
6383

6384 6385 6386 6387 6388
	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
		if (IS_ERR(crtc_state))
			return PTR_ERR(crtc_state);
	}
6389

6390 6391
	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
		int ret;
6392

6393
		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6394

6395
		crtc_state->uapi.mode_changed = true;
6396

6397
		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6398 6399 6400
		if (ret)
			return ret;

6401
		ret = intel_atomic_add_affected_planes(state, crtc);
6402 6403
		if (ret)
			return ret;
6404 6405
	}

6406
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6407
		/* Kill old joiner link, we may re-establish afterwards */
6408
		if (intel_crtc_needs_modeset(crtc_state) &&
6409 6410
		    intel_crtc_is_joiner_primary(crtc_state))
			kill_joiner_secondaries(state, crtc);
6411 6412
	}

6413 6414 6415
	return 0;
}

6416 6417 6418
static int intel_atomic_check_config(struct intel_atomic_state *state,
				     struct intel_link_bw_limits *limits,
				     enum pipe *failed_pipe)
6419 6420 6421 6422 6423 6424 6425
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	struct intel_crtc_state *new_crtc_state;
	struct intel_crtc *crtc;
	int ret;
	int i;

6426 6427
	*failed_pipe = INVALID_PIPE;

6428
	ret = intel_joiner_add_affected_crtcs(state);
6429 6430 6431
	if (ret)
		return ret;

6432 6433 6434 6435
	ret = intel_fdi_add_affected_crtcs(state);
	if (ret)
		return ret;

6436 6437
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (!intel_crtc_needs_modeset(new_crtc_state)) {
6438
			if (intel_crtc_is_joiner_secondary(new_crtc_state))
6439
				copy_joiner_crtc_state_nomodeset(state, crtc);
6440 6441 6442 6443 6444
			else
				intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
			continue;
		}

6445
		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6446 6447 6448 6449
			continue;

		ret = intel_crtc_prepare_cleared_state(state, crtc);
		if (ret)
6450
			goto fail;
6451 6452 6453 6454

		if (!new_crtc_state->hw.enable)
			continue;

6455
		ret = intel_modeset_pipe_config(state, crtc, limits);
6456
		if (ret)
6457 6458
			goto fail;
	}
6459

6460 6461 6462 6463
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (!intel_crtc_needs_modeset(new_crtc_state))
			continue;

6464
		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6465 6466 6467 6468 6469 6470
			continue;

		if (!new_crtc_state->hw.enable)
			continue;

		ret = intel_modeset_pipe_config_late(state, crtc);
6471
		if (ret)
6472
			goto fail;
6473 6474
	}

6475
fail:
6476 6477 6478
	if (ret)
		*failed_pipe = crtc->pipe;

6479 6480 6481
	return ret;
}

6482 6483 6484 6485 6486 6487
static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
{
	struct intel_link_bw_limits new_limits;
	struct intel_link_bw_limits old_limits;
	int ret;

6488
	intel_link_bw_init_limits(state, &new_limits);
6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519
	old_limits = new_limits;

	while (true) {
		enum pipe failed_pipe;

		ret = intel_atomic_check_config(state, &new_limits,
						&failed_pipe);
		if (ret) {
			/*
			 * The bpp limit for a pipe is below the minimum it supports, set the
			 * limit to the minimum and recalculate the config.
			 */
			if (ret == -EINVAL &&
			    intel_link_bw_set_bpp_limit_for_pipe(state,
								 &old_limits,
								 &new_limits,
								 failed_pipe))
				continue;

			break;
		}

		old_limits = new_limits;

		ret = intel_link_bw_atomic_check(state, &new_limits);
		if (ret != -EAGAIN)
			break;
	}

	return ret;
}
6520 6521 6522
/**
 * intel_atomic_check - validate state object
 * @dev: drm device
6523
 * @_state: state to validate
6524
 */
6525 6526
int intel_atomic_check(struct drm_device *dev,
		       struct drm_atomic_state *_state)
6527
{
6528
	struct drm_i915_private *dev_priv = to_i915(dev);
6529 6530 6531
	struct intel_atomic_state *state = to_intel_atomic_state(_state);
	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
	struct intel_crtc *crtc;
6532
	int ret, i;
6533
	bool any_ms = false;
6534

6535 6536 6537
	if (!intel_display_driver_check_access(dev_priv))
		return -ENODEV;

6538 6539
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
6540 6541 6542 6543 6544 6545 6546
		/*
		 * crtc's state no longer considered to be inherited
		 * after the first userspace/client initiated commit.
		 */
		if (!state->internal)
			new_crtc_state->inherited = false;

6547
		if (new_crtc_state->inherited != old_crtc_state->inherited)
6548
			new_crtc_state->uapi.mode_changed = true;
6549 6550 6551 6552

		if (new_crtc_state->uapi.scaling_filter !=
		    old_crtc_state->uapi.scaling_filter)
			new_crtc_state->uapi.mode_changed = true;
6553 6554
	}

6555 6556
	intel_vrr_check_modeset(state);

6557
	ret = drm_atomic_helper_check_modeset(dev, &state->base);
6558
	if (ret)
6559
		goto fail;
6560

6561 6562 6563 6564 6565 6566
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		ret = intel_async_flip_check_uapi(state, crtc);
		if (ret)
			return ret;
	}

6567
	ret = intel_atomic_check_config_and_link(state);
6568 6569 6570
	if (ret)
		goto fail;

6571 6572 6573 6574
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (!intel_crtc_needs_modeset(new_crtc_state))
			continue;

6575
		if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
6576 6577 6578 6579
			drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
			continue;
		}

6580
		ret = intel_atomic_check_joiner(state, crtc);
6581 6582 6583 6584
		if (ret)
			goto fail;
	}

6585 6586
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
6587
		if (!intel_crtc_needs_modeset(new_crtc_state))
6588 6589
			continue;

6590
		intel_joiner_adjust_pipe_src(new_crtc_state);
6591

6592
		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6593
	}
6594

6595 6596 6597 6598 6599 6600
	/**
	 * Check if fastset is allowed by external dependencies like other
	 * pipes and transcoders.
	 *
	 * Right now it only forces a fullmodeset when the MST master
	 * transcoder did not changed but the pipe of the master transcoder
6601 6602 6603 6604
	 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
	 * in case of port synced crtcs, if one of the synced crtcs
	 * needs a full modeset, all other synced crtcs should be
	 * forced a full modeset.
6605 6606
	 */
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6607
		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6608 6609
			continue;

6610 6611 6612
		if (intel_dp_mst_crtc_needs_modeset(state, crtc))
			intel_crtc_flag_modeset(new_crtc_state);

6613 6614 6615
		if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
			enum transcoder master = new_crtc_state->mst_master_transcoder;

6616 6617
			if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
				intel_crtc_flag_modeset(new_crtc_state);
6618 6619 6620
		}

		if (is_trans_port_sync_mode(new_crtc_state)) {
6621 6622 6623 6624
			u8 trans = new_crtc_state->sync_mode_slaves_mask;

			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
				trans |= BIT(new_crtc_state->master_transcoder);
6625

6626 6627
			if (intel_cpu_transcoders_need_modeset(state, trans))
				intel_crtc_flag_modeset(new_crtc_state);
6628
		}
6629

6630 6631
		if (new_crtc_state->joiner_pipes) {
			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))
6632
				intel_crtc_flag_modeset(new_crtc_state);
6633
		}
6634 6635
	}

6636 6637
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
6638
		if (!intel_crtc_needs_modeset(new_crtc_state))
6639 6640
			continue;

6641
		any_ms = true;
6642

6643
		intel_release_shared_dplls(state, crtc);
6644 6645
	}

6646
	if (any_ms && !check_digital_port_conflicts(state)) {
6647 6648
		drm_dbg_kms(&dev_priv->drm,
			    "rejecting conflicting digital port configuration\n");
6649
		ret = -EINVAL;
6650 6651 6652
		goto fail;
	}

6653
	ret = intel_atomic_check_planes(state);
6654 6655 6656
	if (ret)
		goto fail;

6657
	ret = intel_compute_global_watermarks(state);
6658
	if (ret)
6659
		goto fail;
6660

6661
	ret = intel_bw_atomic_check(state);
6662
	if (ret)
6663
		goto fail;
6664

6665
	ret = intel_cdclk_atomic_check(state, &any_ms);
6666 6667 6668
	if (ret)
		goto fail;

6669 6670 6671
	if (intel_any_crtc_needs_modeset(state))
		any_ms = true;

6672
	if (any_ms) {
6673 6674 6675 6676
		ret = intel_modeset_checks(state);
		if (ret)
			goto fail;

6677 6678 6679 6680 6681
		ret = intel_modeset_calc_cdclk(state);
		if (ret)
			return ret;
	}

6682 6683 6684 6685
	ret = intel_pmdemand_atomic_check(state);
	if (ret)
		goto fail;

6686 6687 6688 6689
	ret = intel_atomic_check_crtcs(state);
	if (ret)
		goto fail;

6690 6691 6692 6693
	ret = intel_fbc_atomic_check(state);
	if (ret)
		goto fail;

6694 6695
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
6696 6697
		intel_color_assert_luts(new_crtc_state);

6698 6699 6700
		ret = intel_async_flip_check_hw(state, crtc);
		if (ret)
			goto fail;
6701

6702 6703 6704 6705 6706
		/* Either full modeset or fastset (or neither), never both */
		drm_WARN_ON(&dev_priv->drm,
			    intel_crtc_needs_modeset(new_crtc_state) &&
			    intel_crtc_needs_fastset(new_crtc_state));

6707
		if (!intel_crtc_needs_modeset(new_crtc_state) &&
6708
		    !intel_crtc_needs_fastset(new_crtc_state))
6709 6710
			continue;

6711 6712
		intel_crtc_state_dump(new_crtc_state, state,
				      intel_crtc_needs_modeset(new_crtc_state) ?
6713
				      "modeset" : "fastset");
6714 6715
	}

6716
	return 0;
6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727

 fail:
	if (ret == -EDEADLK)
		return ret;

	/*
	 * FIXME would probably be nice to know which crtc specifically
	 * caused the failure, in cases where we can pinpoint it.
	 */
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i)
6728
		intel_crtc_state_dump(new_crtc_state, state, "failed");
6729 6730

	return ret;
6731 6732
}

6733
static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6734
{
6735
	struct intel_crtc_state __maybe_unused *crtc_state;
6736 6737 6738 6739 6740 6741 6742
	struct intel_crtc *crtc;
	int i, ret;

	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
	if (ret < 0)
		return ret;

6743 6744
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
		intel_color_prepare_commit(state, crtc);
6745 6746

	return 0;
6747 6748
}

6749 6750 6751 6752 6753
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

6754
	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767
		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);

	if (crtc_state->has_pch_encoder) {
		enum pipe pch_transcoder =
			intel_crtc_pch_transcoder(crtc);

		intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
	}
}

static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
			       const struct intel_crtc_state *new_crtc_state)
{
6768
	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	/*
	 * Update pipe size and adjust fitter if needed: the reason for this is
	 * that in compute_mode_changes we check the native mode (not the pfit
	 * mode) to see if we can flip rather than do a full mode set. In the
	 * fastboot case, we'll flip, but if we don't update the pipesrc and
	 * pfit state, we'll end up with a big fb scanned out into the wrong
	 * sized surface.
	 */
	intel_set_pipe_src_size(new_crtc_state);

	/* on skylake this is done by detaching scalers */
6782
	if (DISPLAY_VER(dev_priv) >= 9) {
6783
		if (new_crtc_state->pch_pfit.enabled)
6784
			skl_pfit_enable(new_crtc_state);
6785 6786
	} else if (HAS_PCH_SPLIT(dev_priv)) {
		if (new_crtc_state->pch_pfit.enabled)
6787
			ilk_pfit_enable(new_crtc_state);
6788
		else if (old_crtc_state->pch_pfit.enabled)
6789
			ilk_pfit_disable(old_crtc_state);
6790 6791
	}

6792 6793 6794 6795 6796 6797 6798 6799
	/*
	 * The register is supposedly single buffered so perhaps
	 * not 100% correct to do this here. But SKL+ calculate
	 * this based on the adjust pixel rate so pfit changes do
	 * affect it and so it must be updated for fastsets.
	 * HSW/BDW only really need this here for fastboot, after
	 * that the value should not change without a full modeset.
	 */
6800
	if (DISPLAY_VER(dev_priv) >= 9 ||
6801 6802
	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
		hsw_set_linetime_wm(new_crtc_state);
6803

6804
	if (new_crtc_state->update_m_n)
6805 6806
		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
					       &new_crtc_state->dp_m_n);
6807 6808 6809

	if (new_crtc_state->update_lrr)
		intel_set_transcoder_timings_lrr(new_crtc_state);
6810 6811
}

6812 6813
static void commit_pipe_pre_planes(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
6814 6815
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6816 6817 6818 6819
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
6820
	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6821 6822 6823 6824 6825 6826

	/*
	 * During modesets pipe configuration was programmed as the
	 * CRTC was enabled.
	 */
	if (!modeset) {
6827
		if (intel_crtc_needs_color_update(new_crtc_state))
6828
			intel_color_commit_arm(new_crtc_state);
6829

6830
		if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6831
			bdw_set_pipe_misc(new_crtc_state);
6832

6833
		if (intel_crtc_needs_fastset(new_crtc_state))
6834 6835 6836
			intel_pipe_fastset(old_crtc_state, new_crtc_state);
	}

6837 6838
	intel_psr2_program_trans_man_trk_ctl(new_crtc_state);

6839
	intel_atomic_update_watermarks(state, crtc);
6840 6841
}

6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856
static void commit_pipe_post_planes(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);

	/*
	 * Disable the scaler(s) after the plane(s) so that we don't
	 * get a catastrophic underrun even if the two operations
	 * end up happening in two different frames.
	 */
	if (DISPLAY_VER(dev_priv) >= 9 &&
	    !intel_crtc_needs_modeset(new_crtc_state))
		skl_detach_scalers(new_crtc_state);
6857

6858
	if (intel_crtc_vrr_enabling(state, crtc))
6859
		intel_vrr_enable(new_crtc_state);
6860 6861
}

6862 6863
static void intel_enable_crtc(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
6864
{
6865
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6866 6867
	const struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
6868
	struct intel_crtc *pipe_crtc;
6869

6870
	if (!intel_crtc_needs_modeset(new_crtc_state))
6871
		return;
6872

6873 6874 6875 6876
	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
		const struct intel_crtc_state *pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);
6877

6878 6879 6880
		/* VRR will be enable later, if required */
		intel_crtc_update_active_timings(pipe_crtc_state, false);
	}
6881

6882
	dev_priv->display.funcs.display->crtc_enable(state, crtc);
6883

6884 6885 6886 6887
	/* vblanks work again, re-enable pipe CRC. */
	intel_crtc_enable_pipe_crc(crtc);
}

6888 6889
static void intel_pre_update_crtc(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
6890
{
6891
	struct drm_i915_private *i915 = to_i915(state->base.dev);
6892 6893 6894 6895
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
6896
	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6897

6898 6899 6900 6901 6902 6903
	if (old_crtc_state->inherited ||
	    intel_crtc_needs_modeset(new_crtc_state)) {
		if (HAS_DPT(i915))
			intel_dpt_configure(crtc);
	}

6904
	if (!modeset) {
6905
		if (new_crtc_state->preload_luts &&
6906
		    intel_crtc_needs_color_update(new_crtc_state))
6907 6908
			intel_color_load_luts(new_crtc_state);

6909
		intel_pre_plane_update(state, crtc);
6910

6911
		if (intel_crtc_needs_fastset(new_crtc_state))
6912
			intel_encoders_update_pipe(state, crtc);
6913 6914

		if (DISPLAY_VER(i915) >= 11 &&
6915
		    intel_crtc_needs_fastset(new_crtc_state))
6916
			icl_set_pipe_chicken(new_crtc_state);
6917

6918 6919
		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
		    cmrr_params_changed(old_crtc_state, new_crtc_state))
6920
			intel_vrr_set_transcoder_timings(new_crtc_state);
6921 6922
	}

6923
	intel_fbc_update(state, crtc);
6924

6925 6926
	drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));

6927
	if (!modeset &&
6928
	    intel_crtc_needs_color_update(new_crtc_state))
6929 6930
		intel_color_commit_noarm(new_crtc_state);

6931
	intel_crtc_planes_update_noarm(state, crtc);
6932 6933 6934 6935 6936 6937 6938 6939 6940
}

static void intel_update_crtc(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
{
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	struct intel_crtc_state *new_crtc_state =
		intel_atomic_get_new_crtc_state(state, crtc);
6941

6942
	/* Perform vblank evasion around commit operation */
6943
	intel_pipe_update_start(state, crtc);
6944

6945
	commit_pipe_pre_planes(state, crtc);
6946

6947
	intel_crtc_planes_update_arm(state, crtc);
6948

6949 6950
	commit_pipe_post_planes(state, crtc);

6951
	intel_pipe_update_end(state, crtc);
6952

6953 6954 6955 6956 6957
	/*
	 * VRR/Seamless M/N update may need to update frame timings.
	 *
	 * FIXME Should be synchronized with the start of vblank somehow...
	 */
6958
	if (intel_crtc_vrr_enabling(state, crtc) ||
6959
	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6960 6961 6962
		intel_crtc_update_active_timings(new_crtc_state,
						 new_crtc_state->vrr.enable);

6963 6964 6965 6966 6967 6968
	/*
	 * We usually enable FIFO underrun interrupts as part of the
	 * CRTC enable sequence during modesets.  But when we inherit a
	 * valid pipe configuration from the BIOS we need to take care
	 * of enabling them on the CRTC's first fastset.
	 */
6969
	if (intel_crtc_needs_fastset(new_crtc_state) &&
6970
	    old_crtc_state->inherited)
6971
		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6972 6973
}

6974 6975 6976 6977
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
					  struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6978 6979 6980
	const struct intel_crtc_state *old_crtc_state =
		intel_atomic_get_old_crtc_state(state, crtc);
	struct intel_crtc *pipe_crtc;
6981 6982 6983 6984 6985

	/*
	 * We need to disable pipe CRC before disabling the pipe,
	 * or we race against vblank off.
	 */
6986 6987 6988
	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
					 intel_crtc_joined_pipe_mask(old_crtc_state))
		intel_crtc_disable_pipe_crc(pipe_crtc);
6989

6990
	dev_priv->display.funcs.display->crtc_disable(state, crtc);
6991

6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002
	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
		const struct intel_crtc_state *new_pipe_crtc_state =
			intel_atomic_get_new_crtc_state(state, pipe_crtc);

		pipe_crtc->active = false;
		intel_fbc_disable(pipe_crtc);

		if (!new_pipe_crtc_state->hw.active)
			intel_initial_watermarks(state, pipe_crtc);
	}
7003 7004 7005 7006
}

static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
7007
	struct drm_i915_private *i915 = to_i915(state->base.dev);
7008
	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7009
	struct intel_crtc *crtc;
7010
	u8 disable_pipes = 0;
7011 7012
	int i;

7013 7014 7015 7016 7017
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
		if (!intel_crtc_needs_modeset(new_crtc_state))
			continue;

7018 7019 7020 7021
		/*
		 * Needs to be done even for pipes
		 * that weren't enabled previously.
		 */
7022 7023
		intel_pre_plane_update(state, crtc);

7024 7025 7026
		if (!old_crtc_state->hw.active)
			continue;

7027
		disable_pipes |= BIT(crtc->pipe);
7028 7029
	}

7030 7031 7032 7033 7034
	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
		if ((disable_pipes & BIT(crtc->pipe)) == 0)
			continue;

		intel_crtc_disable_planes(state, crtc);
7035 7036

		drm_vblank_work_flush_all(&crtc->base);
7037 7038
	}

7039
	/* Only disable port sync and MST slaves */
7040
	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
7041
		if ((disable_pipes & BIT(crtc->pipe)) == 0)
7042 7043
			continue;

7044
		if (intel_crtc_is_joiner_secondary(old_crtc_state))
7045 7046
			continue;

7047 7048 7049 7050 7051
		/* In case of Transcoder port Sync master slave CRTCs can be
		 * assigned in any order and we need to make sure that
		 * slave CRTCs are disabled first and then master CRTC since
		 * Slave vblanks are masked till Master Vblanks.
		 */
7052
		if (!is_trans_port_sync_slave(old_crtc_state) &&
7053
		    !intel_dp_mst_is_slave_trans(old_crtc_state))
7054
			continue;
7055

7056
		intel_old_crtc_state_disables(state, crtc);
7057

7058
		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
7059 7060 7061
	}

	/* Disable everything else left on */
7062
	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
7063
		if ((disable_pipes & BIT(crtc->pipe)) == 0)
7064 7065
			continue;

7066
		if (intel_crtc_is_joiner_secondary(old_crtc_state))
7067 7068
			continue;

7069
		intel_old_crtc_state_disables(state, crtc);
7070

7071
		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
7072
	}
7073 7074

	drm_WARN_ON(&i915->drm, disable_pipes);
7075 7076
}

7077
static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7078
{
7079
	struct intel_crtc_state *new_crtc_state;
7080
	struct intel_crtc *crtc;
7081 7082
	int i;

7083
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7084
		if (!new_crtc_state->hw.active)
7085 7086
			continue;

7087
		intel_enable_crtc(state, crtc);
7088
		intel_pre_update_crtc(state, crtc);
7089 7090 7091 7092 7093 7094
	}

	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		if (!new_crtc_state->hw.active)
			continue;

7095
		intel_update_crtc(state, crtc);
7096 7097 7098
	}
}

7099
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7100
{
7101 7102 7103
	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
	struct intel_crtc *crtc;
	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7104
	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7105
	u8 update_pipes = 0, modeset_pipes = 0;
7106
	int i;
7107

7108
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7109 7110
		enum pipe pipe = crtc->pipe;

7111 7112 7113
		if (!new_crtc_state->hw.active)
			continue;

7114
		/* ignore allocations for crtc's that have been turned off. */
7115
		if (!intel_crtc_needs_modeset(new_crtc_state)) {
7116 7117
			entries[pipe] = old_crtc_state->wm.skl.ddb;
			update_pipes |= BIT(pipe);
7118
		} else {
7119
			modeset_pipes |= BIT(pipe);
7120
		}
7121
	}
7122 7123 7124 7125

	/*
	 * Whenever the number of active pipes changes, we need to make sure we
	 * update the pipes in the right order so that their ddb allocations
7126
	 * never overlap with each other between CRTC updates. Otherwise we'll
7127
	 * cause pipe underruns and other bad stuff.
7128 7129 7130
	 *
	 * So first lets enable all pipes that do not need a fullmodeset as
	 * those don't have any external dependency.
7131
	 */
7132 7133 7134 7135 7136 7137 7138 7139 7140
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		enum pipe pipe = crtc->pipe;

		if ((update_pipes & BIT(pipe)) == 0)
			continue;

		intel_pre_update_crtc(state, crtc);
	}

7141 7142
	intel_dbuf_mbus_pre_ddb_update(state);

7143
	while (update_pipes) {
7144
		/*
7145 7146
		 * Commit in reverse order to make joiner primary
		 * send the uapi events after secondaries are done.
7147 7148 7149
		 */
		for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
							    new_crtc_state, i) {
7150
			enum pipe pipe = crtc->pipe;
7151

7152
			if ((update_pipes & BIT(pipe)) == 0)
7153
				continue;
7154

7155
			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7156
							entries, I915_MAX_PIPES, pipe))
7157 7158
				continue;

7159
			entries[pipe] = new_crtc_state->wm.skl.ddb;
7160 7161
			update_pipes &= ~BIT(pipe);

7162
			intel_update_crtc(state, crtc);
7163

7164 7165 7166 7167 7168 7169 7170 7171
			/*
			 * If this is an already active pipe, it's DDB changed,
			 * and this isn't the last pipe that needs updating
			 * then we need to wait for a vblank to pass for the
			 * new ddb allocation to take effect.
			 */
			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
						 &old_crtc_state->wm.skl.ddb) &&
7172
			    (update_pipes | modeset_pipes))
7173
				intel_crtc_wait_for_next_vblank(crtc);
7174
		}
7175
	}
7176

7177 7178
	intel_dbuf_mbus_post_ddb_update(state);

7179 7180
	update_pipes = modeset_pipes;

7181 7182 7183 7184
	/*
	 * Enable all pipes that needs a modeset and do not depends on other
	 * pipes
	 */
7185
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7186 7187 7188 7189 7190
		enum pipe pipe = crtc->pipe;

		if ((modeset_pipes & BIT(pipe)) == 0)
			continue;

7191
		if (intel_crtc_is_joiner_secondary(new_crtc_state))
7192 7193
			continue;

7194
		if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7195
		    is_trans_port_sync_master(new_crtc_state))
7196 7197
			continue;

7198
		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7199

7200
		intel_enable_crtc(state, crtc);
7201 7202 7203
	}

	/*
7204
	 * Then we enable all remaining pipes that depend on other
7205
	 * pipes: MST slaves and port sync masters
7206
	 */
7207
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7208 7209 7210 7211 7212
		enum pipe pipe = crtc->pipe;

		if ((modeset_pipes & BIT(pipe)) == 0)
			continue;

7213
		if (intel_crtc_is_joiner_secondary(new_crtc_state))
7214 7215 7216
			continue;

		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7217 7218 7219 7220 7221 7222 7223

		intel_enable_crtc(state, crtc);
	}

	/*
	 * Finally we do the plane updates/etc. for all pipes that got enabled.
	 */
7224 7225 7226 7227 7228 7229 7230 7231 7232
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
		enum pipe pipe = crtc->pipe;

		if ((update_pipes & BIT(pipe)) == 0)
			continue;

		intel_pre_update_crtc(state, crtc);
	}

7233
	/*
7234 7235
	 * Commit in reverse order to make joiner primary
	 * send the uapi events after secondaries are done.
7236 7237
	 */
	for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7238 7239 7240 7241 7242
		enum pipe pipe = crtc->pipe;

		if ((update_pipes & BIT(pipe)) == 0)
			continue;

7243
		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7244
									entries, I915_MAX_PIPES, pipe));
7245

7246
		entries[pipe] = new_crtc_state->wm.skl.ddb;
7247
		update_pipes &= ~BIT(pipe);
7248

7249
		intel_update_crtc(state, crtc);
7250 7251
	}

7252
	drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7253
	drm_WARN_ON(&dev_priv->drm, update_pipes);
7254 7255
}

7256 7257
static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
{
7258 7259 7260 7261
	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
	struct drm_plane *plane;
	struct drm_plane_state *new_plane_state;
	int ret, i;
7262

7263 7264 7265 7266 7267 7268
	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
		if (new_plane_state->fence) {
			ret = dma_fence_wait_timeout(new_plane_state->fence, false,
						     i915_fence_timeout(i915));
			if (ret <= 0)
				break;
7269

7270 7271 7272
			dma_fence_put(new_plane_state->fence);
			new_plane_state->fence = NULL;
		}
7273 7274 7275
	}
}

7276 7277
static void intel_atomic_cleanup_work(struct work_struct *work)
{
7278 7279 7280
	struct intel_atomic_state *state =
		container_of(work, struct intel_atomic_state, base.commit_work);
	struct drm_i915_private *i915 = to_i915(state->base.dev);
7281 7282 7283 7284 7285 7286
	struct intel_crtc_state *old_crtc_state;
	struct intel_crtc *crtc;
	int i;

	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
		intel_color_cleanup_commit(old_crtc_state);
7287

7288 7289 7290
	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
	drm_atomic_helper_commit_cleanup_done(&state->base);
	drm_atomic_state_put(&state->base);
7291 7292
}

7293 7294 7295 7296 7297 7298 7299 7300 7301
static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
{
	struct drm_i915_private *i915 = to_i915(state->base.dev);
	struct intel_plane *plane;
	struct intel_plane_state *plane_state;
	int i;

	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
		struct drm_framebuffer *fb = plane_state->hw.fb;
7302
		int cc_plane;
7303 7304
		int ret;

7305 7306 7307 7308 7309
		if (!fb)
			continue;

		cc_plane = intel_fb_rc_ccs_cc_plane(fb);
		if (cc_plane < 0)
7310 7311 7312 7313
			continue;

		/*
		 * The layout of the fast clear color value expected by HW
7314 7315 7316
		 * (the DRM ABI requiring this value to be located in fb at
		 * offset 0 of cc plane, plane #2 previous generations or
		 * plane #1 for flat ccs):
7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327
		 * - 4 x 4 bytes per-channel value
		 *   (in surface type specific float/int format provided by the fb user)
		 * - 8 bytes native color value used by the display
		 *   (converted/written by GPU during a fast clear operation using the
		 *    above per-channel values)
		 *
		 * The commit's FB prepare hook already ensured that FB obj is pinned and the
		 * caller made sure that the object is synced wrt. the related color clear value
		 * GPU write on it.
		 */
		ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7328
						     fb->offsets[cc_plane] + 16,
7329 7330 7331 7332 7333 7334 7335
						     &plane_state->ccval,
						     sizeof(plane_state->ccval));
		/* The above could only fail if the FB obj has an unexpected backing store type. */
		drm_WARN_ON(&i915->drm, ret);
	}
}

7336
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7337
{
7338
	struct drm_device *dev = state->base.dev;
7339
	struct drm_i915_private *dev_priv = to_i915(dev);
7340 7341
	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
	struct intel_crtc *crtc;
7342
	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7343
	intel_wakeref_t wakeref = 0;
7344
	int i;
7345

7346
	intel_atomic_commit_fence_wait(state);
7347

7348 7349
	intel_td_flush(dev_priv);

7350
	drm_atomic_helper_wait_for_dependencies(&state->base);
7351
	drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7352
	intel_atomic_global_state_wait_for_dependencies(state);
7353

7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371 7372 7373
	/*
	 * During full modesets we write a lot of registers, wait
	 * for PLLs, etc. Doing that while DC states are enabled
	 * is not a good idea.
	 *
	 * During fastsets and other updates we also need to
	 * disable DC states due to the following scenario:
	 * 1. DC5 exit and PSR exit happen
	 * 2. Some or all _noarm() registers are written
	 * 3. Due to some long delay PSR is re-entered
	 * 4. DC5 entry -> DMC saves the already written new
	 *    _noarm() registers and the old not yet written
	 *    _arm() registers
	 * 5. DC5 exit -> DMC restores a mixture of old and
	 *    new register values and arms the update
	 * 6. PSR exit -> hardware latches a mixture of old and
	 *    new register values -> corrupted frame, or worse
	 * 7. New _arm() registers are finally written
	 * 8. Hardware finally latches a complete set of new
	 *    register values, and subsequent frames will be OK again
7374 7375 7376 7377 7378 7379
	 *
	 * Also note that due to the pipe CSC hardware issues on
	 * SKL/GLK DC states must remain off until the pipe CSC
	 * state readout has happened. Otherwise we risk corrupting
	 * the CSC latched register values with the readout (see
	 * skl_read_csc() and skl_color_commit_noarm()).
7380 7381
	 */
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7382

7383 7384
	intel_atomic_prepare_plane_clear_colors(state);

7385 7386
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
7387
		if (intel_crtc_needs_modeset(new_crtc_state) ||
7388
		    intel_crtc_needs_fastset(new_crtc_state))
7389
			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7390
	}
7391

7392 7393
	intel_commit_modeset_disables(state);

7394 7395
	intel_dp_tunnel_atomic_alloc_bw(state);

7396 7397 7398
	/* FIXME: Eventually get rid of our crtc->config pointer */
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
		crtc->config = new_crtc_state;
7399

7400 7401 7402 7403 7404 7405 7406 7407
	/*
	 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
	 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
	 * index, cdclk/ddiclk frequencies are supposed to be configured before
	 * the cdclk config is set.
	 */
	intel_pmdemand_pre_plane_update(state);

7408 7409
	if (state->modeset) {
		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7410

7411
		intel_set_cdclk_pre_plane_update(state);
7412

7413
		intel_modeset_verify_disabled(state);
7414
	}
7415

7416 7417
	intel_sagv_pre_plane_update(state);

7418
	/* Complete the events for pipes that have now been disabled */
7419
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7420
		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7421

7422
		/* Complete events for now disable pipes here. */
7423
		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7424
			spin_lock_irq(&dev->event_lock);
7425 7426
			drm_crtc_send_vblank_event(&crtc->base,
						   new_crtc_state->uapi.event);
7427 7428
			spin_unlock_irq(&dev->event_lock);

7429
			new_crtc_state->uapi.event = NULL;
7430
		}
7431 7432
	}

7433
	intel_encoders_update_prepare(state);
7434

7435
	intel_dbuf_pre_plane_update(state);
7436

7437
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7438
		if (new_crtc_state->do_async_flip)
7439
			intel_crtc_enable_flip_done(state, crtc);
7440 7441
	}

7442
	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7443
	dev_priv->display.funcs.display->commit_modeset_enables(state);
7444

7445
	if (state->modeset)
7446
		intel_set_cdclk_post_plane_update(state);
7447

7448 7449
	intel_wait_for_vblank_workers(state);

7450 7451 7452 7453 7454 7455 7456 7457 7458
	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
	 * already, but still need the state for the delayed optimization. To
	 * fix this:
	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
	 * - schedule that vblank worker _before_ calling hw_done
	 * - at the start of commit_tail, cancel it _synchrously
	 * - switch over to the vblank wait helper in the core after that since
	 *   we don't need out special handling any more.
	 */
7459
	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7460

7461
	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7462
		if (new_crtc_state->do_async_flip)
7463
			intel_crtc_disable_flip_done(state, crtc);
7464 7465

		intel_color_wait_commit(new_crtc_state);
7466 7467
	}

7468 7469 7470 7471 7472 7473 7474
	/*
	 * Now that the vblank has passed, we can go ahead and program the
	 * optimal watermarks on platforms that need two-step watermark
	 * programming.
	 *
	 * TODO: Move this (and other cleanup) to an async worker eventually.
	 */
7475 7476 7477 7478 7479 7480 7481 7482 7483 7484
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
					    new_crtc_state, i) {
		/*
		 * Gen2 reports pipe underruns whenever all planes are disabled.
		 * So re-enable underrun reporting after some planes get enabled.
		 *
		 * We do this before .optimize_watermarks() so that we have a
		 * chance of catching underruns with the intermediate watermarks
		 * vs. the new plane configuration.
		 */
7485
		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7486 7487
			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);

7488
		intel_optimize_watermarks(state, crtc);
7489 7490
	}

7491
	intel_dbuf_post_plane_update(state);
7492

7493
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7494
		intel_post_plane_update(state, crtc);
7495

7496
		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7497

7498
		intel_modeset_verify_crtc(state, crtc);
7499

7500 7501 7502
		/* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
		hsw_ips_post_update(state, crtc);

7503 7504 7505 7506 7507 7508
		/*
		 * Activate DRRS after state readout to avoid
		 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
		 */
		intel_drrs_activate(new_crtc_state);

7509 7510 7511 7512
		/*
		 * DSB cleanup is done in cleanup_work aligning with framebuffer
		 * cleanup. So copy and reset the dsb structure to sync with
		 * commit_done and later do dsb cleanup in cleanup_work.
7513 7514
		 *
		 * FIXME get rid of this funny new->old swapping
7515
		 */
7516
		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
7517 7518
	}

7519 7520 7521 7522
	/* Underruns don't always raise interrupts, so check manually */
	intel_check_cpu_fifo_underruns(dev_priv);
	intel_check_pch_fifo_underruns(dev_priv);

7523
	if (state->modeset)
7524
		intel_verify_planes(state);
7525

7526
	intel_sagv_post_plane_update(state);
7527
	intel_pmdemand_post_plane_update(state);
7528

7529
	drm_atomic_helper_commit_hw_done(&state->base);
7530
	intel_atomic_global_state_commit_done(state);
7531

7532
	if (state->modeset) {
7533 7534 7535 7536 7537 7538
		/* As one of the primary mmio accessors, KMS has a high
		 * likelihood of triggering bugs in unclaimed access. After we
		 * finish modesetting, see if an error has been flagged, and if
		 * so enable debugging for the next modeset - and hope we catch
		 * the culprit.
		 */
7539
		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7540
	}
7541 7542 7543 7544 7545
	/*
	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
	 * toggling overhead at and above 60 FPS.
	 */
	intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7546
	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7547

7548 7549 7550 7551 7552 7553 7554 7555
	/*
	 * Defer the cleanup of the old state to a separate worker to not
	 * impede the current task (userspace for blocking modesets) that
	 * are executed inline. For out-of-line asynchronous modesets/flips,
	 * deferring to a new worker seems overkill, but we would place a
	 * schedule point (cond_resched()) here anyway to keep latencies
	 * down.
	 */
7556 7557
	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
	queue_work(system_highpri_wq, &state->base.commit_work);
7558 7559 7560 7561
}

static void intel_atomic_commit_work(struct work_struct *work)
{
7562 7563
	struct intel_atomic_state *state =
		container_of(work, struct intel_atomic_state, base.commit_work);
7564

7565 7566 7567
	intel_atomic_commit_tail(state);
}

7568
static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7569
{
7570 7571
	struct intel_plane_state *old_plane_state, *new_plane_state;
	struct intel_plane *plane;
7572 7573
	int i;

7574 7575
	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
					     new_plane_state, i)
7576 7577
		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
					to_intel_frontbuffer(new_plane_state->hw.fb),
7578
					plane->frontbuffer_bit);
7579 7580
}

7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595
static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
{
	int ret;

	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
	if (ret)
		return ret;

	ret = intel_atomic_global_state_setup_commit(state);
	if (ret)
		return ret;

	return 0;
}

7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612
static int intel_atomic_swap_state(struct intel_atomic_state *state)
{
	int ret;

	ret = drm_atomic_helper_swap_state(&state->base, true);
	if (ret)
		return ret;

	intel_atomic_swap_global_state(state);

	intel_shared_dpll_swap_state(state);

	intel_atomic_track_fbs(state);

	return 0;
}

7613 7614
int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
			bool nonblock)
7615
{
7616
	struct intel_atomic_state *state = to_intel_atomic_state(_state);
7617
	struct drm_i915_private *dev_priv = to_i915(dev);
7618 7619
	int ret = 0;

7620
	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7621

7622 7623 7624 7625 7626 7627 7628 7629
	/*
	 * The intel_legacy_cursor_update() fast path takes care
	 * of avoiding the vblank waits for simple cursor
	 * movement and flips. For cursor on/off and size changes,
	 * we want to perform the vblank waits so that watermark
	 * updates happen during the correct frames. Gen9+ have
	 * double buffered watermarks and so shouldn't need this.
	 *
7630 7631 7632 7633 7634
	 * Unset state->legacy_cursor_update before the call to
	 * drm_atomic_helper_setup_commit() because otherwise
	 * drm_atomic_helper_wait_for_flip_done() is a noop and
	 * we get FIFO underruns because we didn't wait
	 * for vblank.
7635 7636 7637 7638
	 *
	 * FIXME doing watermarks and fb cleanup from a vblank worker
	 * (assuming we had any) would solve these problems.
	 */
7639
	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7640 7641 7642 7643
		struct intel_crtc_state *new_crtc_state;
		struct intel_crtc *crtc;
		int i;

7644
		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7645 7646
			if (new_crtc_state->wm.need_postvbl_update ||
			    new_crtc_state->update_wm_post)
7647
				state->base.legacy_cursor_update = false;
7648
	}
7649

7650
	ret = intel_atomic_prepare_commit(state);
7651
	if (ret) {
7652 7653
		drm_dbg_atomic(&dev_priv->drm,
			       "Preparing state failed with %i\n", ret);
7654
		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7655 7656 7657
		return ret;
	}

7658
	ret = intel_atomic_setup_commit(state, nonblock);
7659
	if (!ret)
7660
		ret = intel_atomic_swap_state(state);
7661

7662
	if (ret) {
7663 7664 7665 7666 7667
		struct intel_crtc_state *new_crtc_state;
		struct intel_crtc *crtc;
		int i;

		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7668
			intel_color_cleanup_commit(new_crtc_state);
7669

7670
		drm_atomic_helper_unprepare_planes(dev, &state->base);
7671
		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7672 7673
		return ret;
	}
7674

7675 7676
	drm_atomic_state_get(&state->base);
	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7677

7678
	if (nonblock && state->modeset) {
7679
		queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7680
	} else if (nonblock) {
7681
		queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7682
	} else {
7683
		if (state->modeset)
7684
			flush_workqueue(dev_priv->display.wq.modeset);
7685
		intel_atomic_commit_tail(state);
7686
	}
7687

7688
	return 0;
7689 7690
}

7691
/**
7692 7693
 * intel_plane_destroy - destroy a plane
 * @plane: plane to destroy
7694
 *
7695 7696
 * Common destruction function for all types of planes (primary, cursor,
 * sprite).
7697
 */
7698
void intel_plane_destroy(struct drm_plane *plane)
7699 7700
{
	drm_plane_cleanup(plane);
7701
	kfree(to_intel_plane(plane));
7702 7703
}

7704 7705
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
				      struct drm_file *file)
7706 7707
{
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark's avatar
Rob Clark committed
7708
	struct drm_crtc *drmmode_crtc;
7709
	struct intel_crtc *crtc;
7710

7711
	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7712
	if (!drmmode_crtc)
7713
		return -ENOENT;
7714

Rob Clark's avatar
Rob Clark committed
7715
	crtc = to_intel_crtc(drmmode_crtc);
7716
	pipe_from_crtc_id->pipe = crtc->pipe;
7717

7718
	return 0;
7719 7720
}

7721
static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7722
{
7723 7724
	struct drm_device *dev = encoder->base.dev;
	struct intel_encoder *source_encoder;
7725
	u32 possible_clones = 0;
7726

7727
	for_each_intel_encoder(dev, source_encoder) {
7728
		if (encoders_cloneable(encoder, source_encoder))
7729
			possible_clones |= drm_encoder_mask(&source_encoder->base);
7730
	}
7731

7732
	return possible_clones;
7733 7734
}

7735 7736 7737 7738 7739 7740
static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct intel_crtc *crtc;
	u32 possible_crtcs = 0;

7741 7742
	for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
		possible_crtcs |= drm_crtc_mask(&crtc->base);
7743 7744 7745 7746

	return possible_crtcs;
}

7747
static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7748
{
7749
	if (!IS_MOBILE(dev_priv))
7750 7751
		return false;

7752
	if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7753 7754
		return false;

7755
	if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7756 7757 7758 7759 7760
		return false;

	return true;
}

7761
static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7762
{
7763
	if (DISPLAY_VER(dev_priv) >= 9)
7764 7765
		return false;

7766
	if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7767 7768
		return false;

7769
	if (HAS_PCH_LPT_H(dev_priv) &&
7770
	    intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7771 7772
		return false;

7773
	/* DDI E can't be used if DDI A requires 4 lanes */
7774
	if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7775 7776
		return false;

7777
	if (!dev_priv->display.vbt.int_crt_support)
7778 7779 7780 7781 7782
		return false;

	return true;
}

7783 7784 7785 7786 7787 7788
bool assert_port_valid(struct drm_i915_private *i915, enum port port)
{
	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
			 "Platform does not support port %c\n", port_name(port));
}

7789
void intel_setup_outputs(struct drm_i915_private *dev_priv)
7790
{
7791
	struct intel_display *display = &dev_priv->display;
7792
	struct intel_encoder *encoder;
7793
	bool dpd_is_edp = false;
7794

7795
	intel_pps_unlock_regs_wa(dev_priv);
7796

7797
	if (!HAS_DISPLAY(dev_priv))
7798 7799
		return;

7800 7801 7802 7803
	if (HAS_DDI(dev_priv)) {
		if (intel_ddi_crt_present(dev_priv))
			intel_crt_init(dev_priv);

7804
		intel_bios_for_each_encoder(display, intel_ddi_init);
7805 7806 7807

		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
			vlv_dsi_init(dev_priv);
7808
	} else if (HAS_PCH_SPLIT(dev_priv)) {
7809
		int found;
7810

7811 7812 7813 7814 7815 7816
		/*
		 * intel_edp_init_connector() depends on this completing first,
		 * to prevent the registration of both eDP and LVDS and the
		 * incorrect sharing of the PPS.
		 */
		intel_lvds_init(dev_priv);
7817
		intel_crt_init(dev_priv);
7818

7819
		dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7820

7821
		if (ilk_has_edp_a(dev_priv))
7822
			g4x_dp_init(dev_priv, DP_A, PORT_A);
7823

7824
		if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7825
			/* PCH SDVOB multiplex with HDMIB */
7826
			found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7827
			if (!found)
7828
				g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7829
			if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7830
				g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7831 7832
		}

7833
		if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7834
			g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7835

7836
		if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7837
			g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7838

7839
		if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7840
			g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7841

7842
		if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7843
			g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7844
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7845
		bool has_edp, has_port;
7846

7847
		if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7848 7849
			intel_crt_init(dev_priv);

7850 7851 7852 7853 7854 7855 7856 7857
		/*
		 * The DP_DETECTED bit is the latched state of the DDC
		 * SDA pin at boot. However since eDP doesn't require DDC
		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
		 * eDP ports may have been muxed to an alternate function.
		 * Thus we can't rely on the DP_DETECTED bit alone to detect
		 * eDP ports. Consult the VBT as well as DP_DETECTED to
		 * detect eDP ports.
7858 7859 7860 7861 7862 7863
		 *
		 * Sadly the straps seem to be missing sometimes even for HDMI
		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
		 * and VBT for the presence of the port. Additionally we can't
		 * trust the port type the VBT declares as we've seen at least
		 * HDMI ports that the VBT claim are DP or eDP.
7864
		 */
7865
		has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7866
		has_port = intel_bios_is_port_present(display, PORT_B);
7867
		if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7868
			has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7869
		if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7870
			g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7871

7872
		has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7873
		has_port = intel_bios_is_port_present(display, PORT_C);
7874
		if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7875
			has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7876
		if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7877
			g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7878

7879
		if (IS_CHERRYVIEW(dev_priv)) {
7880 7881 7882 7883
			/*
			 * eDP not supported on port D,
			 * so no need to worry about it
			 */
7884
			has_port = intel_bios_is_port_present(display, PORT_D);
7885
			if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7886
				g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7887
			if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7888
				g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7889 7890
		}

7891
		vlv_dsi_init(dev_priv);
7892
	} else if (IS_PINEVIEW(dev_priv)) {
7893
		intel_lvds_init(dev_priv);
7894
		intel_crt_init(dev_priv);
7895
	} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7896
		bool found = false;
7897

7898 7899
		if (IS_MOBILE(dev_priv))
			intel_lvds_init(dev_priv);
7900

7901
		intel_crt_init(dev_priv);
7902

7903
		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7904
			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7905
			found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7906
			if (!found && IS_G4X(dev_priv)) {
7907 7908
				drm_dbg_kms(&dev_priv->drm,
					    "probing HDMI on SDVOB\n");
7909
				g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7910
			}
7911

7912
			if (!found && IS_G4X(dev_priv))
7913
				g4x_dp_init(dev_priv, DP_B, PORT_B);
7914
		}
7915 7916 7917

		/* Before G4X SDVOC doesn't have its own detect register */

7918
		if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7919
			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7920
			found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7921
		}
7922

7923
		if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7924

7925
			if (IS_G4X(dev_priv)) {
7926 7927
				drm_dbg_kms(&dev_priv->drm,
					    "probing HDMI on SDVOC\n");
7928
				g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7929
			}
7930
			if (IS_G4X(dev_priv))
7931
				g4x_dp_init(dev_priv, DP_C, PORT_C);
7932
		}
7933

7934
		if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7935
			g4x_dp_init(dev_priv, DP_D, PORT_D);
7936 7937

		if (SUPPORTS_TV(dev_priv))
7938
			intel_tv_init(display);
7939
	} else if (DISPLAY_VER(dev_priv) == 2) {
7940
		if (IS_I85X(dev_priv))
7941
			intel_lvds_init(dev_priv);
7942

7943
		intel_crt_init(dev_priv);
7944
		intel_dvo_init(dev_priv);
7945
	}
7946

7947
	for_each_intel_encoder(&dev_priv->drm, encoder) {
7948 7949
		encoder->base.possible_crtcs =
			intel_encoder_possible_crtcs(encoder);
7950
		encoder->base.possible_clones =
7951
			intel_encoder_possible_clones(encoder);
7952
	}
7953

7954
	intel_init_pch_refclk(dev_priv);
7955

7956
	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7957 7958
}

7959 7960
static int max_dotclock(struct drm_i915_private *i915)
{
7961
	int max_dotclock = i915->display.cdclk.max_dotclk_freq;
7962

7963
	/* icl+ might use joiner */
7964 7965 7966 7967 7968 7969
	if (DISPLAY_VER(i915) >= 11)
		max_dotclock *= 2;

	return max_dotclock;
}

7970 7971
enum drm_mode_status intel_mode_valid(struct drm_device *dev,
				      const struct drm_display_mode *mode)
7972
{
7973 7974 7975 7976
	struct drm_i915_private *dev_priv = to_i915(dev);
	int hdisplay_max, htotal_max;
	int vdisplay_max, vtotal_max;

7977 7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989
	/*
	 * Can't reject DBLSCAN here because Xorg ddxen can add piles
	 * of DBLSCAN modes to the output's mode list when they detect
	 * the scaling mode property on the connector. And they don't
	 * ask the kernel to validate those modes in any way until
	 * modeset time at which point the client gets a protocol error.
	 * So in order to not upset those clients we silently ignore the
	 * DBLSCAN flag on such connectors. For other connectors we will
	 * reject modes with the DBLSCAN flag in encoder->compute_config().
	 * And we always reject DBLSCAN modes in connector->mode_valid()
	 * as we never want such modes on the connector's mode list.
	 */

7990 7991 7992 7993 7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005
	if (mode->vscan > 1)
		return MODE_NO_VSCAN;

	if (mode->flags & DRM_MODE_FLAG_HSKEW)
		return MODE_H_ILLEGAL;

	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
			   DRM_MODE_FLAG_NCSYNC |
			   DRM_MODE_FLAG_PCSYNC))
		return MODE_HSYNC;

	if (mode->flags & (DRM_MODE_FLAG_BCAST |
			   DRM_MODE_FLAG_PIXMUX |
			   DRM_MODE_FLAG_CLKDIV2))
		return MODE_BAD;

8006 8007 8008 8009 8010 8011 8012
	/*
	 * Reject clearly excessive dotclocks early to
	 * avoid having to worry about huge integers later.
	 */
	if (mode->clock > max_dotclock(dev_priv))
		return MODE_CLOCK_HIGH;

8013
	/* Transcoder timing limits */
8014
	if (DISPLAY_VER(dev_priv) >= 11) {
8015 8016 8017 8018
		hdisplay_max = 16384;
		vdisplay_max = 8192;
		htotal_max = 16384;
		vtotal_max = 8192;
8019
	} else if (DISPLAY_VER(dev_priv) >= 9 ||
8020
		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8021 8022 8023 8024
		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
		vdisplay_max = 4096;
		htotal_max = 8192;
		vtotal_max = 8192;
8025
	} else if (DISPLAY_VER(dev_priv) >= 3) {
8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048
		hdisplay_max = 4096;
		vdisplay_max = 4096;
		htotal_max = 8192;
		vtotal_max = 8192;
	} else {
		hdisplay_max = 2048;
		vdisplay_max = 2048;
		htotal_max = 4096;
		vtotal_max = 4096;
	}

	if (mode->hdisplay > hdisplay_max ||
	    mode->hsync_start > htotal_max ||
	    mode->hsync_end > htotal_max ||
	    mode->htotal > htotal_max)
		return MODE_H_ILLEGAL;

	if (mode->vdisplay > vdisplay_max ||
	    mode->vsync_start > vtotal_max ||
	    mode->vsync_end > vtotal_max ||
	    mode->vtotal > vtotal_max)
		return MODE_V_ILLEGAL;

8049 8050 8051 8052 8053 8054 8055 8056 8057 8058
	return MODE_OK;
}

enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
						     const struct drm_display_mode *mode)
{
	/*
	 * Additional transcoder timing limits,
	 * excluding BXT/GLK DSI transcoders.
	 */
8059
	if (DISPLAY_VER(dev_priv) >= 5) {
8060 8061 8062 8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073
		if (mode->hdisplay < 64 ||
		    mode->htotal - mode->hdisplay < 32)
			return MODE_H_ILLEGAL;

		if (mode->vtotal - mode->vdisplay < 5)
			return MODE_V_ILLEGAL;
	} else {
		if (mode->htotal - mode->hdisplay < 32)
			return MODE_H_ILLEGAL;

		if (mode->vtotal - mode->vdisplay < 3)
			return MODE_V_ILLEGAL;
	}

8074 8075 8076 8077
	/*
	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
	 */
8078
	if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
8079 8080 8081
	    mode->hsync_start == mode->hdisplay)
		return MODE_H_ILLEGAL;

8082 8083 8084
	return MODE_OK;
}

8085 8086
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8087
				const struct drm_display_mode *mode,
8088
				bool joiner)
8089 8090 8091 8092 8093 8094 8095
{
	int plane_width_max, plane_height_max;

	/*
	 * intel_mode_valid() should be
	 * sufficient on older platforms.
	 */
8096
	if (DISPLAY_VER(dev_priv) < 9)
8097 8098 8099 8100 8101 8102 8103
		return MODE_OK;

	/*
	 * Most people will probably want a fullscreen
	 * plane so let's not advertize modes that are
	 * too big for that.
	 */
8104
	if (DISPLAY_VER(dev_priv) >= 11) {
8105
		plane_width_max = 5120 << joiner;
8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118 8119 8120
		plane_height_max = 4320;
	} else {
		plane_width_max = 5120;
		plane_height_max = 4096;
	}

	if (mode->hdisplay > plane_width_max)
		return MODE_H_ILLEGAL;

	if (mode->vdisplay > plane_height_max)
		return MODE_V_ILLEGAL;

	return MODE_OK;
}

8121
static const struct intel_display_funcs skl_display_funcs = {
8122 8123 8124 8125 8126
	.get_pipe_config = hsw_get_pipe_config,
	.crtc_enable = hsw_crtc_enable,
	.crtc_disable = hsw_crtc_disable,
	.commit_modeset_enables = skl_commit_modeset_enables,
	.get_initial_plane_config = skl_get_initial_plane_config,
8127
	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
8128 8129
};

8130
static const struct intel_display_funcs ddi_display_funcs = {
8131 8132 8133 8134 8135
	.get_pipe_config = hsw_get_pipe_config,
	.crtc_enable = hsw_crtc_enable,
	.crtc_disable = hsw_crtc_disable,
	.commit_modeset_enables = intel_commit_modeset_enables,
	.get_initial_plane_config = i9xx_get_initial_plane_config,
8136
	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8137 8138
};

8139
static const struct intel_display_funcs pch_split_display_funcs = {
8140 8141 8142 8143 8144
	.get_pipe_config = ilk_get_pipe_config,
	.crtc_enable = ilk_crtc_enable,
	.crtc_disable = ilk_crtc_disable,
	.commit_modeset_enables = intel_commit_modeset_enables,
	.get_initial_plane_config = i9xx_get_initial_plane_config,
8145
	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8146 8147
};

8148
static const struct intel_display_funcs vlv_display_funcs = {
8149 8150 8151 8152 8153
	.get_pipe_config = i9xx_get_pipe_config,
	.crtc_enable = valleyview_crtc_enable,
	.crtc_disable = i9xx_crtc_disable,
	.commit_modeset_enables = intel_commit_modeset_enables,
	.get_initial_plane_config = i9xx_get_initial_plane_config,
8154
	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8155 8156
};

8157
static const struct intel_display_funcs i9xx_display_funcs = {
8158 8159 8160 8161 8162
	.get_pipe_config = i9xx_get_pipe_config,
	.crtc_enable = i9xx_crtc_enable,
	.crtc_disable = i9xx_crtc_disable,
	.commit_modeset_enables = intel_commit_modeset_enables,
	.get_initial_plane_config = i9xx_get_initial_plane_config,
8163
	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8164 8165
};

8166 8167 8168 8169 8170
/**
 * intel_init_display_hooks - initialize the display modesetting hooks
 * @dev_priv: device private
 */
void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8171
{
8172
	if (DISPLAY_VER(dev_priv) >= 9) {
8173
		dev_priv->display.funcs.display = &skl_display_funcs;
8174
	} else if (HAS_DDI(dev_priv)) {
8175
		dev_priv->display.funcs.display = &ddi_display_funcs;
8176
	} else if (HAS_PCH_SPLIT(dev_priv)) {
8177
		dev_priv->display.funcs.display = &pch_split_display_funcs;
8178 8179
	} else if (IS_CHERRYVIEW(dev_priv) ||
		   IS_VALLEYVIEW(dev_priv)) {
8180
		dev_priv->display.funcs.display = &vlv_display_funcs;
8181
	} else {
8182
		dev_priv->display.funcs.display = &i9xx_display_funcs;
8183
	}
8184 8185
}

8186
int intel_initial_commit(struct drm_device *dev)
8187 8188 8189
{
	struct drm_atomic_state *state = NULL;
	struct drm_modeset_acquire_ctx ctx;
8190
	struct intel_crtc *crtc;
8191 8192 8193 8194 8195 8196 8197 8198 8199
	int ret = 0;

	state = drm_atomic_state_alloc(dev);
	if (!state)
		return -ENOMEM;

	drm_modeset_acquire_init(&ctx, 0);

	state->acquire_ctx = &ctx;
8200
	to_intel_atomic_state(state)->internal = true;
8201

8202
retry:
8203 8204 8205 8206
	for_each_intel_crtc(dev, crtc) {
		struct intel_crtc_state *crtc_state =
			intel_atomic_get_crtc_state(state, crtc);

8207 8208 8209 8210 8211
		if (IS_ERR(crtc_state)) {
			ret = PTR_ERR(crtc_state);
			goto out;
		}

8212
		if (crtc_state->hw.active) {
8213 8214
			struct intel_encoder *encoder;

8215
			ret = drm_atomic_add_affected_planes(state, &crtc->base);
8216 8217
			if (ret)
				goto out;
8218 8219 8220 8221 8222 8223 8224

			/*
			 * FIXME hack to force a LUT update to avoid the
			 * plane update forcing the pipe gamma on without
			 * having a proper LUT loaded. Remove once we
			 * have readout for pipe gamma enable.
			 */
8225
			crtc_state->uapi.color_mgmt_changed = true;
8226

8227 8228 8229 8230 8231 8232 8233 8234 8235
			for_each_intel_encoder_mask(dev, encoder,
						    crtc_state->uapi.encoder_mask) {
				if (encoder->initial_fastset_check &&
				    !encoder->initial_fastset_check(encoder, crtc_state)) {
					ret = drm_atomic_add_affected_connectors(state,
										 &crtc->base);
					if (ret)
						goto out;
				}
8236
			}
8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256
		}
	}

	ret = drm_atomic_commit(state);

out:
	if (ret == -EDEADLK) {
		drm_atomic_state_clear(state);
		drm_modeset_backoff(&ctx);
		goto retry;
	}

	drm_atomic_state_put(state);

	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);

	return ret;
}

8257 8258
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
8259
	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8260
	enum transcoder cpu_transcoder = (enum transcoder)pipe;
8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271
	/* 640x480@60Hz, ~25175 kHz */
	struct dpll clock = {
		.m1 = 18,
		.m2 = 7,
		.p1 = 13,
		.p2 = 4,
		.n = 2,
	};
	u32 dpll, fp;
	int i;

8272 8273
	drm_WARN_ON(&dev_priv->drm,
		    i9xx_calc_dpll_params(48000, &clock) != 25154);
8274

8275 8276 8277
	drm_dbg_kms(&dev_priv->drm,
		    "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
		    pipe_name(pipe), clock.vco, clock.dot);
8278 8279

	fp = i9xx_dpll_compute_fp(&clock);
8280
	dpll = DPLL_DVO_2X_MODE |
8281 8282 8283 8284 8285 8286
		DPLL_VGA_MODE_DIS |
		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
		PLL_P2_DIVIDE_BY_4 |
		PLL_REF_INPUT_DREFCLK |
		DPLL_VCO_ENABLE;

8287
	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
8288
		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
8289
	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
8290
		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8291
	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
8292
		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8293
	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
8294
		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
8295
	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
8296
		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8297
	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
8298
		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8299
	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
8300
		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8301

8302 8303 8304
	intel_de_write(dev_priv, FP0(pipe), fp);
	intel_de_write(dev_priv, FP1(pipe), fp);

8305 8306 8307 8308 8309
	/*
	 * Apparently we need to have VGA mode enabled prior to changing
	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
	 * dividers, even though the register value does change.
	 */
8310 8311 8312
	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
		       dpll & ~DPLL_VGA_MODE_DIS);
	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
8313 8314

	/* Wait for the clocks to stabilize. */
8315
	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
8316 8317 8318 8319 8320 8321 8322
	udelay(150);

	/* The pixel multiplier can only be updated once the
	 * DPLL is enabled and the clocks are stable.
	 *
	 * So write it again.
	 */
8323
	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
8324 8325 8326

	/* We do this three times for luck */
	for (i = 0; i < 3 ; i++) {
8327 8328
		intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
		intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
8329 8330 8331
		udelay(150); /* wait for warmup */
	}

8332 8333
	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
8334 8335

	intel_wait_for_pipe_scanline_moving(crtc);
8336 8337 8338 8339
}

void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
8340
	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8341

8342 8343
	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
		    pipe_name(pipe));
8344

8345
	drm_WARN_ON(&dev_priv->drm,
8346
		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE);
8347
	drm_WARN_ON(&dev_priv->drm,
8348
		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE);
8349
	drm_WARN_ON(&dev_priv->drm,
8350
		    intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE);
8351
	drm_WARN_ON(&dev_priv->drm,
8352
		    intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK);
8353
	drm_WARN_ON(&dev_priv->drm,
8354
		    intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
8355

8356 8357
	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
8358

8359
	intel_wait_for_pipe_scanline_stopped(crtc);
8360

8361 8362
	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
8363 8364
}

8365
void intel_hpd_poll_fini(struct drm_i915_private *i915)
8366 8367 8368 8369
{
	struct intel_connector *connector;
	struct drm_connector_list_iter conn_iter;

8370
	/* Kill all the work that may have been queued by hpd. */
8371
	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8372
	for_each_intel_connector_iter(connector, &conn_iter) {
8373 8374 8375
		if (connector->modeset_retry_work.func &&
		    cancel_work_sync(&connector->modeset_retry_work))
			drm_connector_put(&connector->base);
8376 8377 8378
		if (connector->hdcp.shim) {
			cancel_delayed_work_sync(&connector->hdcp.check_work);
			cancel_work_sync(&connector->hdcp.prop_work);
8379
		}
8380 8381 8382 8383
	}
	drm_connector_list_iter_end(&conn_iter);
}

8384 8385 8386 8387
bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
{
	return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
}