intel_drv.h 53.2 KB
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/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__

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#include <linux/async.h>
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#include <linux/i2c.h>
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#include <linux/hdmi.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
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#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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/**
 * _wait_for - magic (register) wait macro
 *
 * Does the right thing for modeset paths when run under kdgb or similar atomic
 * contexts. Note that it's important that we check the condition again after
 * having timed out, since the timeout could be due to preemption or similar and
 * we've never had a chance to check the condition before the timeout.
 */
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#define _wait_for(COND, MS, W) ({ \
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	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;	\
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	int ret__ = 0;							\
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	while (!(COND)) {						\
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		if (time_after(jiffies, timeout__)) {			\
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			if (!(COND))					\
				ret__ = -ETIMEDOUT;			\
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			break;						\
		}							\
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		if ((W) && drm_can_sleep()) {				\
			usleep_range((W)*1000, (W)*2000);		\
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		} else {						\
			cpu_relax();					\
		}							\
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	}								\
	ret__;								\
})

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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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#define wait_for_atomic_us(COND, US) _wait_for((COND), \
					       DIV_ROUND_UP((US), 1000), 0)
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#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
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/*
 * Display related stuff
 */

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */

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/* Maximum cursor sizes */
#define GEN2_CURSOR_WIDTH 64
#define GEN2_CURSOR_HEIGHT 64
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#define MAX_CURSOR_WIDTH 256
#define MAX_CURSOR_HEIGHT 256
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#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
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enum intel_output_type {
	INTEL_OUTPUT_UNUSED = 0,
	INTEL_OUTPUT_ANALOG = 1,
	INTEL_OUTPUT_DVO = 2,
	INTEL_OUTPUT_SDVO = 3,
	INTEL_OUTPUT_LVDS = 4,
	INTEL_OUTPUT_TVOUT = 5,
	INTEL_OUTPUT_HDMI = 6,
	INTEL_OUTPUT_DISPLAYPORT = 7,
	INTEL_OUTPUT_EDP = 8,
	INTEL_OUTPUT_DSI = 9,
	INTEL_OUTPUT_UNKNOWN = 10,
	INTEL_OUTPUT_DP_MST = 11,
};
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#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4

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#define INTEL_DSI_VIDEO_MODE	0
#define INTEL_DSI_COMMAND_MODE	1
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struct intel_framebuffer {
	struct drm_framebuffer base;
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	struct drm_i915_gem_object *obj;
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};

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struct intel_fbdev {
	struct drm_fb_helper helper;
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	struct intel_framebuffer *fb;
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	int preferred_bpp;
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};
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struct intel_encoder {
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	struct drm_encoder base;
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	enum intel_output_type type;
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	unsigned int cloneable;
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	void (*hot_plug)(struct intel_encoder *);
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	bool (*compute_config)(struct intel_encoder *,
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			       struct intel_crtc_state *);
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	void (*pre_pll_enable)(struct intel_encoder *);
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	void (*pre_enable)(struct intel_encoder *);
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	void (*enable)(struct intel_encoder *);
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	void (*mode_set)(struct intel_encoder *intel_encoder);
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	void (*disable)(struct intel_encoder *);
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	void (*post_disable)(struct intel_encoder *);
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	void (*post_pll_disable)(struct intel_encoder *);
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	/* Read out the current hw state of this connector, returning true if
	 * the encoder is active. If the encoder is enabled it also set the pipe
	 * it is connected to in the pipe parameter. */
	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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	/* Reconstructs the equivalent mode flags for the current hardware
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	 * state. This must be called _after_ display->get_pipe_config has
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	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
	 * be set correctly before calling this function. */
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	void (*get_config)(struct intel_encoder *,
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			   struct intel_crtc_state *pipe_config);
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	/*
	 * Called during system suspend after all pending requests for the
	 * encoder are flushed (for example for DP AUX transactions) and
	 * device interrupts are disabled.
	 */
	void (*suspend)(struct intel_encoder *);
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	int crtc_mask;
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	enum hpd_pin hpd_pin;
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};

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struct intel_panel {
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	struct drm_display_mode *fixed_mode;
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	struct drm_display_mode *downclock_mode;
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	int fitting_mode;
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	/* backlight */
	struct {
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		bool present;
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		u32 level;
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		u32 min;
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		u32 max;
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		bool enabled;
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		bool combination_mode;	/* gen 2/4 only */
		bool active_low_pwm;
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		/* PWM chip */
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		bool util_pin_active_low;	/* bxt+ */
		u8 controller;		/* bxt+ only */
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		struct pwm_device *pwm;

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		struct backlight_device *device;
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		/* Connector and platform specific backlight functions */
		int (*setup)(struct intel_connector *connector, enum pipe pipe);
		uint32_t (*get)(struct intel_connector *connector);
		void (*set)(struct intel_connector *connector, uint32_t level);
		void (*disable)(struct intel_connector *connector);
		void (*enable)(struct intel_connector *connector);
		uint32_t (*hz_to_pwm)(struct intel_connector *connector,
				      uint32_t hz);
		void (*power)(struct intel_connector *, bool enable);
	} backlight;
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};

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struct intel_connector {
	struct drm_connector base;
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	/*
	 * The fixed encoder this connector is connected to.
	 */
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	struct intel_encoder *encoder;
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	/* Reads out the current hw, returning true if the connector is enabled
	 * and active (i.e. dpms ON state). */
	bool (*get_hw_state)(struct intel_connector *);
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	/*
	 * Removes all interfaces through which the connector is accessible
	 * - like sysfs, debugfs entries -, so that no new operations can be
	 * started on the connector. Also makes sure all currently pending
	 * operations finish before returing.
	 */
	void (*unregister)(struct intel_connector *);

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	/* Panel info for eDP and LVDS */
	struct intel_panel panel;
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	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
	struct edid *edid;
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	struct edid *detect_edid;
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	/* since POLL and HPD connectors may use the same HPD line keep the native
	   state of connector->polled in case hotplug storm detection changes it */
	u8 polled;
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	void *port; /* store this opaque as its illegal to dereference it */

	struct intel_dp *mst_port;
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};

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typedef struct dpll {
	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
} intel_clock_t;

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struct intel_atomic_state {
	struct drm_atomic_state base;

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	unsigned int cdclk;
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	bool dpll_set;
	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
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	struct intel_wm_config wm_config;
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};

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struct intel_plane_state {
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	struct drm_plane_state base;
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	struct drm_rect src;
	struct drm_rect dst;
	struct drm_rect clip;
	bool visible;
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	/*
	 * scaler_id
	 *    = -1 : not using a scaler
	 *    >=  0 : using a scalers
	 *
	 * plane requiring a scaler:
	 *   - During check_plane, its bit is set in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 *   - scaler_id indicates the scaler it got assigned.
	 *
	 * plane doesn't require a scaler:
	 *   - this can happen when scaling is no more required or plane simply
	 *     got disabled.
	 *   - During check_plane, corresponding bit is reset in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 */
	int scaler_id;
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	struct drm_intel_sprite_colorkey ckey;
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	/* async flip related structures */
	struct drm_i915_gem_request *wait_req;
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};

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struct intel_initial_plane_config {
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	struct intel_framebuffer *fb;
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	unsigned int tiling;
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	int size;
	u32 base;
};

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#define SKL_MIN_SRC_W 8
#define SKL_MAX_SRC_W 4096
#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
#define SKL_MAX_DST_W 4096
#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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struct intel_scaler {
	int in_use;
	uint32_t mode;
};

struct intel_crtc_scaler_state {
#define SKL_NUM_SCALERS 2
	struct intel_scaler scalers[SKL_NUM_SCALERS];

	/*
	 * scaler_users: keeps track of users requesting scalers on this crtc.
	 *
	 *     If a bit is set, a user is using a scaler.
	 *     Here user can be a plane or crtc as defined below:
	 *       bits 0-30 - plane (bit position is index from drm_plane_index)
	 *       bit 31    - crtc
	 *
	 * Instead of creating a new index to cover planes and crtc, using
	 * existing drm_plane_index for planes which is well less than 31
	 * planes and bit 31 for crtc. This should be fine to cover all
	 * our platforms.
	 *
	 * intel_atomic_setup_scalers will setup available scalers to users
	 * requesting scalers. It will gracefully fail if request exceeds
	 * avilability.
	 */
#define SKL_CRTC_INDEX 31
	unsigned scaler_users;

	/* scaler used by crtc for panel fitting purpose */
	int scaler_id;
};

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/* drm_mode->private_flags */
#define I915_MODE_FLAG_INHERITED 1

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struct intel_pipe_wm {
	struct intel_wm_level wm[5];
	uint32_t linetime;
	bool fbc_wm_enabled;
	bool pipe_enabled;
	bool sprites_enabled;
	bool sprites_scaled;
};

struct skl_pipe_wm {
	struct skl_wm_level wm[8];
	struct skl_wm_level trans_wm;
	uint32_t linetime;
};

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struct intel_crtc_state {
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	struct drm_crtc_state base;

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	/**
	 * quirks - bitfield with hw state readout quirks
	 *
	 * For various reasons the hw state readout code might not be able to
	 * completely faithfully read out the current state. These cases are
	 * tracked with quirk flags so that fastboot and state checker can act
	 * accordingly.
	 */
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */
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	unsigned long quirks;

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	bool update_pipe; /* can a fast modeset be performed? */
	bool disable_cxsr;
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	bool wm_changed; /* watermarks are updated */
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	/* Pipe source size (ie. panel fitter input size)
	 * All planes will be positioned inside this space,
	 * and get clipped at the edges. */
	int pipe_src_w, pipe_src_h;

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	/* Whether to set up the PCH/FDI. Note that we never allow sharing
	 * between pch encoders and cpu encoders. */
	bool has_pch_encoder;
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	/* Are we sending infoframes on the attached port */
	bool has_infoframe;

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	/* CPU Transcoder for the pipe. Currently this can only differ from the
	 * pipe on Haswell (where we have a special eDP transcoder). */
	enum transcoder cpu_transcoder;

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	/*
	 * Use reduced/limited/broadcast rbg range, compressing from the full
	 * range fed into the crtcs.
	 */
	bool limited_color_range;

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	/* DP has a bunch of special case unfortunately, so mark the pipe
	 * accordingly. */
	bool has_dp_encoder;
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	/* DSI has special cases */
	bool has_dsi_encoder;

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	/* Whether we should send NULL infoframes. Required for audio. */
	bool has_hdmi_sink;

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	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
	 * has_dp_encoder is set. */
	bool has_audio;

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	/*
	 * Enable dithering, used when the selected pipe bpp doesn't match the
	 * plane bpp.
	 */
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	bool dither;
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	/* Controls for the clock computation, to override various stages. */
	bool clock_set;

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	/* SDVO TV has a bunch of special case. To make multifunction encoders
	 * work correctly, we need to track this at runtime.*/
	bool sdvo_tv_clock;

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	/*
	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
	 * required. This is set in the 2nd loop of calling encoder's
	 * ->compute_config if the first pick doesn't work out.
	 */
	bool bw_constrained;

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	/* Settings for the intel dpll used on pretty much everything but
	 * haswell. */
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	struct dpll dpll;
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	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
	enum intel_dpll_id shared_dpll;

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	/*
	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
	 * - enum skl_dpll on SKL
	 */
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	uint32_t ddi_pll_sel;

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	/* Actual register state of the dpll, for shared dpll cross-checking. */
	struct intel_dpll_hw_state dpll_hw_state;

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	int pipe_bpp;
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	struct intel_link_m_n dp_m_n;
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	/* m2_n2 for eDP downclock */
	struct intel_link_m_n dp_m2_n2;
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	bool has_drrs;
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	/*
	 * Frequence the dpll for the port should run at. Differs from the
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	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
	 * already multiplied by pixel_multiplier.
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	 */
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	int port_clock;

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	/* Used by SDVO (and if we ever fix it, HDMI). */
	unsigned pixel_multiplier;
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	uint8_t lane_count;

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	/* Panel fitter controls for gen2-gen4 + VLV */
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	struct {
		u32 control;
		u32 pgm_ratios;
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		u32 lvds_border_bits;
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	} gmch_pfit;

	/* Panel fitter placement and size for Ironlake+ */
	struct {
		u32 pos;
		u32 size;
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		bool enabled;
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		bool force_thru;
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	} pch_pfit;
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	/* FDI configuration, only valid if has_pch_encoder is set. */
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	int fdi_lanes;
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	struct intel_link_m_n fdi_m_n;
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	bool ips_enabled;
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	bool double_wide;
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	bool dp_encoder_is_mst;
	int pbn;
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	struct intel_crtc_scaler_state scaler_state;
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	/* w/a for waiting 2 vblanks during crtc enable */
	enum pipe hsw_workaround_pipe;
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	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
	bool disable_lp_wm;
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	struct {
		/*
		 * optimal watermarks, programmed post-vblank when this state
		 * is committed
		 */
		union {
			struct intel_pipe_wm ilk;
			struct skl_pipe_wm skl;
		} optimal;
	} wm;
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};

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struct vlv_wm_state {
	struct vlv_pipe_wm wm[3];
	struct vlv_sr_wm sr[3];
	uint8_t num_active_planes;
	uint8_t num_levels;
	uint8_t level;
	bool cxsr;
};

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struct intel_mmio_flip {
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	struct work_struct work;
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	struct drm_i915_private *i915;
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	struct drm_i915_gem_request *req;
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	struct intel_crtc *crtc;
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	unsigned int rotation;
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};

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/*
 * Tracking of operations that need to be performed at the beginning/end of an
 * atomic commit, outside the atomic section where interrupts are disabled.
 * These are generally operations that grab mutexes or might otherwise sleep
 * and thus can't be run with interrupts disabled.
 */
struct intel_crtc_atomic_commit {
	/* Sleepable operations to perform before commit */
	bool disable_fbc;
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	bool disable_ips;
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	bool pre_disable_primary;

	/* Sleepable operations to perform after commit */
	unsigned fb_bits;
	bool wait_vblank;
	bool update_fbc;
	bool post_enable_primary;
	unsigned update_sprite_watermarks;
};

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struct intel_crtc {
	struct drm_crtc base;
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	enum pipe pipe;
	enum plane plane;
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	u8 lut_r[256], lut_g[256], lut_b[256];
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	/*
	 * Whether the crtc and the connected output pipeline is active. Implies
	 * that crtc->enabled is set, i.e. the current mode configuration has
	 * some outputs connected to this crtc.
	 */
	bool active;
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	unsigned long enabled_power_domains;
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	bool lowfreq_avail;
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	struct intel_overlay *overlay;
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	struct intel_unpin_work *unpin_work;
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	atomic_t unpin_work_count;

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	/* Display surface base address adjustement for pageflips. Note that on
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
	 * handled in the hw itself (with the TILEOFF register). */
	unsigned long dspaddr_offset;
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	int adjusted_x;
	int adjusted_y;
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	uint32_t cursor_addr;
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	uint32_t cursor_cntl;
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	uint32_t cursor_size;
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	uint32_t cursor_base;
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	struct intel_crtc_state *config;
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	/* reset counter value when the last flip was submitted */
	unsigned int reset_counter;
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	/* Access to these should be protected by dev_priv->irq_lock. */
	bool cpu_fifo_underrun_disabled;
	bool pch_fifo_underrun_disabled;
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	/* per-pipe watermark state */
	struct {
		/* watermarks currently being used  */
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		union {
			struct intel_pipe_wm ilk;
			struct skl_pipe_wm skl;
		} active;
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		/* allow CxSR on this pipe */
		bool cxsr_allowed;
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	} wm;
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	int scanline_offset;
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	struct {
		unsigned start_vbl_count;
		ktime_t start_vbl_time;
		int min_vbl, max_vbl;
		int scanline_start;
	} debug;
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	struct intel_crtc_atomic_commit atomic;
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	/* scalers available on this crtc */
	int num_scalers;
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	struct vlv_wm_state wm_state;
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};

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struct intel_plane_wm_parameters {
	uint32_t horiz_pixels;
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	uint32_t vert_pixels;
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	/*
	 *   For packed pixel formats:
	 *     bytes_per_pixel - holds bytes per pixel
	 *   For planar pixel formats:
	 *     bytes_per_pixel - holds bytes per pixel for uv-plane
	 *     y_bytes_per_pixel - holds bytes per pixel for y-plane
	 */
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	uint8_t bytes_per_pixel;
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	uint8_t y_bytes_per_pixel;
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	bool enabled;
	bool scaled;
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	u64 tiling;
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	unsigned int rotation;
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	uint16_t fifo_size;
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};

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struct intel_plane {
	struct drm_plane base;
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	int plane;
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	enum pipe pipe;
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	bool can_scale;
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	int max_downscale;
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	uint32_t frontbuffer_bit;
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	/* Since we need to change the watermarks before/after
	 * enabling/disabling the planes, we need to store the parameters here
	 * as the other pieces of the struct may not reflect the values we want
	 * for the watermark calculations. Currently only Haswell uses this.
	 */
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	struct intel_plane_wm_parameters wm;
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	/*
	 * NOTE: Do not place new plane state fields here (e.g., when adding
	 * new plane properties).  New runtime state should now be placed in
	 * the intel_plane_state structure and accessed via drm_plane->state.
	 */

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	void (*update_plane)(struct drm_plane *plane,
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			     struct drm_crtc *crtc,
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			     struct drm_framebuffer *fb,
			     int crtc_x, int crtc_y,
			     unsigned int crtc_w, unsigned int crtc_h,
			     uint32_t x, uint32_t y,
			     uint32_t src_w, uint32_t src_h);
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	void (*disable_plane)(struct drm_plane *plane,
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			      struct drm_crtc *crtc);
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	int (*check_plane)(struct drm_plane *plane,
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			   struct intel_crtc_state *crtc_state,
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			   struct intel_plane_state *state);
	void (*commit_plane)(struct drm_plane *plane,
			     struct intel_plane_state *state);
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};

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struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};

struct cxsr_latency {
	int is_desktop;
	int is_ddr3;
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};

688
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
689
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
690
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
691
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
692
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
693
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
694
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
695
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
696
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
697

698
struct intel_hdmi {
699
	i915_reg_t hdmi_reg;
700
	int ddc_bus;
701
	bool limited_color_range;
702
	bool color_range_auto;
703 704 705
	bool has_hdmi_sink;
	bool has_audio;
	enum hdmi_force_audio force_audio;
706
	bool rgb_quant_range_selectable;
707
	enum hdmi_picture_aspect aspect_ratio;
708
	struct intel_connector *attached_connector;
709
	void (*write_infoframe)(struct drm_encoder *encoder,
710
				enum hdmi_infoframe_type type,
711
				const void *frame, ssize_t len);
712
	void (*set_infoframes)(struct drm_encoder *encoder,
713
			       bool enable,
714
			       const struct drm_display_mode *adjusted_mode);
715 716
	bool (*infoframe_enabled)(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config);
717 718
};

719
struct intel_dp_mst_encoder;
720
#define DP_MAX_DOWNSTREAM_PORTS		0x10
721

722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741
/*
 * enum link_m_n_set:
 *	When platform provides two set of M_N registers for dp, we can
 *	program them and switch between them incase of DRRS.
 *	But When only one such register is provided, we have to program the
 *	required divider value on that registers itself based on the DRRS state.
 *
 * M1_N1	: Program dp_m_n on M1_N1 registers
 *			  dp_m2_n2 on M2_N2 registers (If supported)
 *
 * M2_N2	: Program dp_m2_n2 on M1_N1 registers
 *			  M2_N2 registers are not supported
 */

enum link_m_n_set {
	/* Sets the m1_n1 and m2_n2 */
	M1_N1 = 0,
	M2_N2
};

742
struct intel_dp {
743 744 745
	i915_reg_t output_reg;
	i915_reg_t aux_ch_ctl_reg;
	i915_reg_t aux_ch_data_reg[5];
746
	uint32_t DP;
747 748
	int link_rate;
	uint8_t lane_count;
749 750
	bool has_audio;
	enum hdmi_force_audio force_audio;
751
	bool limited_color_range;
752
	bool color_range_auto;
753
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
754
	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
755
	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
756 757 758
	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
	uint8_t num_sink_rates;
	int sink_rates[DP_MAX_SUPPORTED_RATES];
759
	struct drm_dp_aux aux;
760 761 762 763 764 765 766 767
	uint8_t train_set[4];
	int panel_power_up_delay;
	int panel_power_down_delay;
	int panel_power_cycle_delay;
	int backlight_on_delay;
	int backlight_off_delay;
	struct delayed_work panel_vdd_work;
	bool want_panel_vdd;
768 769 770
	unsigned long last_power_cycle;
	unsigned long last_power_on;
	unsigned long last_backlight_off;
771

772 773
	struct notifier_block edp_notifier;

774 775 776 777 778
	/*
	 * Pipe whose power sequencer is currently locked into
	 * this port. Only relevant on VLV/CHV.
	 */
	enum pipe pps_pipe;
779
	struct edp_power_seq pps_delays;
780

781 782 783 784
	bool can_mst; /* this port supports mst */
	bool is_mst;
	int active_mst_links;
	/* connector directly attached - won't be use for modeset in mst world */
785
	struct intel_connector *attached_connector;
786

787 788 789 790
	/* mst connector list */
	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
	struct drm_dp_mst_topology_mgr mst_mgr;

791
	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
792 793 794 795 796 797 798 799
	/*
	 * This function returns the value we have to program the AUX_CTL
	 * register with to kick off an AUX transaction.
	 */
	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
				     bool has_aux_irq,
				     int send_bytes,
				     uint32_t aux_clock_divider);
800 801 802 803

	/* This is called before a link training is starterd */
	void (*prepare_link_retrain)(struct intel_dp *intel_dp);

804
	bool train_set_valid;
805 806 807

	/* Displayport compliance testing */
	unsigned long compliance_test_type;
808 809
	unsigned long compliance_test_data;
	bool compliance_test_active;
810 811
};

812 813
struct intel_digital_port {
	struct intel_encoder base;
814
	enum port port;
815
	u32 saved_port_bits;
816 817
	struct intel_dp dp;
	struct intel_hdmi hdmi;
818
	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
819
	bool release_cl2_override;
820 821
	/* for communication with audio component; protected by av_mutex */
	const struct drm_connector *audio_connector;
822 823
};

824 825 826 827 828 829 830
struct intel_dp_mst_encoder {
	struct intel_encoder base;
	enum pipe pipe;
	struct intel_digital_port *primary;
	void *port; /* store this opaque as its illegal to dereference it */
};

831
static inline enum dpio_channel
832 833 834 835
vlv_dport_to_channel(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
836
	case PORT_D:
837
		return DPIO_CH0;
838
	case PORT_C:
839
		return DPIO_CH1;
840 841 842 843 844
	default:
		BUG();
	}
}

845 846 847 848 849 850 851 852 853 854 855 856 857 858 859
static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
	case PORT_C:
		return DPIO_PHY0;
	case PORT_D:
		return DPIO_PHY1;
	default:
		BUG();
	}
}

static inline enum dpio_channel
860 861 862 863 864 865 866 867 868 869 870 871 872
vlv_pipe_to_channel(enum pipe pipe)
{
	switch (pipe) {
	case PIPE_A:
	case PIPE_C:
		return DPIO_CH0;
	case PIPE_B:
		return DPIO_CH1;
	default:
		BUG();
	}
}

873 874 875 876 877 878 879
static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->pipe_to_crtc_mapping[pipe];
}

880 881 882 883 884 885 886
static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->plane_to_crtc_mapping[plane];
}

887 888
struct intel_unpin_work {
	struct work_struct work;
889
	struct drm_crtc *crtc;
890
	struct drm_framebuffer *old_fb;
891
	struct drm_i915_gem_object *pending_flip_obj;
892
	struct drm_pending_vblank_event *event;
893 894 895 896
	atomic_t pending;
#define INTEL_FLIP_INACTIVE	0
#define INTEL_FLIP_PENDING	1
#define INTEL_FLIP_COMPLETE	2
897 898
	u32 flip_count;
	u32 gtt_offset;
899
	struct drm_i915_gem_request *flip_queued_req;
900 901
	u32 flip_queued_vblank;
	u32 flip_ready_vblank;
902 903 904
	bool enable_stall_check;
};

905 906 907 908 909
struct intel_load_detect_pipe {
	struct drm_framebuffer *release_fb;
	bool load_detect_temp;
	int dpms_mode;
};
910

911 912
static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector *connector)
913 914 915 916
{
	return to_intel_connector(connector)->encoder;
}

917 918 919 920
static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_digital_port, base.base);
921 922
}

923 924 925 926 927 928
static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
}

929 930 931
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
	return &enc_to_dig_port(encoder)->dp;
932 933 934 935 936 937 938 939 940 941 942 943
}

static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp *intel_dp)
{
	return container_of(intel_dp, struct intel_digital_port, dp);
}

static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
944 945
}

946 947 948 949 950 951 952 953
/*
 * Returns the number of planes for this pipe, ie the number of sprites + 1
 * (primary plane). This doesn't count the cursor plane then.
 */
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
{
	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
}
954

955
/* intel_fifo_underrun.c */
956
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
957
					   enum pipe pipe, bool enable);
958
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
959 960
					   enum transcoder pch_transcoder,
					   bool enable);
961 962 963 964
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe);
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum transcoder pch_transcoder);
965 966
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
967 968

/* i915_irq.c */
969 970 971 972
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
973
void gen6_reset_rps_interrupts(struct drm_device *dev);
974 975
void gen6_enable_rps_interrupts(struct drm_device *dev);
void gen6_disable_rps_interrupts(struct drm_device *dev);
976
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
977 978
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
979 980 981 982 983 984
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
{
	/*
	 * We only use drm_irq_uninstall() at unload and VT switch, so
	 * this is the only thing we need to check.
	 */
985
	return dev_priv->pm.irqs_enabled;
986 987
}

988
int intel_get_crtc_scanline(struct intel_crtc *crtc);
989 990
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask);
991 992

/* intel_crt.c */
993
void intel_crt_init(struct drm_device *dev);
994 995 996


/* intel_ddi.c */
997 998
void intel_ddi_clk_select(struct intel_encoder *encoder,
			  const struct intel_crtc_state *pipe_config);
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009
void intel_prepare_ddi(struct drm_device *dev);
void hsw_fdi_link_train(struct drm_crtc *crtc);
void intel_ddi_init(struct drm_device *dev, enum port port);
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
void intel_ddi_pll_init(struct drm_device *dev);
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder);
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1010 1011
bool intel_ddi_pll_select(struct intel_crtc *crtc,
			  struct intel_crtc_state *crtc_state);
1012
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1013
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1014 1015 1016
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
void intel_ddi_get_config(struct intel_encoder *encoder,
1017
			  struct intel_crtc_state *pipe_config);
1018 1019
struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1020

1021
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1022
void intel_ddi_clock_get(struct intel_encoder *encoder,
1023
			 struct intel_crtc_state *pipe_config);
1024
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1025
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1026

1027
/* intel_frontbuffer.c */
1028
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1029
			     enum fb_op_origin origin);
1030 1031 1032 1033 1034
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
				    unsigned frontbuffer_bits);
void intel_frontbuffer_flip_complete(struct drm_device *dev,
				     unsigned frontbuffer_bits);
void intel_frontbuffer_flip(struct drm_device *dev,
1035
			    unsigned frontbuffer_bits);
1036 1037 1038 1039
unsigned int intel_fb_align_height(struct drm_device *dev,
				   unsigned int height,
				   uint32_t pixel_format,
				   uint64_t fb_format_modifier);
1040 1041
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
			enum fb_op_origin origin);
1042 1043
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
			      uint32_t pixel_format);
1044

1045 1046
/* intel_audio.c */
void intel_init_audio(struct drm_device *dev);
1047 1048
void intel_audio_codec_enable(struct intel_encoder *encoder);
void intel_audio_codec_disable(struct intel_encoder *encoder);
1049 1050
void i915_audio_component_init(struct drm_i915_private *dev_priv);
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1051

1052
/* intel_display.c */
1053
extern const struct drm_plane_funcs intel_plane_funcs;
1054 1055
bool intel_has_pending_fb_unpin(struct drm_device *dev);
int intel_pch_rawclk(struct drm_device *dev);
1056
int intel_hrawclk(struct drm_device *dev);
1057
void intel_mark_busy(struct drm_device *dev);
1058 1059
void intel_mark_idle(struct drm_device *dev);
void intel_crtc_restore_mode(struct drm_crtc *crtc);
1060
int intel_display_suspend(struct drm_device *dev);
1061
void intel_encoder_destroy(struct drm_encoder *encoder);
1062 1063
int intel_connector_init(struct intel_connector *);
struct intel_connector *intel_connector_alloc(void);
1064 1065 1066 1067 1068 1069
bool intel_connector_get_hw_state(struct intel_connector *connector);
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder);
struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc);
1070
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1071 1072
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
1073 1074
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe);
1075
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1076 1077 1078 1079 1080
static inline void
intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
	drm_wait_one_vblank(dev, pipe);
}
1081 1082 1083 1084 1085 1086 1087 1088 1089
static inline void
intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
{
	const struct intel_crtc *crtc =
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));

	if (crtc->active)
		intel_wait_for_vblank(dev, pipe);
}
1090
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1091
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1092 1093
			 struct intel_digital_port *dport,
			 unsigned int expected_mask);
1094 1095
bool intel_get_load_detect_pipe(struct drm_connector *connector,
				struct drm_display_mode *mode,
1096 1097
				struct intel_load_detect_pipe *old,
				struct drm_modeset_acquire_ctx *ctx);
1098
void intel_release_load_detect_pipe(struct drm_connector *connector,
1099 1100
				    struct intel_load_detect_pipe *old,
				    struct drm_modeset_acquire_ctx *ctx);
1101 1102
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
			       struct drm_framebuffer *fb,
1103
			       const struct drm_plane_state *plane_state);
1104 1105
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
1106 1107 1108 1109 1110
			   struct drm_mode_fb_cmd2 *mode_cmd,
			   struct drm_i915_gem_object *obj);
void intel_prepare_page_flip(struct drm_device *dev, int plane);
void intel_finish_page_flip(struct drm_device *dev, int pipe);
void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1111
void intel_check_page_flip(struct drm_device *dev, int pipe);
1112
int intel_prepare_plane_fb(struct drm_plane *plane,
1113
			   const struct drm_plane_state *new_state);
1114
void intel_cleanup_plane_fb(struct drm_plane *plane,
1115
			    const struct drm_plane_state *old_state);
1116 1117 1118 1119 1120 1121 1122 1123
int intel_plane_atomic_get_property(struct drm_plane *plane,
				    const struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t *val);
int intel_plane_atomic_set_property(struct drm_plane *plane,
				    struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t val);
1124 1125
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
				    struct drm_plane_state *plane_state);
1126

1127 1128
unsigned int
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1129
		  uint64_t fb_format_modifier, unsigned int plane);
1130

1131 1132 1133 1134 1135 1136
static inline bool
intel_rotation_90_or_270(unsigned int rotation)
{
	return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
}

1137 1138 1139
void intel_create_rotation_property(struct drm_device *dev,
					struct intel_plane *plane);

1140
/* shared dpll functions */
1141
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1142 1143 1144 1145 1146
void assert_shared_dpll(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll,
			bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1147 1148
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
						struct intel_crtc_state *state);
1149

1150 1151 1152 1153
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
		      const struct dpll *dpll);
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);

1154
/* modesetting asserts */
1155 1156
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
			   enum pipe pipe);
1157 1158 1159 1160 1161 1162 1163 1164
void assert_pll(struct drm_i915_private *dev_priv,
		enum pipe pipe, bool state);
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1165
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1166 1167
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1168 1169
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
					     int *x, int *y,
1170 1171 1172
					     unsigned int tiling_mode,
					     unsigned int bpp,
					     unsigned int pitch);
1173 1174
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
1175 1176
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1177 1178
void broxton_init_cdclk(struct drm_device *dev);
void broxton_uninit_cdclk(struct drm_device *dev);
1179 1180
void broxton_ddi_phy_init(struct drm_device *dev);
void broxton_ddi_phy_uninit(struct drm_device *dev);
1181 1182
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1183
void skl_init_cdclk(struct drm_i915_private *dev_priv);
1184
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1185
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1186 1187
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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		      struct intel_crtc_state *pipe_config);
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void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
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int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
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ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
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				int dotclock);
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
			intel_clock_t *best_clock);
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int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);

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bool intel_crtc_active(struct drm_crtc *crtc);
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void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
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enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
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enum intel_display_power_domain
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
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void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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				 struct intel_crtc_state *pipe_config);
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void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
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u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
			   struct drm_i915_gem_object *obj,
			   unsigned int plane);
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u32 skl_plane_ctl_format(uint32_t pixel_format);
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
u32 skl_plane_ctl_rotation(unsigned int rotation);
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/* intel_csr.c */
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void intel_csr_ucode_init(struct drm_i915_private *);
void intel_csr_load_program(struct drm_i915_private *);
void intel_csr_ucode_fini(struct drm_i915_private *);
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/* intel_dp.c */
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void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
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bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			     struct intel_connector *intel_connector);
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void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config);
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_destroy(struct drm_encoder *encoder);
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int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
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bool intel_dp_compute_config(struct intel_encoder *encoder,
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			     struct intel_crtc_state *pipe_config);
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bool intel_dp_is_edp(struct drm_device *dev, enum port port);
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enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
				  bool long_hpd);
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void intel_edp_backlight_on(struct intel_dp *intel_dp);
void intel_edp_backlight_off(struct intel_dp *intel_dp);
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void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
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void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp);
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void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
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int intel_dp_max_link_rate(struct intel_dp *intel_dp);
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int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
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void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
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void intel_plane_destroy(struct drm_plane *plane);
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void intel_edp_drrs_enable(struct intel_dp *intel_dp);
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
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void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
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bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
					 struct intel_digital_port *port);
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void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
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void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat);
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp);
uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select);
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bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
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bool
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);

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/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
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/* intel_dsi.c */
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void intel_dsi_init(struct drm_device *dev);
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/* intel_dvo.c */
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void intel_dvo_init(struct drm_device *dev);
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/* legacy fbdev emulation in intel_fbdev.c */
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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extern int intel_fbdev_init(struct drm_device *dev);
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extern void intel_fbdev_initial_config_async(struct drm_device *dev);
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extern void intel_fbdev_fini(struct drm_device *dev);
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extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
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extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
extern void intel_fbdev_restore_mode(struct drm_device *dev);
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#else
static inline int intel_fbdev_init(struct drm_device *dev)
{
	return 0;
}
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static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
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{
}

static inline void intel_fbdev_fini(struct drm_device *dev)
{
}

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static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
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{
}

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static inline void intel_fbdev_restore_mode(struct drm_device *dev)
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{
}
#endif
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/* intel_fbc.c */
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bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
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void intel_fbc_deactivate(struct intel_crtc *crtc);
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void intel_fbc_update(struct intel_crtc *crtc);
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void intel_fbc_init(struct drm_i915_private *dev_priv);
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void intel_fbc_enable(struct intel_crtc *crtc);
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void intel_fbc_disable(struct drm_i915_private *dev_priv);
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void intel_fbc_disable_crtc(struct intel_crtc *crtc);
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void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits,
			  enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
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		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
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void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
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/* intel_hdmi.c */
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void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
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void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector);
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
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			       struct intel_crtc_state *pipe_config);
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/* intel_lvds.c */
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void intel_lvds_init(struct drm_device *dev);
bool intel_is_dual_link_lvds(struct drm_device *dev);
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/* intel_modes.c */
int intel_connector_update_modes(struct drm_connector *connector,
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				 struct edid *edid);
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int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
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void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
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void intel_attach_aspect_ratio_property(struct drm_connector *connector);
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/* intel_overlay.c */
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void intel_setup_overlay(struct drm_device *dev);
void intel_cleanup_overlay(struct drm_device *dev);
int intel_overlay_switch_off(struct intel_overlay *overlay);
int intel_overlay_put_image(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
int intel_overlay_attrs(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
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void intel_overlay_reset(struct drm_i915_private *dev_priv);
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/* intel_panel.c */
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int intel_panel_init(struct intel_panel *panel,
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		     struct drm_display_mode *fixed_mode,
		     struct drm_display_mode *downclock_mode);
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void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
			    struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc *crtc,
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			     struct intel_crtc_state *pipe_config,
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			     int fitting_mode);
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
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			      struct intel_crtc_state *pipe_config,
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			      int fitting_mode);
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void intel_panel_set_backlight_acpi(struct intel_connector *connector,
				    u32 level, u32 max);
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int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
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void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector);
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void intel_panel_destroy_backlight(struct drm_connector *connector);
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enum drm_connector_status intel_panel_detect(struct drm_device *dev);
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extern struct drm_display_mode *intel_find_panel_downclock(
				struct drm_device *dev,
				struct drm_display_mode *fixed_mode,
				struct drm_connector *connector);
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void intel_backlight_register(struct drm_device *dev);
void intel_backlight_unregister(struct drm_device *dev);

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/* intel_psr.c */
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
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			  unsigned frontbuffer_bits);
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void intel_psr_flush(struct drm_device *dev,
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		     unsigned frontbuffer_bits,
		     enum fb_op_origin origin);
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void intel_psr_init(struct drm_device *dev);
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void intel_psr_single_frame_update(struct drm_device *dev,
				   unsigned frontbuffer_bits);
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/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
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void intel_power_domains_fini(struct drm_i915_private *);
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void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
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void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
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void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
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const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
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bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				    enum intel_display_power_domain domain);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				      enum intel_display_power_domain domain);
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void intel_display_power_get(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
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bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
					enum intel_display_power_domain domain);
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void intel_display_power_put(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
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static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
{
	WARN_ONCE(dev_priv->pm.suspended,
		  "Device suspended during HW access\n");
}

static inline void
assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
{
	assert_rpm_device_not_suspended(dev_priv);
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	/* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
	 * too much noise. */
	if (!atomic_read(&dev_priv->pm.wakeref_count))
		DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
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}

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static inline int
assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
{
	int seq = atomic_read(&dev_priv->pm.atomic_seq);

	assert_rpm_wakelock_held(dev_priv);

	return seq;
}

static inline void
assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
{
	WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
		  "HW access outside of RPM atomic section\n");
}

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/**
 * disable_rpm_wakeref_asserts - disable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function disable asserts that check if we hold an RPM wakelock
 * reference, while keeping the device-not-suspended checks still enabled.
 * It's meant to be used only in special circumstances where our rule about
 * the wakelock refcount wrt. the device power state doesn't hold. According
 * to this rule at any point where we access the HW or want to keep the HW in
 * an active state we must hold an RPM wakelock reference acquired via one of
 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
 * forcewake release timer, and the GPU RPS and hangcheck works. All other
 * users should avoid using this function.
 *
 * Any calls to this function must have a symmetric call to
 * enable_rpm_wakeref_asserts().
 */
static inline void
disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_inc(&dev_priv->pm.wakeref_count);
}

/**
 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function re-enables the RPM assert checks after disabling them with
 * disable_rpm_wakeref_asserts. It's meant to be used only in special
 * circumstances otherwise its use should be avoided.
 *
 * Any calls to this function must have a symmetric call to
 * disable_rpm_wakeref_asserts().
 */
static inline void
enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_dec(&dev_priv->pm.wakeref_count);
}

/* TODO: convert users of these to rely instead on proper RPM refcounting */
#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
	disable_rpm_wakeref_asserts(dev_priv)

#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
	enable_rpm_wakeref_asserts(dev_priv)

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void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
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bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
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void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);

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void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);

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void chv_phy_powergate_lanes(struct intel_encoder *encoder,
			     bool override, unsigned int mask);
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bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
			  enum dpio_channel ch, bool override);
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/* intel_pm.c */
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void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
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int ilk_wm_max_level(const struct drm_device *dev);
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void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
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void intel_pm_setup(struct drm_device *dev);
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void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
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void intel_init_gt_powersave(struct drm_device *dev);
void intel_cleanup_gt_powersave(struct drm_device *dev);
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void intel_enable_gt_powersave(struct drm_device *dev);
void intel_disable_gt_powersave(struct drm_device *dev);
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void intel_suspend_gt_powersave(struct drm_device *dev);
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void intel_reset_gt_powersave(struct drm_device *dev);
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void gen6_update_ring_freq(struct drm_device *dev);
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void gen6_rps_busy(struct drm_i915_private *dev_priv);
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
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void gen6_rps_idle(struct drm_i915_private *dev_priv);
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void gen6_rps_boost(struct drm_i915_private *dev_priv,
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		    struct intel_rps_client *rps,
		    unsigned long submitted);
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void intel_queue_rps_boost_for_request(struct drm_device *dev,
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				       struct drm_i915_gem_request *req);
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void vlv_wm_get_hw_state(struct drm_device *dev);
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void ilk_wm_get_hw_state(struct drm_device *dev);
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void skl_wm_get_hw_state(struct drm_device *dev);
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
			  struct skl_ddb_allocation *ddb /* out */);
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uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
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/* intel_sdvo.c */
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bool intel_sdvo_init(struct drm_device *dev,
		     i915_reg_t reg, enum port port);
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/* intel_sprite.c */
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int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
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void intel_pipe_update_start(struct intel_crtc *crtc);
void intel_pipe_update_end(struct intel_crtc *crtc);
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/* intel_tv.c */
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void intel_tv_init(struct drm_device *dev);
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/* intel_atomic.c */
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int intel_connector_atomic_get_property(struct drm_connector *connector,
					const struct drm_connector_state *state,
					struct drm_property *property,
					uint64_t *val);
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struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
			       struct drm_crtc_state *state);
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struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *);
struct intel_shared_dpll_config *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);

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static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
			    struct intel_crtc *crtc)
{
	struct drm_crtc_state *crtc_state;
	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
	if (IS_ERR(crtc_state))
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		return ERR_CAST(crtc_state);
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	return to_intel_crtc_state(crtc_state);
}
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int intel_atomic_setup_scalers(struct drm_device *dev,
	struct intel_crtc *intel_crtc,
	struct intel_crtc_state *crtc_state);
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/* intel_atomic_plane.c */
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struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
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struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
void intel_plane_destroy_state(struct drm_plane *plane,
			       struct drm_plane_state *state);
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;

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#endif /* __INTEL_DRV_H__ */