intel_dp.c 196 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <asm/byteorder.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_hdcp.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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#define DP_DPRX_ESI_LEN 14
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/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
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#define DP_DSC_MIN_SUPPORTED_BPC		8
#define DP_DSC_MAX_SUPPORTED_BPC		10
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/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE			2720000
#define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1		400000

/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
#define DP_DSC_FEC_OVERHEAD_FACTOR		976

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

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static const struct dp_link_dpll g4x_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
};
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/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

/* With Single pipe configuration, HW is capable of supporting maximum
 * of 4 slices per line.
 */
static const u8 valid_dsc_slicecount[] = {1, 2, 4};

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/**
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 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
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bool intel_dp_is_edp(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_encoder *encoder,
			       const struct intel_crtc_state *old_crtc_state);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
					   const struct intel_crtc_state *crtc_state);
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static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
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				      enum pipe pipe);
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static void intel_dp_unset_edid(struct intel_dp *intel_dp);
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/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
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	static const int dp_rates[] = {
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		162000, 270000, 540000, 810000
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	};
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	int i, max_rate;
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	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
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	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
		if (dp_rates[i] > max_rate)
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			break;
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		intel_dp->sink_rates[i] = dp_rates[i];
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	}
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	intel_dp->num_sink_rates = i;
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}

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/* Get length of rates array potentially limited by max_rate. */
static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
{
	int i;

	/* Limit results by potentially reduced max rate */
	for (i = 0; i < len; i++) {
		if (rates[len - i - 1] <= max_rate)
			return len - i;
	}

	return 0;
}

/* Get length of common rates array potentially limited by max_rate. */
static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
					  int max_rate)
{
	return intel_dp_rate_limit_len(intel_dp->common_rates,
				       intel_dp->num_common_rates, max_rate);
}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
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{
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	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
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}

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static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
	u32 lane_info;

	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
		return 4;

	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);

	switch (lane_info) {
	default:
		MISSING_CASE(lane_info);
	case 1:
	case 2:
	case 4:
	case 8:
		return 1;
	case 3:
	case 12:
		return 2;
	case 15:
		return 4;
	}
}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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	int source_max = intel_dig_port->max_lanes;
	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
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	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
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	return min3(source_max, sink_max, fia_max);
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}

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int intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
	return intel_dp->max_link_lane_count;
}

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int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
	return DIV_ROUND_UP(pixel_clock * bpp, 8);
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}

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int
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intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
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	/* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
	 * link rate that is generally expressed in Gbps. Since, 8 bits of data
	 * is transmitted every LS_Clk per lane, there is no need to account for
	 * the channel encoding that is done in the PHY layer here.
	 */

	return max_link_clock * max_lanes;
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}

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static int
intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int max_dotclk = dev_priv->max_dotclk_freq;
	int ds_max_dotclk;

	int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;

	if (type != DP_DS_PORT_TYPE_VGA)
		return max_dotclk;

	ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
						    intel_dp->downstream_ports);

	if (ds_max_dotclk != 0)
		max_dotclk = min(max_dotclk, ds_max_dotclk);

	return max_dotclk;
}

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static int cnl_max_source_rate(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;

	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

	/* Low voltage SKUs are limited to max of 5.4G */
	if (voltage == VOLTAGE_INFO_0_85V)
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		return 540000;
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	/* For this SKU 8.1G is supported in all ports */
	if (IS_CNL_WITH_PORT_F(dev_priv))
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		return 810000;
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	/* For other SKUs, max rate on ports A and D is 5.4G */
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	if (port == PORT_A || port == PORT_D)
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		return 540000;
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	return 810000;
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}

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static int icl_max_source_rate(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum port port = dig_port->base.port;

	if (port == PORT_B)
		return 540000;

	return 810000;
}

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static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
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{
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	/* The values must be in increasing order */
	static const int cnl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
	};
	static const int bxt_rates[] = {
		162000, 216000, 243000, 270000, 324000, 432000, 540000
	};
	static const int skl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000
	};
	static const int hsw_rates[] = {
		162000, 270000, 540000
	};
	static const int g4x_rates[] = {
		162000, 270000
	};
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	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
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	const int *source_rates;
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	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
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	/* This should only be done once */
	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);

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	if (INTEL_GEN(dev_priv) >= 10) {
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		source_rates = cnl_rates;
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		size = ARRAY_SIZE(cnl_rates);
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		if (IS_GEN10(dev_priv))
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			max_rate = cnl_max_source_rate(intel_dp);
		else
			max_rate = icl_max_source_rate(intel_dp);
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	} else if (IS_GEN9_LP(dev_priv)) {
		source_rates = bxt_rates;
		size = ARRAY_SIZE(bxt_rates);
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	} else if (IS_GEN9_BC(dev_priv)) {
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		source_rates = skl_rates;
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		size = ARRAY_SIZE(skl_rates);
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	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
		   IS_BROADWELL(dev_priv)) {
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		source_rates = hsw_rates;
		size = ARRAY_SIZE(hsw_rates);
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	} else {
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		source_rates = g4x_rates;
		size = ARRAY_SIZE(g4x_rates);
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	}

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	if (max_rate && vbt_max_rate)
		max_rate = min(max_rate, vbt_max_rate);
	else if (vbt_max_rate)
		max_rate = vbt_max_rate;

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	if (max_rate)
		size = intel_dp_rate_limit_len(source_rates, size, max_rate);

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	intel_dp->source_rates = source_rates;
	intel_dp->num_source_rates = size;
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}

static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
			   int *common_rates)
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
			common_rates[k] = source_rates[i];
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

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/* return index of rate in rates array, or -1 if not found */
static int intel_dp_rate_index(const int *rates, int len, int rate)
{
	int i;

	for (i = 0; i < len; i++)
		if (rate == rates[i])
			return i;

	return -1;
}

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static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
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{
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	WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
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	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
						     intel_dp->num_source_rates,
						     intel_dp->sink_rates,
						     intel_dp->num_sink_rates,
						     intel_dp->common_rates);

	/* Paranoia, there should always be something in common. */
	if (WARN_ON(intel_dp->num_common_rates == 0)) {
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		intel_dp->common_rates[0] = 162000;
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		intel_dp->num_common_rates = 1;
	}
}

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static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
				       uint8_t lane_count)
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{
	/*
	 * FIXME: we need to synchronize the current link parameters with
	 * hardware readout. Currently fast link training doesn't work on
	 * boot-up.
	 */
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	if (link_rate == 0 ||
	    link_rate > intel_dp->max_link_rate)
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		return false;

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	if (lane_count == 0 ||
	    lane_count > intel_dp_max_lane_count(intel_dp))
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		return false;

	return true;
}

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static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
						     int link_rate,
						     uint8_t lane_count)
{
	const struct drm_display_mode *fixed_mode =
		intel_dp->attached_connector->panel.fixed_mode;
	int mode_rate, max_rate;

	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
	if (mode_rate > max_rate)
		return false;

	return true;
}

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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
					    int link_rate, uint8_t lane_count)
{
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	int index;
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	index = intel_dp_rate_index(intel_dp->common_rates,
				    intel_dp->num_common_rates,
				    link_rate);
	if (index > 0) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp->common_rates[index - 1],
							      lane_count)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
		intel_dp->max_link_lane_count = lane_count;
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	} else if (lane_count > 1) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp_max_common_rate(intel_dp),
							      lane_count >> 1)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
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		intel_dp->max_link_lane_count = lane_count >> 1;
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	} else {
		DRM_ERROR("Link Training Unsuccessful\n");
		return -1;
	}

	return 0;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	struct drm_i915_private *dev_priv = to_i915(connector->dev);
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	int max_dotclk;
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	u16 dsc_max_output_bpp = 0;
	u8 dsc_slice_count = 0;
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	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

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	max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
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	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
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		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = intel_dp_max_link_rate(intel_dp);
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

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	/*
	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
	 * integer value since we support only integer values of bpp.
	 */
	if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
		if (intel_dp_is_edp(intel_dp)) {
			dsc_max_output_bpp =
				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
			dsc_slice_count =
				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
								true);
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		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
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			dsc_max_output_bpp =
				intel_dp_dsc_get_output_bpp(max_link_clock,
							    max_lanes,
							    target_clock,
							    mode->hdisplay) >> 4;
			dsc_slice_count =
				intel_dp_dsc_get_slice_count(intel_dp,
							     target_clock,
							     mode->hdisplay);
		}
	}

	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
	    target_clock > max_dotclk)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

586
static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
587 588 589 590 591 592 593 594
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

595
static void
596
intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
597
static void
598
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
599
					      bool force_disable_vdd);
600
static void
601
intel_dp_pps_init(struct intel_dp *intel_dp);
602

603 604
static void pps_lock(struct intel_dp *intel_dp)
{
605
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
606 607

	/*
608
	 * See intel_power_sequencer_reset() why we need
609 610
	 * a power domain reference here.
	 */
611 612
	intel_display_power_get(dev_priv,
				intel_aux_power_domain(dp_to_dig_port(intel_dp)));
613 614 615 616 617 618

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
619
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
620 621 622

	mutex_unlock(&dev_priv->pps_mutex);

623 624
	intel_display_power_put(dev_priv,
				intel_aux_power_domain(dp_to_dig_port(intel_dp)));
625 626
}

627 628 629
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
630
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
631 632
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum pipe pipe = intel_dp->pps_pipe;
633 634 635
	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
636 637 638
	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
639
		 "skipping pipe %c power sequencer kick due to port %c being active\n",
640
		 pipe_name(pipe), port_name(intel_dig_port->base.port)))
641 642 643
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
644
		      pipe_name(pipe), port_name(intel_dig_port->base.port));
645 646 647 648 649 650 651 652 653

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

654
	if (IS_CHERRYVIEW(dev_priv))
655 656 657
		DP |= DP_PIPE_SEL_CHV(pipe);
	else
		DP |= DP_PIPE_SEL(pipe);
658

659 660 661 662 663 664
	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
665
	if (!pll_enabled) {
666
		release_cl_override = IS_CHERRYVIEW(dev_priv) &&
667 668
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

669
		if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
670 671 672 673 674
				     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
			DRM_ERROR("Failed to force on pll for pipe %c!\n",
				  pipe_name(pipe));
			return;
		}
675
	}
676

677 678 679
	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
680
	 * to make this power sequencer lock onto the port.
681 682 683 684 685 686 687 688 689 690
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
691

692
	if (!pll_enabled) {
693
		vlv_force_pll_off(dev_priv, pipe);
694 695 696 697

		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
698 699
}

700 701 702 703 704 705 706 707 708
static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
{
	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
709 710
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731

		if (encoder->type == INTEL_OUTPUT_EDP) {
			WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
				intel_dp->active_pipe != intel_dp->pps_pipe);

			if (intel_dp->pps_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->pps_pipe);
		} else {
			WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);

			if (intel_dp->active_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->active_pipe);
		}
	}

	if (pipes == 0)
		return INVALID_PIPE;

	return ffs(pipes) - 1;
}

732 733 734
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
735
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
736
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737
	enum pipe pipe;
738

739
	lockdep_assert_held(&dev_priv->pps_mutex);
740

741
	/* We should never land here with regular DP ports */
742
	WARN_ON(!intel_dp_is_edp(intel_dp));
743

744 745 746
	WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
		intel_dp->active_pipe != intel_dp->pps_pipe);

747 748 749
	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

750
	pipe = vlv_find_free_pps(dev_priv);
751 752 753 754 755

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
756
	if (WARN_ON(pipe == INVALID_PIPE))
757
		pipe = PIPE_A;
758

759
	vlv_steal_power_sequencer(dev_priv, pipe);
760
	intel_dp->pps_pipe = pipe;
761 762 763

	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
764
		      port_name(intel_dig_port->base.port));
765 766

	/* init power sequencer on this pipe and port */
767 768
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
769

770 771 772 773 774
	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
775 776 777 778

	return intel_dp->pps_pipe;
}

779 780 781
static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
782
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
783
	int backlight_controller = dev_priv->vbt.backlight.controller;
784 785 786 787

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* We should never land here with regular DP ports */
788
	WARN_ON(!intel_dp_is_edp(intel_dp));
789 790

	if (!intel_dp->pps_reset)
791
		return backlight_controller;
792 793 794 795 796 797 798

	intel_dp->pps_reset = false;

	/*
	 * Only the HW needs to be reprogrammed, the SW state is fixed and
	 * has been setup during connector init.
	 */
799
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
800

801
	return backlight_controller;
802 803
}

804 805 806 807 808 809
typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
810
	return I915_READ(PP_STATUS(pipe)) & PP_ON;
811 812 813 814 815
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
816
	return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
817 818 819 820 821 822 823
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
824

825
static enum pipe
826 827 828
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
829 830
{
	enum pipe pipe;
831 832

	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
833
		u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
834
			PANEL_PORT_SELECT_MASK;
835 836 837 838

		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

839 840 841
		if (!pipe_check(dev_priv, pipe))
			continue;

842
		return pipe;
843 844
	}

845 846 847 848 849 850
	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
851
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
852
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
853
	enum port port = intel_dig_port->base.port;
854 855 856 857

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
858 859 860 861 862 863 864 865 866 867 868
	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
869 870 871 872 873 874

	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
875 876
	}

877 878 879
	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

880 881
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
882 883
}

884
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
885 886 887
{
	struct intel_encoder *encoder;

888
	if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
889
		    !IS_GEN9_LP(dev_priv)))
890 891 892 893 894 895 896 897 898 899 900 901
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

902 903
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
904

905 906 907 908 909
		WARN_ON(intel_dp->active_pipe != INVALID_PIPE);

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

910
		if (IS_GEN9_LP(dev_priv))
911 912 913
			intel_dp->pps_reset = true;
		else
			intel_dp->pps_pipe = INVALID_PIPE;
914
	}
915 916
}

917 918 919 920 921 922 923 924
struct pps_registers {
	i915_reg_t pp_ctrl;
	i915_reg_t pp_stat;
	i915_reg_t pp_on;
	i915_reg_t pp_off;
	i915_reg_t pp_div;
};

925
static void intel_pps_get_registers(struct intel_dp *intel_dp,
926 927
				    struct pps_registers *regs)
{
928
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
929 930
	int pps_idx = 0;

931 932
	memset(regs, 0, sizeof(*regs));

933
	if (IS_GEN9_LP(dev_priv))
934 935 936
		pps_idx = bxt_power_sequencer_idx(intel_dp);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		pps_idx = vlv_power_sequencer_pipe(intel_dp);
937

938 939 940 941
	regs->pp_ctrl = PP_CONTROL(pps_idx);
	regs->pp_stat = PP_STATUS(pps_idx);
	regs->pp_on = PP_ON_DELAYS(pps_idx);
	regs->pp_off = PP_OFF_DELAYS(pps_idx);
942 943
	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
	    !HAS_PCH_ICP(dev_priv))
944
		regs->pp_div = PP_DIVISOR(pps_idx);
945 946
}

947 948
static i915_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
949
{
950
	struct pps_registers regs;
951

952
	intel_pps_get_registers(intel_dp, &regs);
953 954

	return regs.pp_ctrl;
955 956
}

957 958
static i915_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
959
{
960
	struct pps_registers regs;
961

962
	intel_pps_get_registers(intel_dp, &regs);
963 964

	return regs.pp_stat;
965 966
}

967 968 969 970 971 972 973
/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
974
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
975

976
	if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
977 978
		return 0;

979
	pps_lock(intel_dp);
980

981
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
982
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
983
		i915_reg_t pp_ctrl_reg, pp_div_reg;
984
		u32 pp_div;
985

986 987
		pp_ctrl_reg = PP_CONTROL(pipe);
		pp_div_reg  = PP_DIVISOR(pipe);
988 989 990 991 992 993 994 995 996
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

997
	pps_unlock(intel_dp);
998

999 1000 1001
	return 0;
}

1002
static bool edp_have_panel_power(struct intel_dp *intel_dp)
1003
{
1004
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1005

1006 1007
	lockdep_assert_held(&dev_priv->pps_mutex);

1008
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1009 1010 1011
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

1012
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1013 1014
}

1015
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1016
{
1017
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1018

1019 1020
	lockdep_assert_held(&dev_priv->pps_mutex);

1021
	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1022 1023 1024
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

1025
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1026 1027
}

1028 1029 1030
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
1031
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1032

1033
	if (!intel_dp_is_edp(intel_dp))
1034
		return;
1035

1036
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1037 1038
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1039 1040
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
1041 1042 1043
	}
}

1044
static uint32_t
1045
intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1046
{
1047
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1048
	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1049 1050 1051
	uint32_t status;
	bool done;

1052
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1053 1054
	done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
				  msecs_to_jiffies_timeout(10));
1055
	if (!done)
1056
		DRM_ERROR("dp aux hw did not signal timeout!\n");
1057 1058 1059 1060 1061
#undef C

	return status;
}

1062
static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1063
{
1064
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1065

1066 1067 1068
	if (index)
		return 0;

1069 1070
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
1071
	 * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1072
	 */
1073
	return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1074 1075 1076 1077
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
1078
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1079
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1080 1081 1082 1083

	if (index)
		return 0;

1084 1085 1086 1087 1088
	/*
	 * The clock divider is based off the cdclk or PCH rawclk, and would
	 * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
	 * divide by 2000 and use that
	 */
1089
	if (dig_port->aux_ch == AUX_CH_A)
1090
		return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1091 1092
	else
		return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1093 1094 1095 1096
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
1097
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1099

1100
	if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1101
		/* Workaround for non-ULT HSW */
1102 1103 1104 1105 1106
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
1107
	}
1108 1109

	return ilk_get_aux_clock_divider(intel_dp, index);
1110 1111
}

1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

1122 1123 1124
static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
				     int send_bytes,
				     uint32_t aux_clock_divider)
1125 1126
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1127 1128
	struct drm_i915_private *dev_priv =
			to_i915(intel_dig_port->base.base.dev);
1129 1130
	uint32_t precharge, timeout;

1131
	if (IS_GEN6(dev_priv))
1132 1133 1134 1135
		precharge = 3;
	else
		precharge = 5;

1136
	if (IS_BROADWELL(dev_priv))
1137 1138 1139 1140 1141
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
1142
	       DP_AUX_CH_CTL_DONE |
1143
	       DP_AUX_CH_CTL_INTERRUPT |
1144
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
1145
	       timeout |
1146
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
1147 1148
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1149
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1150 1151
}

1152 1153 1154 1155
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      int send_bytes,
				      uint32_t unused)
{
1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	uint32_t ret;

	ret = DP_AUX_CH_CTL_SEND_BUSY |
	      DP_AUX_CH_CTL_DONE |
	      DP_AUX_CH_CTL_INTERRUPT |
	      DP_AUX_CH_CTL_TIME_OUT_ERROR |
	      DP_AUX_CH_CTL_TIME_OUT_MAX |
	      DP_AUX_CH_CTL_RECEIVE_ERROR |
	      (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	      DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
	      DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);

	if (intel_dig_port->tc_type == TC_PORT_TBT)
		ret |= DP_AUX_CH_CTL_TBT_IO;

	return ret;
1173 1174
}

1175
static int
1176 1177
intel_dp_aux_xfer(struct intel_dp *intel_dp,
		  const uint8_t *send, int send_bytes,
1178 1179
		  uint8_t *recv, int recv_size,
		  u32 aux_send_ctl_flags)
1180 1181
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1182 1183
	struct drm_i915_private *dev_priv =
			to_i915(intel_dig_port->base.base.dev);
1184
	i915_reg_t ch_ctl, ch_data[5];
1185
	uint32_t aux_clock_divider;
1186 1187
	int i, ret, recv_bytes;
	uint32_t status;
1188
	int try, clock = 0;
1189 1190
	bool vdd;

1191 1192 1193 1194
	ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
		ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);

1195
	pps_lock(intel_dp);
1196

1197 1198 1199 1200 1201 1202
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
1203
	vdd = edp_panel_vdd_on(intel_dp);
1204 1205 1206 1207 1208 1209 1210 1211

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
1212

1213 1214
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
1215
		status = I915_READ_NOTRACE(ch_ctl);
1216 1217 1218 1219 1220 1221
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
1222 1223 1224 1225 1226 1227 1228 1229 1230
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

1231 1232
		ret = -EBUSY;
		goto out;
1233 1234
	}

1235 1236 1237 1238 1239 1240
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

1241
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1242 1243 1244 1245 1246
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  send_bytes,
							  aux_clock_divider);

		send_ctl |= aux_send_ctl_flags;
1247

1248 1249 1250 1251
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
1252
				I915_WRITE(ch_data[i >> 2],
1253 1254
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
1255 1256

			/* Send the command and wait for it to complete */
1257
			I915_WRITE(ch_ctl, send_ctl);
1258

1259
			status = intel_dp_aux_wait_done(intel_dp);
1260 1261 1262 1263 1264 1265 1266 1267

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

1268 1269 1270 1271 1272
			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
1273 1274 1275
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
				continue;

1276 1277
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
1278
				continue;
1279
			}
1280
			if (status & DP_AUX_CH_CTL_DONE)
1281
				goto done;
1282
		}
1283 1284 1285
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1286
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1287 1288
		ret = -EBUSY;
		goto out;
1289 1290
	}

1291
done:
1292 1293 1294
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
1295
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1296
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1297 1298
		ret = -EIO;
		goto out;
1299
	}
1300 1301 1302

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
1303
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1304
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1305 1306
		ret = -ETIMEDOUT;
		goto out;
1307 1308 1309 1310 1311
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324

	/*
	 * By BSpec: "Message sizes of 0 or >20 are not allowed."
	 * We have no idea of what happened so we return -EBUSY so
	 * drm layer takes care for the necessary retries.
	 */
	if (recv_bytes == 0 || recv_bytes > 20) {
		DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
			      recv_bytes);
		ret = -EBUSY;
		goto out;
	}

1325 1326
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
1327

1328
	for (i = 0; i < recv_bytes; i += 4)
1329
		intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1330
				    recv + i, recv_bytes - i);
1331

1332 1333 1334 1335
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

1336 1337 1338
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

1339
	pps_unlock(intel_dp);
1340

1341
	return ret;
1342 1343
}

1344 1345
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356

static void
intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
		    const struct drm_dp_aux_msg *msg)
{
	txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
}

1357 1358
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1359
{
1360 1361 1362
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
1363 1364
	int ret;

1365
	intel_dp_aux_header(txbuf, msg);
1366

1367 1368 1369
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
1370
	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1371
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1372
		rxsize = 2; /* 0 or 1 data bytes */
1373

1374 1375
		if (WARN_ON(txsize > 20))
			return -E2BIG;
1376

1377 1378
		WARN_ON(!msg->buffer != !msg->size);

1379 1380
		if (msg->buffer)
			memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1381

1382
		ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1383
					rxbuf, rxsize, 0);
1384 1385
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
1386

1387 1388 1389 1390 1391 1392 1393
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
1394 1395
		}
		break;
1396

1397 1398
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
1399
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1400
		rxsize = msg->size + 1;
1401

1402 1403
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
1404

1405
		ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1406
					rxbuf, rxsize, 0);
1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
1417
		}
1418 1419 1420 1421 1422
		break;

	default:
		ret = -EINVAL;
		break;
1423
	}
1424

1425
	return ret;
1426 1427
}

1428

1429
static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1430
{
1431
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1432 1433
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1434

1435 1436 1437 1438 1439
	switch (aux_ch) {
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
		return DP_AUX_CH_CTL(aux_ch);
1440
	default:
1441 1442
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_CTL(AUX_CH_B);
1443 1444 1445
	}
}

1446
static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1447
{
1448
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1449 1450
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1451

1452 1453 1454 1455 1456
	switch (aux_ch) {
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
		return DP_AUX_CH_DATA(aux_ch, index);
1457
	default:
1458 1459
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_DATA(AUX_CH_B, index);
1460 1461 1462
	}
}

1463
static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1464
{
1465
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1466 1467
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1468

1469 1470 1471 1472 1473 1474 1475
	switch (aux_ch) {
	case AUX_CH_A:
		return DP_AUX_CH_CTL(aux_ch);
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
		return PCH_DP_AUX_CH_CTL(aux_ch);
1476
	default:
1477 1478
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_CTL(AUX_CH_A);
1479 1480 1481
	}
}

1482
static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1483
{
1484
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1485 1486
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1487

1488 1489 1490 1491 1492 1493 1494
	switch (aux_ch) {
	case AUX_CH_A:
		return DP_AUX_CH_DATA(aux_ch, index);
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
		return PCH_DP_AUX_CH_DATA(aux_ch, index);
1495
	default:
1496 1497
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_DATA(AUX_CH_A, index);
1498 1499 1500
	}
}

1501
static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1502
{
1503
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1504 1505
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1506

1507 1508 1509 1510 1511
	switch (aux_ch) {
	case AUX_CH_A:
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
1512
	case AUX_CH_E:
1513 1514
	case AUX_CH_F:
		return DP_AUX_CH_CTL(aux_ch);
1515
	default:
1516 1517
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_CTL(AUX_CH_A);
1518 1519 1520
	}
}

1521
static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1522
{
1523
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1524 1525
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	enum aux_ch aux_ch = dig_port->aux_ch;
1526

1527 1528 1529 1530 1531
	switch (aux_ch) {
	case AUX_CH_A:
	case AUX_CH_B:
	case AUX_CH_C:
	case AUX_CH_D:
1532
	case AUX_CH_E:
1533 1534
	case AUX_CH_F:
		return DP_AUX_CH_DATA(aux_ch, index);
1535
	default:
1536 1537
		MISSING_CASE(aux_ch);
		return DP_AUX_CH_DATA(AUX_CH_A, index);
1538 1539 1540
	}
}

1541 1542 1543 1544 1545 1546 1547 1548
static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
	kfree(intel_dp->aux.name);
}

static void
intel_dp_aux_init(struct intel_dp *intel_dp)
1549
{
1550
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1551 1552
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &dig_port->base;
1553

1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
	if (INTEL_GEN(dev_priv) >= 9) {
		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
		intel_dp->aux_ch_data_reg = skl_aux_data_reg;
	} else if (HAS_PCH_SPLIT(dev_priv)) {
		intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
		intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
	} else {
		intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
		intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
	}
1564

1565 1566 1567 1568 1569 1570 1571 1572
	if (INTEL_GEN(dev_priv) >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev_priv))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1573

1574 1575 1576 1577
	if (INTEL_GEN(dev_priv) >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1578

1579
	drm_dp_aux_init(&intel_dp->aux);
1580

1581
	/* Failure to allocate our preferred name is not critical */
1582 1583
	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
				       port_name(encoder->port));
1584
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1585 1586
}

1587
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1588
{
1589
	int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1590

1591
	return max_rate >= 540000;
1592 1593
}

1594 1595 1596 1597 1598 1599 1600
bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
{
	int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];

	return max_rate >= 810000;
}

1601 1602
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1603
		   struct intel_crtc_state *pipe_config)
1604
{
1605
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606 1607
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1608

1609
	if (IS_G4X(dev_priv)) {
1610 1611
		divisor = g4x_dpll;
		count = ARRAY_SIZE(g4x_dpll);
1612
	} else if (HAS_PCH_SPLIT(dev_priv)) {
1613 1614
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1615
	} else if (IS_CHERRYVIEW(dev_priv)) {
1616 1617
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1618
	} else if (IS_VALLEYVIEW(dev_priv)) {
1619 1620
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1621
	}
1622 1623 1624

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1625
			if (pipe_config->port_clock == divisor[i].clock) {
1626 1627 1628 1629 1630
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1631 1632 1633
	}
}

1634 1635 1636 1637 1638 1639 1640 1641
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1642
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

1657 1658
	snprintf_int_array(str, sizeof(str),
			   intel_dp->source_rates, intel_dp->num_source_rates);
1659 1660
	DRM_DEBUG_KMS("source rates: %s\n", str);

1661 1662
	snprintf_int_array(str, sizeof(str),
			   intel_dp->sink_rates, intel_dp->num_sink_rates);
1663 1664
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1665 1666
	snprintf_int_array(str, sizeof(str),
			   intel_dp->common_rates, intel_dp->num_common_rates);
1667
	DRM_DEBUG_KMS("common rates: %s\n", str);
1668 1669
}

1670 1671 1672 1673 1674
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int len;

1675
	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1676 1677 1678
	if (WARN_ON(len <= 0))
		return 162000;

1679
	return intel_dp->common_rates[len - 1];
1680 1681
}

1682 1683
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1684 1685
	int i = intel_dp_rate_index(intel_dp->sink_rates,
				    intel_dp->num_sink_rates, rate);
1686 1687 1688 1689 1690

	if (WARN_ON(i < 0))
		i = 0;

	return i;
1691 1692
}

1693 1694
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select)
1695
{
1696 1697
	/* eDP 1.4 rate select method. */
	if (intel_dp->use_rate_select) {
1698 1699 1700 1701 1702 1703 1704 1705 1706
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

1707 1708 1709 1710 1711 1712
struct link_config_limits {
	int min_clock, max_clock;
	int min_lane_count, max_lane_count;
	int min_bpp, max_bpp;
};

1713
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1714 1715 1716 1717
					 const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732
	return INTEL_GEN(dev_priv) >= 11 &&
		pipe_config->cpu_transcoder != TRANSCODER_A;
}

static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
				  const struct intel_crtc_state *pipe_config)
{
	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
		drm_dp_sink_supports_fec(intel_dp->fec_capable);
}

static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
					 const struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1733 1734 1735 1736 1737 1738 1739 1740

	return INTEL_GEN(dev_priv) >= 10 &&
		pipe_config->cpu_transcoder != TRANSCODER_A;
}

static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
				  const struct intel_crtc_state *pipe_config)
{
1741 1742 1743
	if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
		return false;

1744 1745 1746 1747
	return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}

1748 1749
static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
				struct intel_crtc_state *pipe_config)
1750
{
1751
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1752
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1753 1754 1755 1756 1757 1758 1759 1760
	int bpp, bpc;

	bpp = pipe_config->pipe_bpp;
	bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);

	if (bpc > 0)
		bpp = min(bpp, 3*bpc);

1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
	if (intel_dp_is_edp(intel_dp)) {
		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
		    dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp.bpp);
			bpp = dev_priv->vbt.edp.bpp;
		}
	}

1771 1772 1773
	return bpp;
}

1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
/* Adjust link config limits based on compliance test requests. */
static void
intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
				  struct intel_crtc_state *pipe_config,
				  struct link_config_limits *limits)
{
	/* For DP Compliance we override the computed bpp for the pipe */
	if (intel_dp->compliance.test_data.bpc != 0) {
		int bpp = 3 * intel_dp->compliance.test_data.bpc;

		limits->min_bpp = limits->max_bpp = bpp;
		pipe_config->dither_force_disable = bpp == 6 * 3;

		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
	}

	/* Use values requested by Compliance Test Request */
	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
		int index;

		/* Validate the compliance test data since max values
		 * might have changed due to link train fallback.
		 */
		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
					       intel_dp->compliance.test_lane_count)) {
			index = intel_dp_rate_index(intel_dp->common_rates,
						    intel_dp->num_common_rates,
						    intel_dp->compliance.test_link_rate);
			if (index >= 0)
				limits->min_clock = limits->max_clock = index;
			limits->min_lane_count = limits->max_lane_count =
				intel_dp->compliance.test_lane_count;
		}
	}
}

1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
/* Optimize link config in order: max bpp, min clock, min lanes */
static bool
intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
				  struct intel_crtc_state *pipe_config,
				  const struct link_config_limits *limits)
{
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	int bpp, clock, lane_count;
	int mode_rate, link_clock, link_avail;

	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);

		for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
			for (lane_count = limits->min_lane_count;
			     lane_count <= limits->max_lane_count;
			     lane_count <<= 1) {
				link_clock = intel_dp->common_rates[clock];
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					pipe_config->lane_count = lane_count;
					pipe_config->pipe_bpp = bpp;
					pipe_config->port_clock = link_clock;

					return true;
				}
			}
		}
	}

	return false;
}

1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881
/* Optimize link config in order: max bpp, min lanes, min clock */
static bool
intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
				  struct intel_crtc_state *pipe_config,
				  const struct link_config_limits *limits)
{
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	int bpp, clock, lane_count;
	int mode_rate, link_clock, link_avail;

	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);

		for (lane_count = limits->min_lane_count;
		     lane_count <= limits->max_lane_count;
		     lane_count <<= 1) {
			for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
				link_clock = intel_dp->common_rates[clock];
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					pipe_config->lane_count = lane_count;
					pipe_config->pipe_bpp = bpp;
					pipe_config->port_clock = link_clock;

					return true;
				}
			}
		}
	}

	return false;
}

1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
{
	int i, num_bpc;
	u8 dsc_bpc[3] = {0};

	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
						       dsc_bpc);
	for (i = 0; i < num_bpc; i++) {
		if (dsc_max_bpc >= dsc_bpc[i])
			return dsc_bpc[i] * 3;
	}

	return 0;
}

static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
					struct intel_crtc_state *pipe_config,
					struct drm_connector_state *conn_state,
					struct link_config_limits *limits)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	u8 dsc_max_bpc;
	int pipe_bpp;

	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
		return false;

	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
			    conn_state->max_requested_bpc);

	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
		return false;
	}

	/*
	 * For now enable DSC for max bpp, max link rate, max lane count.
	 * Optimize this later for the minimum possible link rate/lane count
	 * with DSC enabled for the requested mode.
	 */
	pipe_config->pipe_bpp = pipe_bpp;
	pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
	pipe_config->lane_count = limits->max_lane_count;

	if (intel_dp_is_edp(intel_dp)) {
		pipe_config->dsc_params.compressed_bpp =
			min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
			      pipe_config->pipe_bpp);
		pipe_config->dsc_params.slice_count =
			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
							true);
	} else {
		u16 dsc_max_output_bpp;
		u8 dsc_dp_slice_count;

		dsc_max_output_bpp =
			intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
						    pipe_config->lane_count,
						    adjusted_mode->crtc_clock,
						    adjusted_mode->crtc_hdisplay);
		dsc_dp_slice_count =
			intel_dp_dsc_get_slice_count(intel_dp,
						     adjusted_mode->crtc_clock,
						     adjusted_mode->crtc_hdisplay);
		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
			DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
			return false;
		}
		pipe_config->dsc_params.compressed_bpp = min_t(u16,
							       dsc_max_output_bpp >> 4,
							       pipe_config->pipe_bpp);
		pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
	}
	/*
	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
	 * is greater than the maximum Cdclock and if slice count is even
	 * then we need to use 2 VDSC instances.
	 */
	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
		if (pipe_config->dsc_params.slice_count > 1) {
			pipe_config->dsc_params.dsc_split = true;
		} else {
			DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
			return false;
		}
	}
1971 1972 1973 1974 1975 1976 1977
	if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
		DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
			      "Compressed BPP = %d\n",
			      pipe_config->pipe_bpp,
			      pipe_config->dsc_params.compressed_bpp);
		return false;
	}
1978 1979 1980 1981 1982 1983 1984 1985 1986 1987
	pipe_config->dsc_params.compression_enable = true;
	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
		      "Compressed Bpp = %d Slice Count = %d\n",
		      pipe_config->pipe_bpp,
		      pipe_config->dsc_params.compressed_bpp,
		      pipe_config->dsc_params.slice_count);

	return true;
}

1988 1989
static bool
intel_dp_compute_link_config(struct intel_encoder *encoder,
1990 1991
			     struct intel_crtc_state *pipe_config,
			     struct drm_connector_state *conn_state)
1992
{
1993
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1994
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1995
	struct link_config_limits limits;
1996
	int common_len;
1997
	bool ret;
1998

1999
	common_len = intel_dp_common_len_rate_limit(intel_dp,
2000
						    intel_dp->max_link_rate);
2001 2002

	/* No common link rates between source and sink */
2003
	WARN_ON(common_len <= 0);
2004

2005 2006 2007 2008 2009 2010 2011 2012
	limits.min_clock = 0;
	limits.max_clock = common_len - 1;

	limits.min_lane_count = 1;
	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);

	limits.min_bpp = 6 * 3;
	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2013

2014
	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2015 2016
		/*
		 * Use the maximum clock and number of lanes the eDP panel
2017 2018 2019 2020 2021 2022
		 * advertizes being capable of. The eDP 1.3 and earlier panels
		 * are generally designed to support only a single clock and
		 * lane configuration, and typically these values correspond to
		 * the native resolution of the panel. With eDP 1.4 rate select
		 * and DSC, this is decreasingly the case, and we need to be
		 * able to select less than maximum link config.
2023
		 */
2024 2025
		limits.min_lane_count = limits.max_lane_count;
		limits.min_clock = limits.max_clock;
2026
	}
2027

2028 2029
	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);

2030 2031 2032 2033 2034 2035
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max rate %d max bpp %d pixel clock %iKHz\n",
		      limits.max_lane_count,
		      intel_dp->common_rates[limits.max_clock],
		      limits.max_bpp, adjusted_mode->crtc_clock);

2036
	if (intel_dp_is_edp(intel_dp))
2037 2038 2039 2040 2041 2042 2043 2044 2045
		/*
		 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
		 * section A.1: "It is recommended that the minimum number of
		 * lanes be used, using the minimum link rate allowed for that
		 * lane configuration."
		 *
		 * Note that we use the max clock and lane count for eDP 1.3 and
		 * earlier, and fast vs. wide is irrelevant.
		 */
2046 2047 2048
		ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
							&limits);
	else
2049
		/* Optimize for slow and wide. */
2050 2051 2052 2053 2054 2055 2056
		ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
							&limits);

	/* enable compression if the mode doesn't fit available BW */
	if (!ret) {
		if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
						 conn_state, &limits))
2057 2058
			return false;
	}
2059

2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081
	if (pipe_config->dsc_params.compression_enable) {
		DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
			      pipe_config->lane_count, pipe_config->port_clock,
			      pipe_config->pipe_bpp,
			      pipe_config->dsc_params.compressed_bpp);

		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
			      intel_dp_link_required(adjusted_mode->crtc_clock,
						     pipe_config->dsc_params.compressed_bpp),
			      intel_dp_max_data_rate(pipe_config->port_clock,
						     pipe_config->lane_count));
	} else {
		DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
			      pipe_config->lane_count, pipe_config->port_clock,
			      pipe_config->pipe_bpp);

		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
			      intel_dp_link_required(adjusted_mode->crtc_clock,
						     pipe_config->pipe_bpp),
			      intel_dp_max_data_rate(pipe_config->port_clock,
						     pipe_config->lane_count));
	}
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092
	return true;
}

bool
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_state *pipe_config,
			struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2093
	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2094 2095 2096 2097 2098
	enum port port = encoder->port;
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct intel_digital_connector_state *intel_conn_state =
		to_intel_digital_connector_state(conn_state);
2099 2100
	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
					   DP_DPCD_QUIRK_CONSTANT_N);
2101 2102 2103 2104

	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
		pipe_config->has_pch_encoder = true;

2105
	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2106 2107 2108
	if (lspcon->active)
		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);

2109 2110 2111 2112 2113 2114 2115 2116 2117
	pipe_config->has_drrs = false;
	if (IS_G4X(dev_priv) || port == PORT_A)
		pipe_config->has_audio = false;
	else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
		pipe_config->has_audio = intel_dp->has_audio;
	else
		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;

	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2118 2119
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136

		if (INTEL_GEN(dev_priv) >= 9) {
			int ret;

			ret = skl_update_scaler_crtc(pipe_config);
			if (ret)
				return ret;
		}

		if (HAS_GMCH_DISPLAY(dev_priv))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 conn_state->scaling_mode);
		else
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						conn_state->scaling_mode);
	}

2137 2138 2139
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return false;

2140
	if (HAS_GMCH_DISPLAY(dev_priv) &&
2141 2142 2143 2144 2145 2146
	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
		return false;

	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		return false;

2147 2148 2149
	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
				  intel_dp_supports_fec(intel_dp, pipe_config);

2150
	if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
2151 2152
		return false;

2153
	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2154 2155 2156 2157 2158
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
2159
		pipe_config->limited_color_range =
2160
			pipe_config->pipe_bpp != 18 &&
2161 2162
			drm_default_rgb_quant_range(adjusted_mode) ==
			HDMI_QUANTIZATION_RANGE_LIMITED;
2163 2164
	} else {
		pipe_config->limited_color_range =
2165
			intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2166 2167
	}

2168 2169 2170 2171 2172 2173 2174 2175
	if (!pipe_config->dsc_params.compression_enable)
		intel_link_compute_m_n(pipe_config->pipe_bpp,
				       pipe_config->lane_count,
				       adjusted_mode->crtc_clock,
				       pipe_config->port_clock,
				       &pipe_config->dp_m_n,
				       constant_n);
	else
2176
		intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2177 2178 2179 2180 2181
				       pipe_config->lane_count,
				       adjusted_mode->crtc_clock,
				       pipe_config->port_clock,
				       &pipe_config->dp_m_n,
				       constant_n);
2182

2183
	if (intel_connector->panel.downclock_mode != NULL &&
2184
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2185
			pipe_config->has_drrs = true;
2186 2187 2188 2189 2190
			intel_link_compute_m_n(pipe_config->pipe_bpp,
					       pipe_config->lane_count,
					       intel_connector->panel.downclock_mode->clock,
					       pipe_config->port_clock,
					       &pipe_config->dp_m2_n2,
2191
					       constant_n);
2192 2193
	}

2194
	if (!HAS_DDI(dev_priv))
2195
		intel_dp_set_clock(encoder, pipe_config);
2196

2197 2198
	intel_psr_compute_config(intel_dp, pipe_config);

2199
	return true;
2200 2201
}

2202
void intel_dp_set_link_params(struct intel_dp *intel_dp,
2203 2204
			      int link_rate, uint8_t lane_count,
			      bool link_mst)
2205
{
2206
	intel_dp->link_trained = false;
2207 2208 2209
	intel_dp->link_rate = link_rate;
	intel_dp->lane_count = lane_count;
	intel_dp->link_mst = link_mst;
2210 2211
}

2212
static void intel_dp_prepare(struct intel_encoder *encoder,
2213
			     const struct intel_crtc_state *pipe_config)
2214
{
2215
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2216
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2217
	enum port port = encoder->port;
2218
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2219
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2220

2221 2222 2223 2224
	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
				 pipe_config->lane_count,
				 intel_crtc_has_type(pipe_config,
						     INTEL_OUTPUT_DP_MST));
2225

2226
	/*
2227
	 * There are four kinds of DP registers:
2228 2229
	 *
	 * 	IBX PCH
2230 2231
	 * 	SNB CPU
	 *	IVB CPU
2232 2233 2234 2235 2236 2237 2238 2239 2240 2241
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
2242

2243 2244 2245 2246
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2247

2248 2249
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2250
	intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2251

2252
	/* Split out the IBX/CPU vs CPT settings */
2253

2254
	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2255 2256 2257 2258 2259 2260
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

2261
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2262 2263
			intel_dp->DP |= DP_ENHANCED_FRAMING;

2264
		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2265
	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2266 2267
		u32 trans_dp;

2268
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2269 2270 2271 2272 2273 2274 2275

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2276
	} else {
2277
		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2278
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
2279 2280 2281 2282 2283 2284 2285

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

2286
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2287 2288
			intel_dp->DP |= DP_ENHANCED_FRAMING;

2289
		if (IS_CHERRYVIEW(dev_priv))
2290 2291 2292
			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
		else
			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2293
	}
2294 2295
}

2296 2297
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2298

2299 2300
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
2301

2302 2303
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2304

2305
static void intel_pps_verify_state(struct intel_dp *intel_dp);
2306

2307
static void wait_panel_status(struct intel_dp *intel_dp,
2308 2309
				       u32 mask,
				       u32 value)
2310
{
2311
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2312
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
2313

2314 2315
	lockdep_assert_held(&dev_priv->pps_mutex);

2316
	intel_pps_verify_state(intel_dp);
2317

2318 2319
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2320

2321
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2322 2323 2324
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
2325

2326 2327 2328
	if (intel_wait_for_register(dev_priv,
				    pp_stat_reg, mask, value,
				    5000))
2329
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2330 2331
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
2332 2333

	DRM_DEBUG_KMS("Wait complete\n");
2334
}
2335

2336
static void wait_panel_on(struct intel_dp *intel_dp)
2337 2338
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
2339
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2340 2341
}

2342
static void wait_panel_off(struct intel_dp *intel_dp)
2343 2344
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
2345
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2346 2347
}

2348
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2349
{
2350 2351 2352
	ktime_t panel_power_on_time;
	s64 panel_power_off_duration;

2353
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
2354

2355 2356 2357 2358 2359
	/* take the difference of currrent time and panel power off time
	 * and then make panel wait for t11_t12 if needed. */
	panel_power_on_time = ktime_get_boottime();
	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);

2360 2361
	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
2362 2363 2364
	if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
		wait_remaining_ms_from_jiffies(jiffies,
				       intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2365

2366
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2367 2368
}

2369
static void wait_backlight_on(struct intel_dp *intel_dp)
2370 2371 2372 2373 2374
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

2375
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2376 2377 2378 2379
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
2380

2381 2382 2383 2384
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

2385
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2386
{
2387
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2388
	u32 control;
2389

2390 2391
	lockdep_assert_held(&dev_priv->pps_mutex);

2392
	control = I915_READ(_pp_ctrl_reg(intel_dp));
2393 2394
	if (WARN_ON(!HAS_DDI(dev_priv) &&
		    (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2395 2396 2397
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
2398
	return control;
2399 2400
}

2401 2402 2403 2404 2405
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
2406
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2407
{
2408
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2409
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2410
	u32 pp;
2411
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
2412
	bool need_to_disable = !intel_dp->want_panel_vdd;
2413

2414 2415
	lockdep_assert_held(&dev_priv->pps_mutex);

2416
	if (!intel_dp_is_edp(intel_dp))
2417
		return false;
2418

2419
	cancel_delayed_work(&intel_dp->panel_vdd_work);
2420
	intel_dp->want_panel_vdd = true;
2421

2422
	if (edp_have_panel_vdd(intel_dp))
2423
		return need_to_disable;
2424

2425 2426
	intel_display_power_get(dev_priv,
				intel_aux_power_domain(intel_dig_port));
2427

2428
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2429
		      port_name(intel_dig_port->base.port));
2430

2431 2432
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
2433

2434
	pp = ironlake_get_pp_control(intel_dp);
2435
	pp |= EDP_FORCE_VDD;
2436

2437 2438
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2439 2440 2441 2442 2443

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2444 2445 2446
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
2447
	if (!edp_have_panel_power(intel_dp)) {
2448
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2449
			      port_name(intel_dig_port->base.port));
2450 2451
		msleep(intel_dp->panel_power_up_delay);
	}
2452 2453 2454 2455

	return need_to_disable;
}

2456 2457 2458 2459 2460 2461 2462
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
2463
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2464
{
2465
	bool vdd;
2466

2467
	if (!intel_dp_is_edp(intel_dp))
2468 2469
		return;

2470
	pps_lock(intel_dp);
2471
	vdd = edp_panel_vdd_on(intel_dp);
2472
	pps_unlock(intel_dp);
2473

2474
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2475
	     port_name(dp_to_dig_port(intel_dp)->base.port));
2476 2477
}

2478
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2479
{
2480
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2481 2482
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
2483
	u32 pp;
2484
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
2485

2486
	lockdep_assert_held(&dev_priv->pps_mutex);
2487

2488
	WARN_ON(intel_dp->want_panel_vdd);
2489

2490
	if (!edp_have_panel_vdd(intel_dp))
2491
		return;
2492

2493
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2494
		      port_name(intel_dig_port->base.port));
2495

2496 2497
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
2498

2499 2500
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
2501

2502 2503
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2504

2505 2506 2507
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2508

2509
	if ((pp & PANEL_POWER_ON) == 0)
2510
		intel_dp->panel_power_off_time = ktime_get_boottime();
2511

2512 2513
	intel_display_power_put(dev_priv,
				intel_aux_power_domain(intel_dig_port));
2514
}
2515

2516
static void edp_panel_vdd_work(struct work_struct *__work)
2517 2518 2519 2520
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

2521
	pps_lock(intel_dp);
2522 2523
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
2524
	pps_unlock(intel_dp);
2525 2526
}

2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

2540 2541 2542 2543 2544
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
2545
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2546
{
2547
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2548 2549 2550

	lockdep_assert_held(&dev_priv->pps_mutex);

2551
	if (!intel_dp_is_edp(intel_dp))
2552
		return;
2553

2554
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2555
	     port_name(dp_to_dig_port(intel_dp)->base.port));
2556

2557 2558
	intel_dp->want_panel_vdd = false;

2559
	if (sync)
2560
		edp_panel_vdd_off_sync(intel_dp);
2561 2562
	else
		edp_panel_vdd_schedule_off(intel_dp);
2563 2564
}

2565
static void edp_panel_on(struct intel_dp *intel_dp)
2566
{
2567
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2568
	u32 pp;
2569
	i915_reg_t pp_ctrl_reg;
2570

2571 2572
	lockdep_assert_held(&dev_priv->pps_mutex);

2573
	if (!intel_dp_is_edp(intel_dp))
2574
		return;
2575

2576
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2577
		      port_name(dp_to_dig_port(intel_dp)->base.port));
2578

2579 2580
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
2581
		 port_name(dp_to_dig_port(intel_dp)->base.port)))
2582
		return;
2583

2584
	wait_panel_power_cycle(intel_dp);
2585

2586
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2587
	pp = ironlake_get_pp_control(intel_dp);
2588
	if (IS_GEN5(dev_priv)) {
2589 2590
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
2591 2592
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
2593
	}
2594

2595
	pp |= PANEL_POWER_ON;
2596
	if (!IS_GEN5(dev_priv))
2597 2598
		pp |= PANEL_POWER_RESET;

2599 2600
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2601

2602
	wait_panel_on(intel_dp);
2603
	intel_dp->last_power_on = jiffies;
2604

2605
	if (IS_GEN5(dev_priv)) {
2606
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2607 2608
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
2609
	}
2610
}
2611

2612 2613
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
2614
	if (!intel_dp_is_edp(intel_dp))
2615 2616 2617 2618
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
2619
	pps_unlock(intel_dp);
2620 2621
}

2622 2623

static void edp_panel_off(struct intel_dp *intel_dp)
2624
{
2625
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2626
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2627
	u32 pp;
2628
	i915_reg_t pp_ctrl_reg;
2629

2630 2631
	lockdep_assert_held(&dev_priv->pps_mutex);

2632
	if (!intel_dp_is_edp(intel_dp))
2633
		return;
2634

2635
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2636
		      port_name(dig_port->base.port));
2637

2638
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2639
	     port_name(dig_port->base.port));
2640

2641
	pp = ironlake_get_pp_control(intel_dp);
2642 2643
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2644
	pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2645
		EDP_BLC_ENABLE);
2646

2647
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2648

2649 2650
	intel_dp->want_panel_vdd = false;

2651 2652
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2653

2654
	wait_panel_off(intel_dp);
2655
	intel_dp->panel_power_off_time = ktime_get_boottime();
2656 2657

	/* We got a reference when we enabled the VDD. */
2658
	intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2659
}
2660

2661 2662
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
2663
	if (!intel_dp_is_edp(intel_dp))
2664
		return;
2665

2666 2667
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2668
	pps_unlock(intel_dp);
2669 2670
}

2671 2672
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2673
{
2674
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2675
	u32 pp;
2676
	i915_reg_t pp_ctrl_reg;
2677

2678 2679 2680 2681 2682 2683
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2684
	wait_backlight_on(intel_dp);
2685

2686
	pps_lock(intel_dp);
2687

2688
	pp = ironlake_get_pp_control(intel_dp);
2689
	pp |= EDP_BLC_ENABLE;
2690

2691
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2692 2693 2694

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2695

2696
	pps_unlock(intel_dp);
2697 2698
}

2699
/* Enable backlight PWM and backlight PP control. */
2700 2701
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
			    const struct drm_connector_state *conn_state)
2702
{
2703 2704
	struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);

2705
	if (!intel_dp_is_edp(intel_dp))
2706 2707 2708 2709
		return;

	DRM_DEBUG_KMS("\n");

2710
	intel_panel_enable_backlight(crtc_state, conn_state);
2711 2712 2713 2714 2715
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2716
{
2717
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2718
	u32 pp;
2719
	i915_reg_t pp_ctrl_reg;
2720

2721
	if (!intel_dp_is_edp(intel_dp))
2722 2723
		return;

2724
	pps_lock(intel_dp);
2725

2726
	pp = ironlake_get_pp_control(intel_dp);
2727
	pp &= ~EDP_BLC_ENABLE;
2728

2729
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2730 2731 2732

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2733

2734
	pps_unlock(intel_dp);
2735 2736

	intel_dp->last_backlight_off = jiffies;
2737
	edp_wait_backlight_off(intel_dp);
2738
}
2739

2740
/* Disable backlight PP control and backlight PWM. */
2741
void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2742
{
2743 2744
	struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);

2745
	if (!intel_dp_is_edp(intel_dp))
2746 2747 2748
		return;

	DRM_DEBUG_KMS("\n");
2749

2750
	_intel_edp_backlight_off(intel_dp);
2751
	intel_panel_disable_backlight(old_conn_state);
2752
}
2753

2754 2755 2756 2757 2758 2759 2760 2761
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2762 2763
	bool is_enabled;

2764
	pps_lock(intel_dp);
2765
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2766
	pps_unlock(intel_dp);
2767 2768 2769 2770

	if (is_enabled == enable)
		return;

2771 2772
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2773 2774 2775 2776 2777 2778 2779

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2780 2781 2782 2783 2784 2785 2786 2787
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;

	I915_STATE_WARN(cur_state != state,
			"DP port %c state assertion failure (expected %s, current %s)\n",
2788
			port_name(dig_port->base.port),
2789
			onoff(state), onoff(cur_state));
2790 2791 2792 2793 2794 2795 2796 2797 2798
}
#define assert_dp_port_disabled(d) assert_dp_port((d), false)

static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
{
	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;

	I915_STATE_WARN(cur_state != state,
			"eDP PLL state assertion failure (expected %s, current %s)\n",
2799
			onoff(state), onoff(cur_state));
2800 2801 2802 2803
}
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

2804
static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2805
				const struct intel_crtc_state *pipe_config)
2806
{
2807
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2808
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2809

2810 2811 2812
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_disabled(dev_priv);
2813

2814
	DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2815
		      pipe_config->port_clock);
2816 2817 2818

	intel_dp->DP &= ~DP_PLL_FREQ_MASK;

2819
	if (pipe_config->port_clock == 162000)
2820 2821 2822 2823 2824 2825 2826 2827
		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
	else
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;

	I915_WRITE(DP_A, intel_dp->DP);
	POSTING_READ(DP_A);
	udelay(500);

2828 2829 2830 2831 2832 2833 2834
	/*
	 * [DevILK] Work around required when enabling DP PLL
	 * while a pipe is enabled going to FDI:
	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
	 * 2. Program DP PLL enable
	 */
	if (IS_GEN5(dev_priv))
2835
		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2836

2837
	intel_dp->DP |= DP_PLL_ENABLE;
2838

2839
	I915_WRITE(DP_A, intel_dp->DP);
2840 2841
	POSTING_READ(DP_A);
	udelay(200);
2842 2843
}

2844 2845
static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
				 const struct intel_crtc_state *old_crtc_state)
2846
{
2847
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2848
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2849

2850 2851 2852
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_enabled(dev_priv);
2853

2854 2855
	DRM_DEBUG_KMS("disabling eDP PLL\n");

2856
	intel_dp->DP &= ~DP_PLL_ENABLE;
2857

2858
	I915_WRITE(DP_A, intel_dp->DP);
2859
	POSTING_READ(DP_A);
2860 2861 2862
	udelay(200);
}

2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877
static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
{
	/*
	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
	 * be capable of signalling downstream hpd with a long pulse.
	 * Whether or not that means D3 is safe to use is not clear,
	 * but let's assume so until proven otherwise.
	 *
	 * FIXME should really check all downstream ports...
	 */
	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
		intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}

2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
					   const struct intel_crtc_state *crtc_state,
					   bool enable)
{
	int ret;

	if (!crtc_state->dsc_params.compression_enable)
		return;

	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
				 enable ? DP_DECOMPRESSION_EN : 0);
	if (ret < 0)
		DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
			      enable ? "enable" : "disable");
}

2894
/* If the sink supports it, try to set the power state appropriately */
2895
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2896 2897 2898 2899 2900 2901 2902 2903
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2904 2905 2906
		if (downstream_hpd_needs_d0(intel_dp))
			return;

2907 2908
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2909
	} else {
2910 2911
		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);

2912 2913 2914 2915 2916
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2917 2918
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2919 2920 2921 2922
			if (ret == 1)
				break;
			msleep(1);
		}
2923 2924 2925

		if (ret == 1 && lspcon->active)
			lspcon_wait_pcon_mode(lspcon);
2926
	}
2927 2928 2929 2930

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2931 2932
}

2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978
static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
				 enum port port, enum pipe *pipe)
{
	enum pipe p;

	for_each_pipe(dev_priv, p) {
		u32 val = I915_READ(TRANS_DP_CTL(p));

		if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
			*pipe = p;
			return true;
		}
	}

	DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));

	/* must initialize pipe to something for the asserts */
	*pipe = PIPE_A;

	return false;
}

bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
			   i915_reg_t dp_reg, enum port port,
			   enum pipe *pipe)
{
	bool ret;
	u32 val;

	val = I915_READ(dp_reg);

	ret = val & DP_PORT_EN;

	/* asserts want to know the pipe even if the port is disabled */
	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
		ret &= cpt_dp_port_selected(dev_priv, port, pipe);
	else if (IS_CHERRYVIEW(dev_priv))
		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
	else
		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;

	return ret;
}

2979 2980
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2981
{
2982
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2983
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2984
	bool ret;
2985

2986 2987
	if (!intel_display_power_get_if_enabled(dev_priv,
						encoder->power_domain))
2988 2989
		return false;

2990 2991
	ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
				    encoder->port, pipe);
2992

2993
	intel_display_power_put(dev_priv, encoder->power_domain);
2994 2995

	return ret;
2996
}
2997

2998
static void intel_dp_get_config(struct intel_encoder *encoder,
2999
				struct intel_crtc_state *pipe_config)
3000
{
3001
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3002 3003
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
3004
	enum port port = encoder->port;
3005
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3006

3007 3008 3009 3010
	if (encoder->type == INTEL_OUTPUT_EDP)
		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
	else
		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3011

3012
	tmp = I915_READ(intel_dp->output_reg);
3013 3014

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3015

3016
	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3017 3018 3019
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3020 3021 3022
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
3023

3024
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3025 3026 3027 3028
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
3029
		if (tmp & DP_SYNC_HS_HIGH)
3030 3031 3032
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
3033

3034
		if (tmp & DP_SYNC_VS_HIGH)
3035 3036 3037 3038
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
3039

3040
	pipe_config->base.adjusted_mode.flags |= flags;
3041

3042
	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3043 3044
		pipe_config->limited_color_range = true;

3045 3046 3047
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

3048 3049
	intel_dp_get_m_n(crtc, pipe_config);

3050
	if (port == PORT_A) {
3051
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3052 3053 3054 3055
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
3056

3057 3058 3059
	pipe_config->base.adjusted_mode.crtc_clock =
		intel_dotclock_calculate(pipe_config->port_clock,
					 &pipe_config->dp_m_n);
3060

3061
	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3062
	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3077 3078
			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3079
	}
3080 3081
}

3082
static void intel_disable_dp(struct intel_encoder *encoder,
3083 3084
			     const struct intel_crtc_state *old_crtc_state,
			     const struct drm_connector_state *old_conn_state)
3085
{
3086
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3087

3088 3089
	intel_dp->link_trained = false;

3090
	if (old_crtc_state->has_audio)
3091 3092
		intel_audio_codec_disable(encoder,
					  old_crtc_state, old_conn_state);
3093 3094 3095

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
3096
	intel_edp_panel_vdd_on(intel_dp);
3097
	intel_edp_backlight_off(old_conn_state);
3098
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3099
	intel_edp_panel_off(intel_dp);
3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113
}

static void g4x_disable_dp(struct intel_encoder *encoder,
			   const struct intel_crtc_state *old_crtc_state,
			   const struct drm_connector_state *old_conn_state)
{
	intel_disable_dp(encoder, old_crtc_state, old_conn_state);
}

static void vlv_disable_dp(struct intel_encoder *encoder,
			   const struct intel_crtc_state *old_crtc_state,
			   const struct drm_connector_state *old_conn_state)
{
	intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3114 3115
}

3116
static void g4x_post_disable_dp(struct intel_encoder *encoder,
3117 3118
				const struct intel_crtc_state *old_crtc_state,
				const struct drm_connector_state *old_conn_state)
3119
{
3120
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3121
	enum port port = encoder->port;
3122

3123 3124 3125 3126 3127 3128
	/*
	 * Bspec does not list a specific disable sequence for g4x DP.
	 * Follow the ilk+ sequence (disable pipe before the port) for
	 * g4x DP as it does not suffer from underruns like the normal
	 * g4x modeset sequence (disable pipe after the port).
	 */
3129
	intel_dp_link_down(encoder, old_crtc_state);
3130 3131

	/* Only ilk+ has port A */
3132
	if (port == PORT_A)
3133
		ironlake_edp_pll_off(intel_dp, old_crtc_state);
3134 3135
}

3136
static void vlv_post_disable_dp(struct intel_encoder *encoder,
3137 3138
				const struct intel_crtc_state *old_crtc_state,
				const struct drm_connector_state *old_conn_state)
3139
{
3140
	intel_dp_link_down(encoder, old_crtc_state);
3141 3142
}

3143
static void chv_post_disable_dp(struct intel_encoder *encoder,
3144 3145
				const struct intel_crtc_state *old_crtc_state,
				const struct drm_connector_state *old_conn_state)
3146
{
3147
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3148

3149
	intel_dp_link_down(encoder, old_crtc_state);
3150 3151 3152 3153

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
3154
	chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3155

3156
	mutex_unlock(&dev_priv->sb_lock);
3157 3158
}

3159 3160 3161 3162 3163
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
3164
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3165
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3166
	enum port port = intel_dig_port->base.port;
3167
	uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3168

3169
	if (dp_train_pat & train_pat_mask)
3170
		DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3171
			      dp_train_pat & train_pat_mask);
3172

3173
	if (HAS_DDI(dev_priv)) {
3174 3175 3176 3177 3178 3179 3180 3181
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3182
		switch (dp_train_pat & train_pat_mask) {
3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
3196 3197 3198
		case DP_TRAINING_PATTERN_4:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
			break;
3199 3200 3201
		}
		I915_WRITE(DP_TP_CTL(port), temp);

3202
	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3203
		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
3217
			DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3218 3219 3220 3221 3222
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
3223
		*DP &= ~DP_LINK_TRAIN_MASK;
3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
3236 3237
			DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
			*DP |= DP_LINK_TRAIN_PAT_2;
3238 3239 3240 3241 3242
			break;
		}
	}
}

3243
static void intel_dp_enable_port(struct intel_dp *intel_dp,
3244
				 const struct intel_crtc_state *old_crtc_state)
3245
{
3246
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3247 3248 3249

	/* enable with pattern 1 (as per spec) */

3250
	intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3251 3252 3253 3254 3255 3256 3257 3258

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;
3259
	if (old_crtc_state->has_audio)
3260
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3261 3262 3263

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
3264 3265
}

3266
static void intel_enable_dp(struct intel_encoder *encoder,
3267 3268
			    const struct intel_crtc_state *pipe_config,
			    const struct drm_connector_state *conn_state)
3269
{
3270
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3271
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3272
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3273
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3274
	enum pipe pipe = crtc->pipe;
3275

3276 3277
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
3278

3279 3280
	pps_lock(intel_dp);

3281
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3282
		vlv_init_panel_power_sequencer(encoder, pipe_config);
3283

3284
	intel_dp_enable_port(intel_dp, pipe_config);
3285 3286 3287 3288 3289 3290 3291

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

3292
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3293 3294
		unsigned int lane_mask = 0x0;

3295
		if (IS_CHERRYVIEW(dev_priv))
3296
			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3297

3298 3299
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
3300
	}
3301

3302
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3303
	intel_dp_start_link_train(intel_dp);
3304
	intel_dp_stop_link_train(intel_dp);
3305

3306
	if (pipe_config->has_audio) {
3307
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3308
				 pipe_name(pipe));
3309
		intel_audio_codec_enable(encoder, pipe_config, conn_state);
3310
	}
3311
}
3312

3313
static void g4x_enable_dp(struct intel_encoder *encoder,
3314 3315
			  const struct intel_crtc_state *pipe_config,
			  const struct drm_connector_state *conn_state)
3316
{
3317
	intel_enable_dp(encoder, pipe_config, conn_state);
3318
	intel_edp_backlight_on(pipe_config, conn_state);
3319
}
3320

3321
static void vlv_enable_dp(struct intel_encoder *encoder,
3322 3323
			  const struct intel_crtc_state *pipe_config,
			  const struct drm_connector_state *conn_state)
3324
{
3325
	intel_edp_backlight_on(pipe_config, conn_state);
3326 3327
}

3328
static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3329 3330
			      const struct intel_crtc_state *pipe_config,
			      const struct drm_connector_state *conn_state)
3331 3332
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3333
	enum port port = encoder->port;
3334

3335
	intel_dp_prepare(encoder, pipe_config);
3336

3337
	/* Only ilk+ has port A */
3338
	if (port == PORT_A)
3339
		ironlake_edp_pll_on(intel_dp, pipe_config);
3340 3341
}

3342 3343 3344
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3345
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3346
	enum pipe pipe = intel_dp->pps_pipe;
3347
	i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3348

3349 3350
	WARN_ON(intel_dp->active_pipe != INVALID_PIPE);

3351 3352 3353
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

3354 3355 3356
	edp_panel_vdd_off_sync(intel_dp);

	/*
3357
	 * VLV seems to get confused when multiple power sequencers
3358 3359 3360
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
3361
	 * selected in multiple power sequencers, but let's clear the
3362 3363 3364 3365
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3366
		      pipe_name(pipe), port_name(intel_dig_port->base.port));
3367 3368 3369 3370 3371 3372
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

3373
static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3374 3375 3376 3377 3378 3379
				      enum pipe pipe)
{
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

3380 3381 3382
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
		enum port port = encoder->port;
3383

3384 3385 3386 3387
		WARN(intel_dp->active_pipe == pipe,
		     "stealing pipe %c power sequencer from active (e)DP port %c\n",
		     pipe_name(pipe), port_name(port));

3388 3389 3390 3391
		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3392
			      pipe_name(pipe), port_name(port));
3393 3394

		/* make sure vdd is off before we steal it */
3395
		vlv_detach_power_sequencer(intel_dp);
3396 3397 3398
	}
}

3399 3400
static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
					   const struct intel_crtc_state *crtc_state)
3401
{
3402
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3403 3404
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3405 3406 3407

	lockdep_assert_held(&dev_priv->pps_mutex);

3408
	WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3409

3410 3411 3412 3413 3414 3415 3416
	if (intel_dp->pps_pipe != INVALID_PIPE &&
	    intel_dp->pps_pipe != crtc->pipe) {
		/*
		 * If another power sequencer was being used on this
		 * port previously make sure to turn off vdd there while
		 * we still have control of it.
		 */
3417
		vlv_detach_power_sequencer(intel_dp);
3418
	}
3419 3420 3421 3422 3423

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
3424
	vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3425

3426 3427
	intel_dp->active_pipe = crtc->pipe;

3428
	if (!intel_dp_is_edp(intel_dp))
3429 3430
		return;

3431 3432 3433 3434
	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3435
		      pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3436 3437

	/* init power sequencer on this pipe and port */
3438 3439
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3440 3441
}

3442
static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3443 3444
			      const struct intel_crtc_state *pipe_config,
			      const struct drm_connector_state *conn_state)
3445
{
3446
	vlv_phy_pre_encoder_enable(encoder, pipe_config);
3447

3448
	intel_enable_dp(encoder, pipe_config, conn_state);
3449 3450
}

3451
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3452 3453
				  const struct intel_crtc_state *pipe_config,
				  const struct drm_connector_state *conn_state)
3454
{
3455
	intel_dp_prepare(encoder, pipe_config);
3456

3457
	vlv_phy_pre_pll_enable(encoder, pipe_config);
3458 3459
}

3460
static void chv_pre_enable_dp(struct intel_encoder *encoder,
3461 3462
			      const struct intel_crtc_state *pipe_config,
			      const struct drm_connector_state *conn_state)
3463
{
3464
	chv_phy_pre_encoder_enable(encoder, pipe_config);
3465

3466
	intel_enable_dp(encoder, pipe_config, conn_state);
3467 3468

	/* Second common lane will stay alive on its own now */
3469
	chv_phy_release_cl2_override(encoder);
3470 3471
}

3472
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3473 3474
				  const struct intel_crtc_state *pipe_config,
				  const struct drm_connector_state *conn_state)
3475
{
3476
	intel_dp_prepare(encoder, pipe_config);
3477

3478
	chv_phy_pre_pll_enable(encoder, pipe_config);
3479 3480
}

3481
static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3482 3483
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state)
3484
{
3485
	chv_phy_post_pll_disable(encoder, old_crtc_state);
3486 3487
}

3488 3489 3490 3491
/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
3492
bool
3493
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3494
{
3495 3496
	return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3497 3498
}

3499
/* These are source-specific values. */
3500
uint8_t
3501
intel_dp_voltage_max(struct intel_dp *intel_dp)
3502
{
3503
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3504 3505
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	enum port port = encoder->port;
3506

3507
	if (HAS_DDI(dev_priv))
3508
		return intel_ddi_dp_voltage_max(encoder);
3509
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3510
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3511
	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3512
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3513
	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3514
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3515
	else
3516
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3517 3518
}

3519
uint8_t
3520 3521
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3522
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3523 3524
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	enum port port = encoder->port;
3525

3526 3527
	if (HAS_DDI(dev_priv)) {
		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3528
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3529
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3530 3531 3532 3533 3534 3535 3536
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3537
		default:
3538
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3539
		}
3540
	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3541
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3542 3543 3544 3545 3546
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
3547
		default:
3548
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3549 3550 3551
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3552 3553 3554 3555 3556 3557 3558
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3559
		default:
3560
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3561
		}
3562 3563 3564
	}
}

3565
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3566
{
3567
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3568 3569 3570 3571 3572
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3573
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3574 3575
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3576
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3577 3578 3579
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3580
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3581 3582 3583
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3584
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3585 3586 3587
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3588
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3589 3590 3591 3592 3593 3594 3595
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3596
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3597 3598
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3599
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3600 3601 3602
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3603
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3604 3605 3606
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3607
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3608 3609 3610 3611 3612 3613 3614
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3615
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3616 3617
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3618
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3619 3620 3621
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3622
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3623 3624 3625 3626 3627 3628 3629
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3630
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3631 3632
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3633
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

3645 3646
	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
				 uniqtranscale_reg_value, 0);
3647 3648 3649 3650

	return 0;
}

3651
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3652
{
3653 3654 3655
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	u32 deemph_reg_value, margin_reg_value;
	bool uniq_trans_scale = false;
3656 3657 3658
	uint8_t train_set = intel_dp->train_set[0];

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3659
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3660
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3661
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3662 3663 3664
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3665
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3666 3667 3668
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3669
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3670 3671 3672
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3673
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3674 3675
			deemph_reg_value = 128;
			margin_reg_value = 154;
3676
			uniq_trans_scale = true;
3677 3678 3679 3680 3681
			break;
		default:
			return 0;
		}
		break;
3682
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3683
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3684
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3685 3686 3687
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3688
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3689 3690 3691
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3692
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3693 3694 3695 3696 3697 3698 3699
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3700
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3701
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3702
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3703 3704 3705
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3706
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3707 3708 3709 3710 3711 3712 3713
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3714
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3715
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3716
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

3728 3729
	chv_set_phy_signal_level(encoder, deemph_reg_value,
				 margin_reg_value, uniq_trans_scale);
3730 3731 3732 3733

	return 0;
}

3734
static uint32_t
3735
g4x_signal_levels(uint8_t train_set)
3736
{
3737
	uint32_t	signal_levels = 0;
3738

3739
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3740
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3741 3742 3743
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3744
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3745 3746
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3747
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3748 3749
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3750
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3751 3752 3753
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3754
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3755
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3756 3757 3758
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3759
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3760 3761
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3762
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3763 3764
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3765
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3766 3767 3768 3769 3770 3771
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3772
/* SNB CPU eDP voltage swing and pre-emphasis control */
3773
static uint32_t
3774
snb_cpu_edp_signal_levels(uint8_t train_set)
3775
{
3776 3777 3778
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3779 3780
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3781
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3782
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3783
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3784 3785
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3786
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3787 3788
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3789
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3790 3791
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3792
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3793
	default:
3794 3795 3796
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3797 3798 3799
	}
}

3800
/* IVB CPU eDP voltage swing and pre-emphasis control */
3801
static uint32_t
3802
ivb_cpu_edp_signal_levels(uint8_t train_set)
3803 3804 3805 3806
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3807
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3808
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3809
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3810
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3811
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3812 3813
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3814
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3815
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3816
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3817 3818
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3819
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3820
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3821
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3822 3823 3824 3825 3826 3827 3828 3829 3830
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3831
void
3832
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3833
{
3834
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3835
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3836
	enum port port = intel_dig_port->base.port;
3837
	uint32_t signal_levels, mask = 0;
3838 3839
	uint8_t train_set = intel_dp->train_set[0];

3840
	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3841 3842
		signal_levels = bxt_signal_levels(intel_dp);
	} else if (HAS_DDI(dev_priv)) {
3843
		signal_levels = ddi_signal_levels(intel_dp);
3844
		mask = DDI_BUF_EMP_MASK;
3845
	} else if (IS_CHERRYVIEW(dev_priv)) {
3846
		signal_levels = chv_signal_levels(intel_dp);
3847
	} else if (IS_VALLEYVIEW(dev_priv)) {
3848
		signal_levels = vlv_signal_levels(intel_dp);
3849
	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3850
		signal_levels = ivb_cpu_edp_signal_levels(train_set);
3851
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3852
	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
3853
		signal_levels = snb_cpu_edp_signal_levels(train_set);
3854 3855
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3856
		signal_levels = g4x_signal_levels(train_set);
3857 3858 3859
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3860 3861 3862 3863 3864 3865 3866 3867
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3868

3869
	intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3870 3871 3872

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
3873 3874
}

3875
void
3876 3877
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat)
3878
{
3879
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3880 3881
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3882

3883
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3884

3885
	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3886
	POSTING_READ(intel_dp->output_reg);
3887 3888
}

3889
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3890
{
3891
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3892
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3893
	enum port port = intel_dig_port->base.port;
3894 3895
	uint32_t val;

3896
	if (!HAS_DDI(dev_priv))
3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

3914 3915 3916 3917
	if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
				    DP_TP_STATUS_IDLE_DONE,
				    DP_TP_STATUS_IDLE_DONE,
				    1))
3918 3919 3920
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3921
static void
3922 3923
intel_dp_link_down(struct intel_encoder *encoder,
		   const struct intel_crtc_state *old_crtc_state)
3924
{
3925 3926 3927 3928
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
	enum port port = encoder->port;
3929
	uint32_t DP = intel_dp->DP;
3930

3931
	if (WARN_ON(HAS_DDI(dev_priv)))
3932 3933
		return;

3934
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3935 3936
		return;

3937
	DRM_DEBUG_KMS("\n");
3938

3939
	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3940
	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3941
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3942
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3943
	} else {
3944
		DP &= ~DP_LINK_TRAIN_MASK;
3945
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3946
	}
3947
	I915_WRITE(intel_dp->output_reg, DP);
3948
	POSTING_READ(intel_dp->output_reg);
3949

3950 3951 3952 3953 3954 3955 3956 3957 3958
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
3959
	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3960 3961 3962 3963 3964 3965 3966
		/*
		 * We get CPU/PCH FIFO underruns on the other pipe when
		 * doing the workaround. Sweep them under the rug.
		 */
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

3967
		/* always enable with pattern 1 (as per spec) */
3968 3969 3970
		DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
			DP_LINK_TRAIN_PAT_1;
3971 3972 3973 3974
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3975
		I915_WRITE(intel_dp->output_reg, DP);
3976
		POSTING_READ(intel_dp->output_reg);
3977

3978
		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3979 3980
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3981 3982
	}

3983
	msleep(intel_dp->panel_power_down_delay);
3984 3985

	intel_dp->DP = DP;
3986 3987 3988 3989 3990 3991

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		pps_lock(intel_dp);
		intel_dp->active_pipe = INVALID_PIPE;
		pps_unlock(intel_dp);
	}
3992 3993
}

3994
bool
3995
intel_dp_read_dpcd(struct intel_dp *intel_dp)
3996
{
3997 3998
	if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
			     sizeof(intel_dp->dpcd)) < 0)
3999
		return false; /* aux transfer failed */
4000

4001
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4002

4003 4004
	return intel_dp->dpcd[DP_DPCD_REV] != 0;
}
4005

4006 4007 4008 4009 4010 4011 4012 4013
static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
{
	/*
	 * Clear the cached register set to avoid using stale values
	 * for the sinks that do not support DSC.
	 */
	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));

4014 4015 4016
	/* Clear fec_capable to avoid using stale values */
	intel_dp->fec_capable = 0;

4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028
	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
				     intel_dp->dsc_dpcd,
				     sizeof(intel_dp->dsc_dpcd)) < 0)
			DRM_ERROR("Failed to read DPCD register 0x%x\n",
				  DP_DSC_SUPPORT);

		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
			      (int)sizeof(intel_dp->dsc_dpcd),
			      intel_dp->dsc_dpcd);
4029

4030
		/* FEC is supported only on DP 1.4 */
4031 4032 4033 4034
		if (!intel_dp_is_edp(intel_dp) &&
		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
				      &intel_dp->fec_capable) < 0)
			DRM_ERROR("Failed to read FEC DPCD register\n");
4035

4036
		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4037 4038 4039
	}
}

4040 4041 4042 4043 4044
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp)
{
	struct drm_i915_private *dev_priv =
		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4045

4046 4047
	/* this function is meant to be called only once */
	WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4048

4049
	if (!intel_dp_read_dpcd(intel_dp))
4050 4051
		return false;

4052 4053
	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
			 drm_dp_is_branch(intel_dp->dpcd));
4054

4055 4056 4057
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
		dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
			DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4058

4059 4060 4061 4062 4063 4064 4065 4066 4067 4068
	/*
	 * Read the eDP display control registers.
	 *
	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
	 * set, but require eDP 1.4+ detection (e.g. for supported link rates
	 * method). The display control registers should read zero if they're
	 * not supported anyway.
	 */
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4069 4070
			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
			     sizeof(intel_dp->edp_dpcd))
4071
		DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4072
			      intel_dp->edp_dpcd);
4073

4074 4075 4076 4077 4078 4079
	/*
	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
	 */
	intel_psr_init_dpcd(intel_dp);

4080 4081
	/* Read the eDP 1.4+ supported link rates. */
	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4082
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4083 4084
		int i;

4085 4086
		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
				sink_rates, sizeof(sink_rates));
4087

4088 4089
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
4090 4091 4092 4093

			if (val == 0)
				break;

4094 4095 4096 4097 4098 4099
			/* Value read multiplied by 200kHz gives the per-lane
			 * link rate in kHz. The source rates are, however,
			 * stored in terms of LS_Clk kHz. The full conversion
			 * back to symbols is
			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
			 */
4100
			intel_dp->sink_rates[i] = (val * 200) / 10;
4101
		}
4102
		intel_dp->num_sink_rates = i;
4103
	}
4104

4105 4106 4107 4108
	/*
	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
	 */
4109 4110 4111 4112 4113
	if (intel_dp->num_sink_rates)
		intel_dp->use_rate_select = true;
	else
		intel_dp_set_sink_rates(intel_dp);

4114 4115
	intel_dp_set_common_rates(intel_dp);

4116 4117 4118 4119
	/* Read the eDP DSC DPCD registers */
	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
		intel_dp_get_dsc_sink_cap(intel_dp);

4120 4121 4122 4123 4124 4125 4126 4127 4128 4129
	return true;
}


static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
{
	if (!intel_dp_read_dpcd(intel_dp))
		return false;

4130
	/* Don't clobber cached eDP rates. */
4131
	if (!intel_dp_is_edp(intel_dp)) {
4132
		intel_dp_set_sink_rates(intel_dp);
4133 4134
		intel_dp_set_common_rates(intel_dp);
	}
4135

4136
	/*
4137 4138
	 * Some eDP panels do not set a valid value for sink count, that is why
	 * it don't care about read it here and in intel_edp_init_dpcd().
4139
	 */
4140 4141 4142
	if (!intel_dp_is_edp(intel_dp)) {
		u8 count;
		ssize_t r;
4143

4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164
		r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
		if (r < 1)
			return false;

		/*
		 * Sink count can change between short pulse hpd hence
		 * a member variable in intel_dp will track any changes
		 * between short pulse interrupts.
		 */
		intel_dp->sink_count = DP_GET_SINK_COUNT(count);

		/*
		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
		 * a dongle is present but no display. Unless we require to know
		 * if a dongle is present or not, we don't need to update
		 * downstream port information. So, an early return here saves
		 * time from performing other operations which are not required.
		 */
		if (!intel_dp->sink_count)
			return false;
	}
4165

4166
	if (!drm_dp_is_branch(intel_dp->dpcd))
4167 4168 4169 4170 4171
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

4172 4173 4174
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
			     intel_dp->downstream_ports,
			     DP_MAX_DOWNSTREAM_PORTS) < 0)
4175 4176 4177
		return false; /* downstream port status fetch failed */

	return true;
4178 4179
}

4180
static bool
4181
intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4182
{
4183
	u8 mstm_cap;
4184 4185 4186 4187

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

4188
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4189
		return false;
4190

4191
	return mstm_cap & DP_MST_CAP;
4192 4193
}

4194 4195 4196 4197 4198 4199 4200 4201
static bool
intel_dp_can_mst(struct intel_dp *intel_dp)
{
	return i915_modparams.enable_dp_mst &&
		intel_dp->can_mst &&
		intel_dp_sink_can_mst(intel_dp);
}

4202 4203 4204
static void
intel_dp_configure_mst(struct intel_dp *intel_dp)
{
4205 4206 4207 4208 4209 4210 4211
	struct intel_encoder *encoder =
		&dp_to_dig_port(intel_dp)->base;
	bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);

	DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
		      port_name(encoder->port), yesno(intel_dp->can_mst),
		      yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4212 4213 4214 4215

	if (!intel_dp->can_mst)
		return;

4216 4217
	intel_dp->is_mst = sink_can_mst &&
		i915_modparams.enable_dp_mst;
4218 4219 4220

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
					intel_dp->is_mst);
4221 4222 4223 4224 4225
}

static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4226 4227 4228
	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
				sink_irq_vector, DP_DPRX_ESI_LEN) ==
		DP_DPRX_ESI_LEN;
4229 4230
}

4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315
u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
				int mode_clock, int mode_hdisplay)
{
	u16 bits_per_pixel, max_bpp_small_joiner_ram;
	int i;

	/*
	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
	 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
	 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
	 * for MST -> TimeSlotsPerMTP has to be calculated
	 */
	bits_per_pixel = (link_clock * lane_count * 8 *
			  DP_DSC_FEC_OVERHEAD_FACTOR) /
		mode_clock;

	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
	max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
		mode_hdisplay;

	/*
	 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
	 * check, output bpp from small joiner RAM check)
	 */
	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);

	/* Error out if the max bpp is less than smallest allowed valid bpp */
	if (bits_per_pixel < valid_dsc_bpp[0]) {
		DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
		return 0;
	}

	/* Find the nearest match in the array of known BPPs from VESA */
	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
		if (bits_per_pixel < valid_dsc_bpp[i + 1])
			break;
	}
	bits_per_pixel = valid_dsc_bpp[i];

	/*
	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
	 * fractional part is 0
	 */
	return bits_per_pixel << 4;
}

u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
				int mode_clock,
				int mode_hdisplay)
{
	u8 min_slice_count, i;
	int max_slice_width;

	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
		min_slice_count = DIV_ROUND_UP(mode_clock,
					       DP_DSC_MAX_ENC_THROUGHPUT_0);
	else
		min_slice_count = DIV_ROUND_UP(mode_clock,
					       DP_DSC_MAX_ENC_THROUGHPUT_1);

	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
		DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
			      max_slice_width);
		return 0;
	}
	/* Also take into account max slice width */
	min_slice_count = min_t(uint8_t, min_slice_count,
				DIV_ROUND_UP(mode_hdisplay,
					     max_slice_width));

	/* Find the closest match to the valid slice count values */
	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
		if (valid_dsc_slicecount[i] >
		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
						    false))
			break;
		if (min_slice_count  <= valid_dsc_slicecount[i])
			return valid_dsc_slicecount[i];
	}

	DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
	return 0;
}

4316 4317
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
4318
	int status = 0;
4319
	int test_link_rate;
4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340
	uint8_t test_lane_count, test_link_bw;
	/* (DP CTS 1.2)
	 * 4.3.1.11
	 */
	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
				   &test_lane_count);

	if (status <= 0) {
		DRM_DEBUG_KMS("Lane count read failed\n");
		return DP_TEST_NAK;
	}
	test_lane_count &= DP_MAX_LANE_COUNT_MASK;

	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
				   &test_link_bw);
	if (status <= 0) {
		DRM_DEBUG_KMS("Link Rate read failed\n");
		return DP_TEST_NAK;
	}
	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4341 4342 4343 4344

	/* Validate the requested link rate and lane count */
	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
					test_lane_count))
4345 4346 4347 4348 4349 4350
		return DP_TEST_NAK;

	intel_dp->compliance.test_lane_count = test_lane_count;
	intel_dp->compliance.test_link_rate = test_link_rate;

	return DP_TEST_ACK;
4351 4352 4353 4354
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
4355
	uint8_t test_pattern;
4356
	uint8_t test_misc;
4357 4358 4359 4360
	__be16 h_width, v_height;
	int status = 0;

	/* Read the TEST_PATTERN (DP CTS 3.1.5) */
4361 4362
	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
				   &test_pattern);
4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383
	if (status <= 0) {
		DRM_DEBUG_KMS("Test pattern read failed\n");
		return DP_TEST_NAK;
	}
	if (test_pattern != DP_COLOR_RAMP)
		return DP_TEST_NAK;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
				  &h_width, 2);
	if (status <= 0) {
		DRM_DEBUG_KMS("H Width read failed\n");
		return DP_TEST_NAK;
	}

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
				  &v_height, 2);
	if (status <= 0) {
		DRM_DEBUG_KMS("V Height read failed\n");
		return DP_TEST_NAK;
	}

4384 4385
	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
				   &test_misc);
4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411
	if (status <= 0) {
		DRM_DEBUG_KMS("TEST MISC read failed\n");
		return DP_TEST_NAK;
	}
	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
		return DP_TEST_NAK;
	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
		return DP_TEST_NAK;
	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
	case DP_TEST_BIT_DEPTH_6:
		intel_dp->compliance.test_data.bpc = 6;
		break;
	case DP_TEST_BIT_DEPTH_8:
		intel_dp->compliance.test_data.bpc = 8;
		break;
	default:
		return DP_TEST_NAK;
	}

	intel_dp->compliance.test_data.video_pattern = test_pattern;
	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance.test_active = 1;

	return DP_TEST_ACK;
4412 4413 4414
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4415
{
4416
	uint8_t test_result = DP_TEST_ACK;
4417 4418 4419 4420
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
4421
	    connector->edid_corrupt ||
4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
4435
		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4436
	} else {
4437 4438 4439 4440 4441 4442 4443
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

4444 4445
		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
				       block->checksum) <= 0)
4446 4447 4448
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4449
		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4450 4451 4452
	}

	/* Set test active flag here so userspace doesn't interrupt things */
4453
	intel_dp->compliance.test_active = 1;
4454

4455 4456 4457 4458
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4459
{
4460 4461 4462 4463 4464 4465 4466
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
4467 4468
	uint8_t request = 0;
	int status;
4469

4470
	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4471 4472 4473 4474 4475
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

4476
	switch (request) {
4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
4494
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4495 4496 4497
		break;
	}

4498 4499 4500
	if (response & DP_TEST_ACK)
		intel_dp->compliance.test_type = request;

4501
update_status:
4502
	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4503 4504
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
4505 4506
}

4507 4508 4509 4510 4511 4512
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
4513
		u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4514 4515 4516
		int ret = 0;
		int retry;
		bool handled;
4517 4518

		WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4519 4520 4521 4522 4523
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
4524
			if (intel_dp->active_mst_links > 0 &&
4525
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4526 4527 4528 4529 4530
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

4531
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
4547
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4566 4567 4568 4569 4570
static bool
intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
{
	u8 link_status[DP_LINK_STATUS_SIZE];

4571
	if (!intel_dp->link_trained)
4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582
		return false;

	/*
	 * While PSR source HW is enabled, it will control main-link sending
	 * frames, enabling and disabling it so trying to do a retrain will fail
	 * as the link would or not be on or it could mix training patterns
	 * and frame data at the same time causing retrain to fail.
	 * Also when exiting PSR, HW will retrain the link anyways fixing
	 * any link status error.
	 */
	if (intel_psr_enabled(intel_dp))
4583 4584 4585
		return false;

	if (!intel_dp_get_link_status(intel_dp, link_status))
4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601
		return false;

	/*
	 * Validate the cached values of intel_dp->link_rate and
	 * intel_dp->lane_count before attempting to retrain.
	 */
	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
					intel_dp->lane_count))
		return false;

	/* Retrain if Channel EQ or CR not ok */
	return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
}

int intel_dp_retrain_link(struct intel_encoder *encoder,
			  struct drm_modeset_acquire_ctx *ctx)
4602 4603
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_connector *connector = intel_dp->attached_connector;
	struct drm_connector_state *conn_state;
	struct intel_crtc_state *crtc_state;
	struct intel_crtc *crtc;
	int ret;

	/* FIXME handle the MST connectors as well */

	if (!connector || connector->base.status != connector_status_connected)
		return 0;

	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
			       ctx);
	if (ret)
		return ret;

	conn_state = connector->base.state;

	crtc = to_intel_crtc(conn_state->crtc);
	if (!crtc)
		return 0;

	ret = drm_modeset_lock(&crtc->base.mutex, ctx);
	if (ret)
		return ret;

	crtc_state = to_intel_crtc_state(crtc->base.state);

	WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));

	if (!crtc_state->base.active)
		return 0;

	if (conn_state->commit &&
	    !try_wait_for_completion(&conn_state->commit->hw_done))
		return 0;

	if (!intel_dp_needs_link_retrain(intel_dp))
		return 0;
4644 4645 4646

	/* Suppress underruns caused by re-training */
	intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4647
	if (crtc_state->has_pch_encoder)
4648 4649 4650 4651 4652 4653 4654
		intel_set_pch_fifo_underrun_reporting(dev_priv,
						      intel_crtc_pch_transcoder(crtc), false);

	intel_dp_start_link_train(intel_dp);
	intel_dp_stop_link_train(intel_dp);

	/* Keep underrun reporting disabled until things are stable */
4655
	intel_wait_for_vblank(dev_priv, crtc->pipe);
4656 4657

	intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4658
	if (crtc_state->has_pch_encoder)
4659 4660
		intel_set_pch_fifo_underrun_reporting(dev_priv,
						      intel_crtc_pch_transcoder(crtc), true);
4661 4662

	return 0;
4663 4664
}

4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678
/*
 * If display is now connected check links status,
 * there has been known issues of link loss triggering
 * long pulse.
 *
 * Some sinks (eg. ASUS PB287Q) seem to perform some
 * weird HPD ping pong during modesets. So we can apparently
 * end up with HPD going low during a modeset, and then
 * going back up soon after. And once that happens we must
 * retrain the link to get a picture. That's in case no
 * userspace component reacted to intermittent HPD dip.
 */
static bool intel_dp_hotplug(struct intel_encoder *encoder,
			     struct intel_connector *connector)
4679
{
4680 4681 4682
	struct drm_modeset_acquire_ctx ctx;
	bool changed;
	int ret;
4683

4684
	changed = intel_encoder_hotplug(encoder, connector);
4685

4686
	drm_modeset_acquire_init(&ctx, 0);
4687

4688 4689
	for (;;) {
		ret = intel_dp_retrain_link(encoder, &ctx);
4690

4691 4692 4693 4694
		if (ret == -EDEADLK) {
			drm_modeset_backoff(&ctx);
			continue;
		}
4695

4696 4697
		break;
	}
4698

4699 4700 4701
	drm_modeset_drop_locks(&ctx);
	drm_modeset_acquire_fini(&ctx);
	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4702

4703
	return changed;
4704 4705
}

4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721
static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
{
	u8 val;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (drm_dp_dpcd_readb(&intel_dp->aux,
			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
		return;

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);

	if (val & DP_AUTOMATED_TEST_REQUEST)
		intel_dp_handle_test_request(intel_dp);

4722 4723 4724 4725 4726
	if (val & DP_CP_IRQ)
		intel_hdcp_check_link(intel_dp->attached_connector);

	if (val & DP_SINK_SPECIFIC_IRQ)
		DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4727 4728
}

4729 4730 4731 4732 4733 4734 4735
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
4736 4737 4738 4739 4740
 *
 * intel_dp_short_pulse -  handles short pulse interrupts
 * when full detection is not required.
 * Returns %true if short pulse is handled and full detection
 * is NOT required and %false otherwise.
4741
 */
4742
static bool
4743
intel_dp_short_pulse(struct intel_dp *intel_dp)
4744
{
4745
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4746 4747
	u8 old_sink_count = intel_dp->sink_count;
	bool ret;
4748

4749 4750 4751 4752
	/*
	 * Clearing compliance test variables to allow capturing
	 * of values for next automated test request.
	 */
4753
	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4754

4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765
	/*
	 * Now read the DPCD to see if it's actually running
	 * If the current value of sink count doesn't match with
	 * the value that was stored earlier or dpcd read failed
	 * we need to do full detection
	 */
	ret = intel_dp_get_dpcd(intel_dp);

	if ((old_sink_count != intel_dp->sink_count) || !ret) {
		/* No need to proceed if we are going to do full detect */
		return false;
4766 4767
	}

4768
	intel_dp_check_service_irq(intel_dp);
4769

4770 4771 4772
	/* Handle CEC interrupts, if any */
	drm_dp_cec_irq(&intel_dp->aux);

4773 4774 4775
	/* defer to the hotplug work for link retraining if needed */
	if (intel_dp_needs_link_retrain(intel_dp))
		return false;
4776

4777 4778
	intel_psr_short_pulse(intel_dp);

4779 4780 4781
	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
		DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
		/* Send a Hotplug Uevent to userspace to start modeset */
4782
		drm_kms_helper_hotplug_event(&dev_priv->drm);
4783
	}
4784 4785

	return true;
4786 4787
}

4788
/* XXX this is probably wrong for multiple downstream ports */
4789
static enum drm_connector_status
4790
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4791
{
4792
	struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4793 4794 4795
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

4796 4797 4798
	if (lspcon->active)
		lspcon_resume(lspcon);

4799 4800 4801
	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

4802
	if (intel_dp_is_edp(intel_dp))
4803 4804
		return connector_status_connected;

4805
	/* if there's no downstream port, we're done */
4806
	if (!drm_dp_is_branch(dpcd))
4807
		return connector_status_connected;
4808 4809

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4810 4811
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4812

4813 4814
		return intel_dp->sink_count ?
		connector_status_connected : connector_status_disconnected;
4815 4816
	}

4817 4818 4819
	if (intel_dp_can_mst(intel_dp))
		return connector_status_connected;

4820
	/* If no HPD, poke DDC gently */
4821
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4822
		return connector_status_connected;
4823 4824

	/* Well we tried, say unknown for unreliable port types */
4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4837 4838 4839

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4840
	return connector_status_disconnected;
4841 4842
}

4843 4844 4845
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
4846
	return connector_status_connected;
4847 4848
}

4849
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4850
{
4851
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4852
	u32 bit;
4853

4854 4855
	switch (encoder->hpd_pin) {
	case HPD_PORT_B:
4856 4857
		bit = SDE_PORTB_HOTPLUG;
		break;
4858
	case HPD_PORT_C:
4859 4860
		bit = SDE_PORTC_HOTPLUG;
		break;
4861
	case HPD_PORT_D:
4862 4863 4864
		bit = SDE_PORTD_HOTPLUG;
		break;
	default:
4865
		MISSING_CASE(encoder->hpd_pin);
4866 4867 4868 4869 4870 4871
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

4872
static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4873
{
4874
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4875 4876
	u32 bit;

4877 4878
	switch (encoder->hpd_pin) {
	case HPD_PORT_B:
4879 4880
		bit = SDE_PORTB_HOTPLUG_CPT;
		break;
4881
	case HPD_PORT_C:
4882 4883
		bit = SDE_PORTC_HOTPLUG_CPT;
		break;
4884
	case HPD_PORT_D:
4885 4886
		bit = SDE_PORTD_HOTPLUG_CPT;
		break;
4887
	default:
4888
		MISSING_CASE(encoder->hpd_pin);
4889 4890 4891 4892 4893 4894
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

4895
static bool spt_digital_port_connected(struct intel_encoder *encoder)
4896
{
4897
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4898 4899
	u32 bit;

4900 4901
	switch (encoder->hpd_pin) {
	case HPD_PORT_A:
4902 4903
		bit = SDE_PORTA_HOTPLUG_SPT;
		break;
4904
	case HPD_PORT_E:
4905 4906
		bit = SDE_PORTE_HOTPLUG_SPT;
		break;
4907
	default:
4908
		return cpt_digital_port_connected(encoder);
4909
	}
4910

4911
	return I915_READ(SDEISR) & bit;
4912 4913
}

4914
static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4915
{
4916
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4917
	u32 bit;
4918

4919 4920
	switch (encoder->hpd_pin) {
	case HPD_PORT_B:
4921 4922
		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
		break;
4923
	case HPD_PORT_C:
4924 4925
		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
		break;
4926
	case HPD_PORT_D:
4927 4928 4929
		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
		break;
	default:
4930
		MISSING_CASE(encoder->hpd_pin);
4931 4932 4933 4934 4935 4936
		return false;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

4937
static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4938
{
4939
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4940 4941
	u32 bit;

4942 4943
	switch (encoder->hpd_pin) {
	case HPD_PORT_B:
4944
		bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4945
		break;
4946
	case HPD_PORT_C:
4947
		bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4948
		break;
4949
	case HPD_PORT_D:
4950
		bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4951 4952
		break;
	default:
4953
		MISSING_CASE(encoder->hpd_pin);
4954
		return false;
4955 4956
	}

4957
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
4958 4959
}

4960
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4961
{
4962 4963 4964
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (encoder->hpd_pin == HPD_PORT_A)
4965 4966
		return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
	else
4967
		return ibx_digital_port_connected(encoder);
4968 4969
}

4970
static bool snb_digital_port_connected(struct intel_encoder *encoder)
4971
{
4972 4973 4974
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (encoder->hpd_pin == HPD_PORT_A)
4975 4976
		return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
	else
4977
		return cpt_digital_port_connected(encoder);
4978 4979
}

4980
static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4981
{
4982 4983 4984
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (encoder->hpd_pin == HPD_PORT_A)
4985 4986
		return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
	else
4987
		return cpt_digital_port_connected(encoder);
4988 4989
}

4990
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4991
{
4992 4993 4994
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	if (encoder->hpd_pin == HPD_PORT_A)
4995 4996
		return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
	else
4997
		return cpt_digital_port_connected(encoder);
4998 4999
}

5000
static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5001
{
5002
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5003 5004
	u32 bit;

5005 5006
	switch (encoder->hpd_pin) {
	case HPD_PORT_A:
5007 5008
		bit = BXT_DE_PORT_HP_DDIA;
		break;
5009
	case HPD_PORT_B:
5010 5011
		bit = BXT_DE_PORT_HP_DDIB;
		break;
5012
	case HPD_PORT_C:
5013 5014 5015
		bit = BXT_DE_PORT_HP_DDIC;
		break;
	default:
5016
		MISSING_CASE(encoder->hpd_pin);
5017 5018 5019 5020 5021 5022
		return false;
	}

	return I915_READ(GEN8_DE_PORT_ISR) & bit;
}

5023 5024 5025 5026 5027 5028 5029 5030
static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
				     struct intel_digital_port *intel_dig_port)
{
	enum port port = intel_dig_port->base.port;

	return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
}

5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062
static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
				    struct intel_digital_port *intel_dig_port,
				    bool is_legacy, bool is_typec, bool is_tbt)
{
	enum port port = intel_dig_port->base.port;
	enum tc_port_type old_type = intel_dig_port->tc_type;
	const char *type_str;

	WARN_ON(is_legacy + is_typec + is_tbt != 1);

	if (is_legacy) {
		intel_dig_port->tc_type = TC_PORT_LEGACY;
		type_str = "legacy";
	} else if (is_typec) {
		intel_dig_port->tc_type = TC_PORT_TYPEC;
		type_str = "typec";
	} else if (is_tbt) {
		intel_dig_port->tc_type = TC_PORT_TBT;
		type_str = "tbt";
	} else {
		return;
	}

	/* Types are not supposed to be changed at runtime. */
	WARN_ON(old_type != TC_PORT_UNKNOWN &&
		old_type != intel_dig_port->tc_type);

	if (old_type != intel_dig_port->tc_type)
		DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
			      type_str);
}

5063 5064 5065
static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
				  struct intel_digital_port *dig_port);

5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119
/*
 * This function implements the first part of the Connect Flow described by our
 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
 * lanes, EDID, etc) is done as needed in the typical places.
 *
 * Unlike the other ports, type-C ports are not available to use as soon as we
 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
 * display, USB, etc. As a result, handshaking through FIA is required around
 * connect and disconnect to cleanly transfer ownership with the controller and
 * set the type-C power state.
 *
 * We could opt to only do the connect flow when we actually try to use the AUX
 * channels or do a modeset, then immediately run the disconnect flow after
 * usage, but there are some implications on this for a dynamic environment:
 * things may go away or change behind our backs. So for now our driver is
 * always trying to acquire ownership of the controller as soon as it gets an
 * interrupt (or polls state and sees a port is connected) and only gives it
 * back when it sees a disconnect. Implementation of a more fine-grained model
 * will require a lot of coordination with user space and thorough testing for
 * the extra possible cases.
 */
static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
			       struct intel_digital_port *dig_port)
{
	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
	u32 val;

	if (dig_port->tc_type != TC_PORT_LEGACY &&
	    dig_port->tc_type != TC_PORT_TYPEC)
		return true;

	val = I915_READ(PORT_TX_DFLEXDPPMS);
	if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
		DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
		return false;
	}

	/*
	 * This function may be called many times in a row without an HPD event
	 * in between, so try to avoid the write when we can.
	 */
	val = I915_READ(PORT_TX_DFLEXDPCSSS);
	if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
		val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
	}

	/*
	 * Now we have to re-check the live state, in case the port recently
	 * became disconnected. Not necessary for legacy mode.
	 */
	if (dig_port->tc_type == TC_PORT_TYPEC &&
	    !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
		DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5120
		icl_tc_phy_disconnect(dev_priv, dig_port);
5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135
		return false;
	}

	return true;
}

/*
 * See the comment at the connect function. This implements the Disconnect
 * Flow.
 */
static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
				  struct intel_digital_port *dig_port)
{
	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);

5136
	if (dig_port->tc_type == TC_PORT_UNKNOWN)
5137 5138 5139
		return;

	/*
5140 5141
	 * TBT disconnection flow is read the live status, what was done in
	 * caller.
5142
	 */
5143 5144 5145 5146 5147
	if (dig_port->tc_type == TC_PORT_TYPEC ||
	    dig_port->tc_type == TC_PORT_LEGACY) {
		u32 val;

		val = I915_READ(PORT_TX_DFLEXDPCSSS);
5148 5149 5150
		val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
	}
5151 5152

	dig_port->tc_type = TC_PORT_UNKNOWN;
5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164
}

/*
 * The type-C ports are different because even when they are connected, they may
 * not be available/usable by the graphics driver: see the comment on
 * icl_tc_phy_connect(). So in our driver instead of adding the additional
 * concept of "usable" and make everything check for "connected and usable" we
 * define a port as "connected" when it is not only connected, but also when it
 * is usable by the rest of the driver. That maintains the old assumption that
 * connected ports are usable, and avoids exposing to the users objects they
 * can't really use.
 */
5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182
static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
				  struct intel_digital_port *intel_dig_port)
{
	enum port port = intel_dig_port->base.port;
	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
	bool is_legacy, is_typec, is_tbt;
	u32 dpsp;

	is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);

	/*
	 * The spec says we shouldn't be using the ISR bits for detecting
	 * between TC and TBT. We should use DFLEXDPSP.
	 */
	dpsp = I915_READ(PORT_TX_DFLEXDPSP);
	is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
	is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);

5183 5184
	if (!is_legacy && !is_typec && !is_tbt) {
		icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5185
		return false;
5186
	}
5187 5188 5189

	icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
				is_tbt);
5190

5191 5192 5193
	if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
		return false;

5194
	return true;
5195 5196 5197 5198 5199 5200 5201
}

static bool icl_digital_port_connected(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);

5202
	if (intel_port_is_combophy(dev_priv, encoder->port))
5203
		return icl_combo_port_connected(dev_priv, dig_port);
5204
	else if (intel_port_is_tc(dev_priv, encoder->port))
5205
		return icl_tc_port_connected(dev_priv, dig_port);
5206
	else
5207
		MISSING_CASE(encoder->hpd_pin);
5208 5209

	return false;
5210 5211
}

5212 5213
/*
 * intel_digital_port_connected - is the specified port connected?
5214
 * @encoder: intel_encoder
5215
 *
5216 5217 5218 5219 5220
 * In cases where there's a connector physically connected but it can't be used
 * by our hardware we also return false, since the rest of the driver should
 * pretty much treat the port as disconnected. This is relevant for type-C
 * (starting on ICL) where there's ownership involved.
 *
5221
 * Return %true if port is connected, %false otherwise.
5222
 */
5223
bool intel_digital_port_connected(struct intel_encoder *encoder)
5224
{
5225 5226
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

5227 5228
	if (HAS_GMCH_DISPLAY(dev_priv)) {
		if (IS_GM45(dev_priv))
5229
			return gm45_digital_port_connected(encoder);
5230
		else
5231
			return g4x_digital_port_connected(encoder);
5232 5233
	}

5234 5235 5236 5237
	if (INTEL_GEN(dev_priv) >= 11)
		return icl_digital_port_connected(encoder);
	else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
		return spt_digital_port_connected(encoder);
5238
	else if (IS_GEN9_LP(dev_priv))
5239
		return bxt_digital_port_connected(encoder);
5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250
	else if (IS_GEN8(dev_priv))
		return bdw_digital_port_connected(encoder);
	else if (IS_GEN7(dev_priv))
		return ivb_digital_port_connected(encoder);
	else if (IS_GEN6(dev_priv))
		return snb_digital_port_connected(encoder);
	else if (IS_GEN5(dev_priv))
		return ilk_digital_port_connected(encoder);

	MISSING_CASE(INTEL_GEN(dev_priv));
	return false;
5251 5252
}

5253
static struct edid *
5254
intel_dp_get_edid(struct intel_dp *intel_dp)
5255
{
5256
	struct intel_connector *intel_connector = intel_dp->attached_connector;
5257

5258 5259 5260 5261
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
5262 5263
			return NULL;

5264
		return drm_edid_duplicate(intel_connector->edid);
5265 5266 5267 5268
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
5269

5270 5271 5272 5273 5274
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
5275

5276
	intel_dp_unset_edid(intel_dp);
5277 5278 5279
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

5280
	intel_dp->has_audio = drm_detect_monitor_audio(edid);
5281
	drm_dp_cec_set_edid(&intel_dp->aux, edid);
5282 5283
}

5284 5285
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
5286
{
5287
	struct intel_connector *intel_connector = intel_dp->attached_connector;
5288

5289
	drm_dp_cec_unset_edid(&intel_dp->aux);
5290 5291
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
5292

5293 5294
	intel_dp->has_audio = false;
}
5295

5296
static int
5297 5298 5299
intel_dp_detect(struct drm_connector *connector,
		struct drm_modeset_acquire_ctx *ctx,
		bool force)
5300
{
5301 5302
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	struct intel_dp *intel_dp = intel_attached_dp(connector);
5303 5304
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &dig_port->base;
5305
	enum drm_connector_status status;
5306 5307
	enum intel_display_power_domain aux_domain =
		intel_aux_power_domain(dig_port);
5308

5309 5310
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
5311
	WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5312

5313
	intel_display_power_get(dev_priv, aux_domain);
5314

5315
	/* Can't disconnect eDP */
5316
	if (intel_dp_is_edp(intel_dp))
5317
		status = edp_detect(intel_dp);
5318
	else if (intel_digital_port_connected(encoder))
5319
		status = intel_dp_detect_dpcd(intel_dp);
5320
	else
5321 5322
		status = connector_status_disconnected;

5323
	if (status == connector_status_disconnected) {
5324
		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5325
		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5326

5327 5328 5329 5330 5331 5332 5333 5334 5335
		if (intel_dp->is_mst) {
			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
				      intel_dp->is_mst,
				      intel_dp->mst_mgr.mst_state);
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
							intel_dp->is_mst);
		}

5336
		goto out;
5337
	}
5338

5339
	if (intel_dp->reset_link_params) {
5340 5341
		/* Initial max link lane count */
		intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5342

5343 5344
		/* Initial max link rate */
		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5345 5346 5347

		intel_dp->reset_link_params = false;
	}
5348

5349 5350
	intel_dp_print_rates(intel_dp);

5351 5352 5353 5354
	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
	if (INTEL_GEN(dev_priv) >= 11)
		intel_dp_get_dsc_sink_cap(intel_dp);

5355 5356
	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
			 drm_dp_is_branch(intel_dp->dpcd));
5357

5358 5359 5360
	intel_dp_configure_mst(intel_dp);

	if (intel_dp->is_mst) {
5361 5362 5363 5364 5365
		/*
		 * If we are in MST mode then this connector
		 * won't appear connected or have anything
		 * with EDID on it
		 */
5366 5367
		status = connector_status_disconnected;
		goto out;
5368 5369 5370 5371 5372 5373
	}

	/*
	 * Some external monitors do not signal loss of link synchronization
	 * with an IRQ_HPD, so force a link status check.
	 */
5374 5375 5376 5377 5378
	if (!intel_dp_is_edp(intel_dp)) {
		int ret;

		ret = intel_dp_retrain_link(encoder, ctx);
		if (ret) {
5379
			intel_display_power_put(dev_priv, aux_domain);
5380 5381 5382
			return ret;
		}
	}
5383

5384 5385 5386 5387 5388 5389 5390 5391
	/*
	 * Clearing NACK and defer counts to get their exact values
	 * while reading EDID which are required by Compliance tests
	 * 4.2.2.4 and 4.2.2.5
	 */
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

5392
	intel_dp_set_edid(intel_dp);
5393 5394
	if (intel_dp_is_edp(intel_dp) ||
	    to_intel_connector(connector)->detect_edid)
5395
		status = connector_status_connected;
5396

5397
	intel_dp_check_service_irq(intel_dp);
5398

5399
out:
5400
	if (status != connector_status_connected && !intel_dp->is_mst)
5401
		intel_dp_unset_edid(intel_dp);
5402

5403
	intel_display_power_put(dev_priv, aux_domain);
5404
	return status;
5405 5406
}

5407 5408
static void
intel_dp_force(struct drm_connector *connector)
5409
{
5410
	struct intel_dp *intel_dp = intel_attached_dp(connector);
5411 5412
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &dig_port->base;
5413
	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5414 5415
	enum intel_display_power_domain aux_domain =
		intel_aux_power_domain(dig_port);
5416

5417 5418 5419
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
5420

5421 5422
	if (connector->status != connector_status_connected)
		return;
5423

5424
	intel_display_power_get(dev_priv, aux_domain);
5425 5426 5427

	intel_dp_set_edid(intel_dp);

5428
	intel_display_power_put(dev_priv, aux_domain);
5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
5442

5443
	/* if eDP has no EDID, fall back to fixed mode */
5444
	if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5445
	    intel_connector->panel.fixed_mode) {
5446
		struct drm_display_mode *mode;
5447 5448

		mode = drm_mode_duplicate(connector->dev,
5449
					  intel_connector->panel.fixed_mode);
5450
		if (mode) {
5451 5452 5453 5454
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
5455

5456
	return 0;
5457 5458
}

5459 5460 5461 5462
static int
intel_dp_connector_register(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
5463
	struct drm_device *dev = connector->dev;
5464 5465 5466 5467 5468
	int ret;

	ret = intel_connector_register(connector);
	if (ret)
		return ret;
5469 5470 5471 5472 5473 5474 5475

	i915_debugfs_connector_add(connector);

	DRM_DEBUG_KMS("registering %s bus for %s\n",
		      intel_dp->aux.name, connector->kdev->kobj.name);

	intel_dp->aux.dev = connector->kdev;
5476 5477 5478 5479 5480
	ret = drm_dp_aux_register(&intel_dp->aux);
	if (!ret)
		drm_dp_cec_register_connector(&intel_dp->aux,
					      connector->name, dev->dev);
	return ret;
5481 5482
}

5483 5484 5485
static void
intel_dp_connector_unregister(struct drm_connector *connector)
{
5486 5487 5488 5489
	struct intel_dp *intel_dp = intel_attached_dp(connector);

	drm_dp_cec_unregister_connector(&intel_dp->aux);
	drm_dp_aux_unregister(&intel_dp->aux);
5490 5491 5492
	intel_connector_unregister(connector);
}

5493
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5494
{
5495 5496
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5497

5498
	intel_dp_mst_encoder_cleanup(intel_dig_port);
5499
	if (intel_dp_is_edp(intel_dp)) {
5500
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5501 5502 5503 5504
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
5505
		pps_lock(intel_dp);
5506
		edp_panel_vdd_off_sync(intel_dp);
5507 5508
		pps_unlock(intel_dp);

5509 5510 5511 5512
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
5513
	}
5514 5515 5516

	intel_dp_aux_fini(intel_dp);

5517
	drm_encoder_cleanup(encoder);
5518
	kfree(intel_dig_port);
5519 5520
}

5521
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5522 5523 5524
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

5525
	if (!intel_dp_is_edp(intel_dp))
5526 5527
		return;

5528 5529 5530 5531
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
5532
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5533
	pps_lock(intel_dp);
5534
	edp_panel_vdd_off_sync(intel_dp);
5535
	pps_unlock(intel_dp);
5536 5537
}

5538 5539 5540 5541 5542
static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
				u8 *an)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5543 5544 5545 5546 5547 5548
	static const struct drm_dp_aux_msg msg = {
		.request = DP_AUX_NATIVE_WRITE,
		.address = DP_AUX_HDCP_AKSV,
		.size = DRM_HDCP_KSV_LEN,
	};
	uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5549 5550 5551 5552 5553 5554 5555
	ssize_t dpcd_ret;
	int ret;

	/* Output An first, that's easy */
	dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
				     an, DRM_HDCP_AN_LEN);
	if (dpcd_ret != DRM_HDCP_AN_LEN) {
5556 5557
		DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
			      dpcd_ret);
5558 5559 5560 5561 5562 5563 5564 5565 5566
		return dpcd_ret >= 0 ? -EIO : dpcd_ret;
	}

	/*
	 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
	 * order to get it on the wire, we need to create the AUX header as if
	 * we were writing the data, and then tickle the hardware to output the
	 * data once the header is sent out.
	 */
5567
	intel_dp_aux_header(txbuf, &msg);
5568

5569
	ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5570 5571
				rxbuf, sizeof(rxbuf),
				DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5572
	if (ret < 0) {
5573
		DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5574 5575
		return ret;
	} else if (ret == 0) {
5576
		DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590
		return -EIO;
	}

	reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
	return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
}

static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
				   u8 *bksv)
{
	ssize_t ret;
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
			       DRM_HDCP_KSV_LEN);
	if (ret != DRM_HDCP_KSV_LEN) {
5591
		DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
				      u8 *bstatus)
{
	ssize_t ret;
	/*
	 * For some reason the HDMI and DP HDCP specs call this register
	 * definition by different names. In the HDMI spec, it's called BSTATUS,
	 * but in DP it's called BINFO.
	 */
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
			       bstatus, DRM_HDCP_BSTATUS_LEN);
	if (ret != DRM_HDCP_BSTATUS_LEN) {
5609
		DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5610 5611 5612 5613 5614 5615
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
5616 5617
int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
			     u8 *bcaps)
5618 5619
{
	ssize_t ret;
5620

5621
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5622
			       bcaps, 1);
5623
	if (ret != 1) {
5624
		DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5625 5626
		return ret >= 0 ? -EIO : ret;
	}
5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641

	return 0;
}

static
int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
				   bool *repeater_present)
{
	ssize_t ret;
	u8 bcaps;

	ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
	if (ret)
		return ret;

5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653
	*repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
	return 0;
}

static
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
				u8 *ri_prime)
{
	ssize_t ret;
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
			       ri_prime, DRM_HDCP_RI_LEN);
	if (ret != DRM_HDCP_RI_LEN) {
5654
		DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
				 bool *ksv_ready)
{
	ssize_t ret;
	u8 bstatus;
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
			       &bstatus, 1);
	if (ret != 1) {
5669
		DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690
		return ret >= 0 ? -EIO : ret;
	}
	*ksv_ready = bstatus & DP_BSTATUS_READY;
	return 0;
}

static
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
				int num_downstream, u8 *ksv_fifo)
{
	ssize_t ret;
	int i;

	/* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
	for (i = 0; i < num_downstream; i += 3) {
		size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
		ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
				       DP_AUX_HDCP_KSV_FIFO,
				       ksv_fifo + i * DRM_HDCP_KSV_LEN,
				       len);
		if (ret != len) {
5691 5692
			DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
				      i, ret);
5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711
			return ret >= 0 ? -EIO : ret;
		}
	}
	return 0;
}

static
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
				    int i, u32 *part)
{
	ssize_t ret;

	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
		return -EINVAL;

	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
			       DP_AUX_HDCP_V_PRIME(i), part,
			       DRM_HDCP_V_PRIME_PART_LEN);
	if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5712
		DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
				    bool enable)
{
	/* Not used for single stream DisplayPort setups */
	return 0;
}

static
bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
{
	ssize_t ret;
	u8 bstatus;
5731

5732 5733 5734
	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
			       &bstatus, 1);
	if (ret != 1) {
5735
		DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5736
		return false;
5737
	}
5738

5739 5740 5741
	return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
}

5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756
static
int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
			  bool *hdcp_capable)
{
	ssize_t ret;
	u8 bcaps;

	ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
	if (ret)
		return ret;

	*hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
	return 0;
}

5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767
static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
	.read_bksv = intel_dp_hdcp_read_bksv,
	.read_bstatus = intel_dp_hdcp_read_bstatus,
	.repeater_present = intel_dp_hdcp_repeater_present,
	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
	.check_link = intel_dp_hdcp_check_link,
5768
	.hdcp_capable = intel_dp_hdcp_capable,
5769 5770
};

5771 5772
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
5773
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5774
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5788
	intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5789 5790 5791 5792

	edp_panel_vdd_schedule_off(intel_dp);
}

5793 5794
static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
{
5795
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5796 5797
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	enum pipe pipe;
5798

5799 5800 5801
	if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
				  encoder->port, &pipe))
		return pipe;
5802

5803
	return INVALID_PIPE;
5804 5805
}

5806
void intel_dp_encoder_reset(struct drm_encoder *encoder)
5807
{
5808
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5809 5810
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
	struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5811 5812 5813

	if (!HAS_DDI(dev_priv))
		intel_dp->DP = I915_READ(intel_dp->output_reg);
5814

5815
	if (lspcon->active)
5816 5817
		lspcon_resume(lspcon);

5818 5819
	intel_dp->reset_link_params = true;

5820 5821
	pps_lock(intel_dp);

5822 5823 5824
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		intel_dp->active_pipe = vlv_active_pipe(intel_dp);

5825
	if (intel_dp_is_edp(intel_dp)) {
5826
		/* Reinit the power sequencer, in case BIOS did something with it. */
5827
		intel_dp_pps_init(intel_dp);
5828 5829
		intel_edp_panel_vdd_sanitize(intel_dp);
	}
5830 5831

	pps_unlock(intel_dp);
5832 5833
}

5834
static const struct drm_connector_funcs intel_dp_connector_funcs = {
5835
	.force = intel_dp_force,
5836
	.fill_modes = drm_helper_probe_single_connector_modes,
5837 5838
	.atomic_get_property = intel_digital_connector_atomic_get_property,
	.atomic_set_property = intel_digital_connector_atomic_set_property,
5839
	.late_register = intel_dp_connector_register,
5840
	.early_unregister = intel_dp_connector_unregister,
5841
	.destroy = intel_connector_destroy,
5842
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5843
	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
5844 5845 5846
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5847
	.detect_ctx = intel_dp_detect,
5848 5849
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
5850
	.atomic_check = intel_digital_connector_atomic_check,
5851 5852 5853
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5854
	.reset = intel_dp_encoder_reset,
5855
	.destroy = intel_dp_encoder_destroy,
5856 5857
};

5858
enum irqreturn
5859 5860 5861
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5862
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5863
	enum irqreturn ret = IRQ_NONE;
5864

5865 5866 5867 5868 5869 5870 5871 5872
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5873
			      port_name(intel_dig_port->base.port));
5874
		return IRQ_HANDLED;
5875 5876
	}

5877
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5878
		      port_name(intel_dig_port->base.port),
5879
		      long_hpd ? "long" : "short");
5880

5881
	if (long_hpd) {
5882
		intel_dp->reset_link_params = true;
5883 5884 5885
		return IRQ_NONE;
	}

5886 5887
	intel_display_power_get(dev_priv,
				intel_aux_power_domain(intel_dig_port));
5888

5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900
	if (intel_dp->is_mst) {
		if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
			/*
			 * If we were in MST mode, and device is not
			 * there, get out of MST mode
			 */
			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
				      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
							intel_dp->is_mst);
			goto put_power;
5901
		}
5902
	}
5903

5904
	if (!intel_dp->is_mst) {
5905
		bool handled;
5906 5907 5908

		handled = intel_dp_short_pulse(intel_dp);

5909
		if (!handled)
5910
			goto put_power;
5911
	}
5912 5913 5914

	ret = IRQ_HANDLED;

5915
put_power:
5916 5917
	intel_display_power_put(dev_priv,
				intel_aux_power_domain(intel_dig_port));
5918 5919

	return ret;
5920 5921
}

5922
/* check the VBT to see whether the eDP is on another port */
5923
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5924
{
5925 5926 5927 5928
	/*
	 * eDP not supported on g4x. so bail out early just
	 * for a bit extra safety in case the VBT is bonkers.
	 */
5929
	if (INTEL_GEN(dev_priv) < 5)
5930 5931
		return false;

5932
	if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5933 5934
		return true;

5935
	return intel_bios_is_port_edp(dev_priv, port);
5936 5937
}

5938
static void
5939 5940
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
5941
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
5942 5943 5944 5945
	enum port port = dp_to_dig_port(intel_dp)->base.port;

	if (!IS_G4X(dev_priv) && port != PORT_A)
		intel_attach_force_audio_property(connector);
5946

5947
	intel_attach_broadcast_rgb_property(connector);
5948 5949 5950 5951
	if (HAS_GMCH_DISPLAY(dev_priv))
		drm_connector_attach_max_bpc_property(connector, 6, 10);
	else if (INTEL_GEN(dev_priv) >= 5)
		drm_connector_attach_max_bpc_property(connector, 6, 12);
5952

5953
	if (intel_dp_is_edp(intel_dp)) {
5954 5955 5956 5957 5958 5959 5960 5961
		u32 allowed_scalers;

		allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
		if (!HAS_GMCH_DISPLAY(dev_priv))
			allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);

		drm_connector_attach_scaling_mode_property(connector, allowed_scalers);

5962
		connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5963

5964
	}
5965 5966
}

5967 5968
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
5969
	intel_dp->panel_power_off_time = ktime_get_boottime();
5970 5971 5972 5973
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

5974
static void
5975
intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5976
{
5977
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5978
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5979
	struct pps_registers regs;
5980

5981
	intel_pps_get_registers(intel_dp, &regs);
5982 5983 5984

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
5985
	pp_ctl = ironlake_get_pp_control(intel_dp);
5986

5987 5988
	pp_on = I915_READ(regs.pp_on);
	pp_off = I915_READ(regs.pp_off);
5989 5990
	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
	    !HAS_PCH_ICP(dev_priv)) {
5991 5992
		I915_WRITE(regs.pp_ctrl, pp_ctl);
		pp_div = I915_READ(regs.pp_div);
5993
	}
5994 5995

	/* Pull timing values out of registers */
5996 5997
	seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		     PANEL_POWER_UP_DELAY_SHIFT;
5998

5999 6000
	seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		  PANEL_LIGHT_ON_DELAY_SHIFT;
6001

6002 6003
	seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		  PANEL_LIGHT_OFF_DELAY_SHIFT;
6004

6005 6006
	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		   PANEL_POWER_DOWN_DELAY_SHIFT;
6007

6008 6009
	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
	    HAS_PCH_ICP(dev_priv)) {
6010 6011
		seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
				BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
6012
	} else {
6013
		seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
6014
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
6015
	}
6016 6017
}

6018 6019 6020 6021 6022 6023 6024 6025 6026
static void
intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
{
	DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      state_name,
		      seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
}

static void
6027
intel_pps_verify_state(struct intel_dp *intel_dp)
6028 6029 6030 6031
{
	struct edp_power_seq hw;
	struct edp_power_seq *sw = &intel_dp->pps_delays;

6032
	intel_pps_readout_hw_state(intel_dp, &hw);
6033 6034 6035 6036 6037 6038 6039 6040 6041

	if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
	    hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
		DRM_ERROR("PPS state mismatch\n");
		intel_pps_dump_state("sw", sw);
		intel_pps_dump_state("hw", &hw);
	}
}

6042
static void
6043
intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6044
{
6045
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6046 6047 6048 6049 6050 6051 6052 6053 6054
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

6055
	intel_pps_readout_hw_state(intel_dp, &cur);
6056

6057
	intel_pps_dump_state("cur", &cur);
6058

6059
	vbt = dev_priv->vbt.edp.pps;
6060 6061 6062 6063 6064 6065
	/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
	 * of 500ms appears to be too short. Ocassionally the panel
	 * just fails to power back on. Increasing the delay to 800ms
	 * seems sufficient to avoid this problem.
	 */
	if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6066
		vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6067 6068 6069
		DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
			      vbt.t11_t12);
	}
6070 6071 6072 6073 6074
	/* T11_T12 delay is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	vbt.t11_t12 += 100 * 10;
6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

6088
	intel_pps_dump_state("vbt", &vbt);
6089 6090 6091

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
6092
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
6093 6094 6095 6096 6097 6098 6099 6100 6101
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

6102
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
6103 6104 6105 6106 6107 6108 6109
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

6110 6111 6112 6113 6114 6115
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6116 6117 6118 6119 6120 6121 6122 6123 6124 6125

	/*
	 * We override the HW backlight delays to 1 because we do manual waits
	 * on them. For T8, even BSpec recommends doing it. For T9, if we
	 * don't do this, we'll end up waiting for the backlight off delay
	 * twice: once when we do the manual sleep, and once when we disable
	 * the panel and wait for the PP_STATUS bit to become zero.
	 */
	final->t8 = 1;
	final->t9 = 1;
6126 6127 6128 6129 6130 6131

	/*
	 * HW has only a 100msec granularity for t11_t12 so round it up
	 * accordingly.
	 */
	final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6132 6133 6134
}

static void
6135
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6136
					      bool force_disable_vdd)
6137
{
6138
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6139
	u32 pp_on, pp_off, pp_div, port_sel = 0;
6140
	int div = dev_priv->rawclk_freq / 1000;
6141
	struct pps_registers regs;
6142
	enum port port = dp_to_dig_port(intel_dp)->base.port;
6143
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
6144

6145
	lockdep_assert_held(&dev_priv->pps_mutex);
6146

6147
	intel_pps_get_registers(intel_dp, &regs);
6148

6149 6150
	/*
	 * On some VLV machines the BIOS can leave the VDD
6151
	 * enabled even on power sequencers which aren't
6152 6153 6154 6155 6156 6157 6158
	 * hooked up to any port. This would mess up the
	 * power domain tracking the first time we pick
	 * one of these power sequencers for use since
	 * edp_panel_vdd_on() would notice that the VDD was
	 * already on and therefore wouldn't grab the power
	 * domain reference. Disable VDD first to avoid this.
	 * This also avoids spuriously turning the VDD on as
6159
	 * soon as the new power sequencer gets initialized.
6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173
	 */
	if (force_disable_vdd) {
		u32 pp = ironlake_get_pp_control(intel_dp);

		WARN(pp & PANEL_POWER_ON, "Panel power already on\n");

		if (pp & EDP_FORCE_VDD)
			DRM_DEBUG_KMS("VDD already on, disabling first\n");

		pp &= ~EDP_FORCE_VDD;

		I915_WRITE(regs.pp_ctrl, pp);
	}

6174
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
6175 6176
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
6177
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
6178 6179
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
6180 6181
	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
	    HAS_PCH_ICP(dev_priv)) {
6182
		pp_div = I915_READ(regs.pp_ctrl);
6183
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
6184
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6185 6186 6187 6188 6189 6190
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
6191 6192 6193

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
6194
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6195
		port_sel = PANEL_PORT_SELECT_VLV(port);
6196
	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6197 6198
		switch (port) {
		case PORT_A:
6199
			port_sel = PANEL_PORT_SELECT_DPA;
6200 6201 6202 6203 6204
			break;
		case PORT_C:
			port_sel = PANEL_PORT_SELECT_DPC;
			break;
		case PORT_D:
6205
			port_sel = PANEL_PORT_SELECT_DPD;
6206 6207 6208 6209 6210
			break;
		default:
			MISSING_CASE(port);
			break;
		}
6211 6212
	}

6213 6214
	pp_on |= port_sel;

6215 6216
	I915_WRITE(regs.pp_on, pp_on);
	I915_WRITE(regs.pp_off, pp_off);
6217 6218
	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
	    HAS_PCH_ICP(dev_priv))
6219
		I915_WRITE(regs.pp_ctrl, pp_div);
6220
	else
6221
		I915_WRITE(regs.pp_div, pp_div);
6222 6223

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6224 6225
		      I915_READ(regs.pp_on),
		      I915_READ(regs.pp_off),
6226 6227
		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
		       HAS_PCH_ICP(dev_priv)) ?
6228 6229
		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
		      I915_READ(regs.pp_div));
6230 6231
}

6232
static void intel_dp_pps_init(struct intel_dp *intel_dp)
6233
{
6234
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6235 6236

	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6237 6238
		vlv_initial_power_sequencer_setup(intel_dp);
	} else {
6239 6240
		intel_dp_init_panel_power_sequencer(intel_dp);
		intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6241 6242 6243
	}
}

6244 6245
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6246
 * @dev_priv: i915 device
6247
 * @crtc_state: a pointer to the active intel_crtc_state
6248 6249 6250 6251 6252 6253 6254 6255 6256
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
6257
static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6258
				    const struct intel_crtc_state *crtc_state,
6259
				    int refresh_rate)
6260 6261
{
	struct intel_encoder *encoder;
6262 6263
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
6264
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6265
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6266 6267 6268 6269 6270 6271

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

6272 6273
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
6274 6275 6276
		return;
	}

6277 6278
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
6279 6280 6281 6282 6283 6284

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

6285
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6286 6287 6288 6289
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

6290 6291
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
6292 6293
		index = DRRS_LOW_RR;

6294
	if (index == dev_priv->drrs.refresh_rate_type) {
6295 6296 6297 6298 6299
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

6300
	if (!crtc_state->base.active) {
6301 6302 6303 6304
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

6305
	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6306 6307
		switch (index) {
		case DRRS_HIGH_RR:
6308
			intel_dp_set_m_n(crtc_state, M1_N1);
6309 6310
			break;
		case DRRS_LOW_RR:
6311
			intel_dp_set_m_n(crtc_state, M2_N2);
6312 6313 6314 6315 6316
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
6317 6318
	} else if (INTEL_GEN(dev_priv) > 6) {
		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6319
		u32 val;
6320

6321
		val = I915_READ(reg);
6322
		if (index > DRRS_HIGH_RR) {
6323
			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6324 6325 6326
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
6327
		} else {
6328
			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6329 6330 6331
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6332 6333 6334 6335
		}
		I915_WRITE(reg, val);
	}

6336 6337 6338 6339 6340
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

6341 6342 6343
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
6344
 * @crtc_state: A pointer to the active crtc state.
6345 6346 6347
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
6348
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6349
			   const struct intel_crtc_state *crtc_state)
6350
{
6351
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6352

6353
	if (!crtc_state->has_drrs) {
6354 6355 6356 6357
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

6358 6359 6360 6361 6362
	if (dev_priv->psr.enabled) {
		DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
		return;
	}

6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376
	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

6377 6378 6379
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
6380
 * @old_crtc_state: Pointer to old crtc_state.
6381 6382
 *
 */
6383
void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6384
			    const struct intel_crtc_state *old_crtc_state)
6385
{
6386
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6387

6388
	if (!old_crtc_state->has_drrs)
6389 6390 6391 6392 6393 6394 6395 6396 6397
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6398 6399
		intel_dp_set_drrs_state(dev_priv, old_crtc_state,
			intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6400 6401 6402 6403 6404 6405 6406

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

6420
	/*
6421 6422
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
6423 6424
	 */

6425 6426
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
6427

6428 6429 6430 6431 6432 6433
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
		struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;

		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
			intel_dp->attached_connector->panel.downclock_mode->vrefresh);
	}
6434

6435 6436
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
6437 6438
}

6439
/**
6440
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6441
 * @dev_priv: i915 device
6442 6443
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
6444 6445
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6446 6447 6448
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
6449 6450
void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
			       unsigned int frontbuffer_bits)
6451 6452 6453 6454
{
	struct drm_crtc *crtc;
	enum pipe pipe;

6455
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6456 6457
		return;

6458
	cancel_delayed_work(&dev_priv->drrs.work);
6459

6460
	mutex_lock(&dev_priv->drrs.mutex);
6461 6462 6463 6464 6465
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

6466 6467 6468
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

6469 6470 6471
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

6472
	/* invalidate means busy screen hence upclock */
6473
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6474 6475
		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
			dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6476 6477 6478 6479

	mutex_unlock(&dev_priv->drrs.mutex);
}

6480
/**
6481
 * intel_edp_drrs_flush - Restart Idleness DRRS
6482
 * @dev_priv: i915 device
6483 6484
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
6485 6486 6487 6488
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
6489 6490 6491
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
6492 6493
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits)
6494 6495 6496 6497
{
	struct drm_crtc *crtc;
	enum pipe pipe;

6498
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6499 6500
		return;

6501
	cancel_delayed_work(&dev_priv->drrs.work);
6502

6503
	mutex_lock(&dev_priv->drrs.mutex);
6504 6505 6506 6507 6508
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

6509 6510
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
6511 6512

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6513 6514
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

6515
	/* flush means busy screen hence upclock */
6516
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6517 6518
		intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
				dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6519 6520 6521 6522 6523 6524

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
6525 6526 6527 6528 6529
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
Daniel Vetter's avatar
Daniel Vetter committed
6553 6554 6555 6556 6557 6558 6559 6560
 * The implementation is based on frontbuffer tracking implementation.  When
 * there is a disturbance on the screen triggered by user activity or a periodic
 * system activity, DRRS is disabled (RR is changed to high RR).  When there is
 * no movement on screen, after a timeout of 1 second, a switch to low RR is
 * made.
 *
 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
 * and intel_edp_drrs_flush() are called.
6561 6562 6563 6564 6565 6566 6567 6568
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6569
 * @connector: eDP connector
6570 6571 6572 6573 6574 6575 6576 6577 6578 6579
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
6580
static struct drm_display_mode *
6581 6582
intel_dp_drrs_init(struct intel_connector *connector,
		   struct drm_display_mode *fixed_mode)
6583
{
6584
	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6585 6586
	struct drm_display_mode *downclock_mode = NULL;

6587 6588 6589
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

6590
	if (INTEL_GEN(dev_priv) <= 6) {
6591 6592 6593 6594 6595
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6596
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6597 6598 6599
		return NULL;
	}

6600 6601
	downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
						    &connector->base);
6602 6603

	if (!downclock_mode) {
6604
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6605 6606 6607
		return NULL;
	}

6608
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6609

6610
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6611
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6612 6613 6614
	return downclock_mode;
}

6615
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6616
				     struct intel_connector *intel_connector)
6617
{
6618 6619
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
	struct drm_device *dev = &dev_priv->drm;
6620
	struct drm_connector *connector = &intel_connector->base;
6621
	struct drm_display_mode *fixed_mode = NULL;
6622
	struct drm_display_mode *downclock_mode = NULL;
6623 6624 6625
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
6626
	enum pipe pipe = INVALID_PIPE;
6627

6628
	if (!intel_dp_is_edp(intel_dp))
6629 6630
		return true;

6631 6632
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);

6633 6634 6635 6636 6637 6638
	/*
	 * On IBX/CPT we may get here with LVDS already registered. Since the
	 * driver uses the only internal power sequencer available for both
	 * eDP and LVDS bail out early in this case to prevent interfering
	 * with an already powered-on LVDS power sequencer.
	 */
6639
	if (intel_get_lvds_encoder(&dev_priv->drm)) {
6640 6641 6642 6643 6644 6645
		WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
		DRM_INFO("LVDS was detected, not registering eDP\n");

		return false;
	}

6646
	pps_lock(intel_dp);
6647 6648

	intel_dp_init_panel_power_timestamps(intel_dp);
6649
	intel_dp_pps_init(intel_dp);
6650
	intel_edp_panel_vdd_sanitize(intel_dp);
6651

6652
	pps_unlock(intel_dp);
6653

6654
	/* Cache DPCD and EDID for edp. */
6655
	has_dpcd = intel_edp_init_dpcd(intel_dp);
6656

6657
	if (!has_dpcd) {
6658 6659
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
6660
		goto out_vdd_off;
6661 6662
	}

6663
	mutex_lock(&dev->mode_config.mutex);
6664
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6665 6666
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
6667
			drm_connector_update_edid_property(connector,
6668 6669 6670 6671 6672 6673 6674 6675 6676 6677
								edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

6678
	/* prefer fixed mode from EDID if available */
6679 6680 6681
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
6682 6683
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
6684
			break;
6685 6686 6687 6688 6689 6690 6691
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
6692
		if (fixed_mode) {
6693
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6694 6695 6696
			connector->display_info.width_mm = fixed_mode->width_mm;
			connector->display_info.height_mm = fixed_mode->height_mm;
		}
6697
	}
6698
	mutex_unlock(&dev->mode_config.mutex);
6699

6700
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6701 6702
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
6703 6704 6705 6706 6707 6708

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
6709
		pipe = vlv_active_pipe(intel_dp);
6710 6711 6712 6713 6714 6715 6716 6717 6718

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
6719 6720
	}

6721
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6722
	intel_connector->panel.backlight.power = intel_edp_backlight_power;
6723
	intel_panel_setup_backlight(connector, pipe);
6724

6725 6726 6727 6728
	if (fixed_mode)
		drm_connector_init_panel_orientation_property(
			connector, fixed_mode->hdisplay, fixed_mode->vdisplay);

6729
	return true;
6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741

out_vdd_off:
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
	pps_lock(intel_dp);
	edp_panel_vdd_off_sync(intel_dp);
	pps_unlock(intel_dp);

	return false;
6742 6743
}

6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759
static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
{
	struct intel_connector *intel_connector;
	struct drm_connector *connector;

	intel_connector = container_of(work, typeof(*intel_connector),
				       modeset_retry_work);
	connector = &intel_connector->base;
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
		      connector->name);

	/* Grab the locks before changing connector property*/
	mutex_lock(&connector->dev->mode_config.mutex);
	/* Set connector link status to BAD and send a Uevent to notify
	 * userspace to do a modeset.
	 */
6760 6761
	drm_connector_set_link_status_property(connector,
					       DRM_MODE_LINK_STATUS_BAD);
6762 6763 6764 6765 6766
	mutex_unlock(&connector->dev->mode_config.mutex);
	/* Send Hotplug uevent so userspace can reprobe */
	drm_kms_helper_hotplug_event(connector->dev);
}

6767
bool
6768 6769
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
6770
{
6771 6772 6773 6774
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
6775
	struct drm_i915_private *dev_priv = to_i915(dev);
6776
	enum port port = intel_encoder->port;
6777
	int type;
6778

6779 6780 6781 6782
	/* Initialize the work for modeset in case of link train failure */
	INIT_WORK(&intel_connector->modeset_retry_work,
		  intel_dp_modeset_retry_work_fn);

6783 6784 6785 6786 6787
	if (WARN(intel_dig_port->max_lanes < 1,
		 "Not enough lanes (%d) for DP on port %c\n",
		 intel_dig_port->max_lanes, port_name(port)))
		return false;

6788 6789
	intel_dp_set_source_rates(intel_dp);

6790
	intel_dp->reset_link_params = true;
6791
	intel_dp->pps_pipe = INVALID_PIPE;
6792
	intel_dp->active_pipe = INVALID_PIPE;
6793

6794
	/* intel_dp vfuncs */
6795
	if (HAS_DDI(dev_priv))
6796 6797
		intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;

6798 6799
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
6800
	intel_dp->attached_connector = intel_connector;
6801

6802
	if (intel_dp_is_port_edp(dev_priv, port))
6803
		type = DRM_MODE_CONNECTOR_eDP;
6804 6805
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
6806

6807 6808 6809
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		intel_dp->active_pipe = vlv_active_pipe(intel_dp);

6810 6811 6812 6813 6814 6815 6816 6817
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

6818
	/* eDP only on port B and/or C on vlv/chv */
6819
	if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6820 6821
		    intel_dp_is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
6822 6823
		return false;

6824 6825 6826 6827
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

6828
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6829 6830
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

6831
	if (!HAS_GMCH_DISPLAY(dev_priv))
6832
		connector->interlace_allowed = true;
6833 6834
	connector->doublescan_allowed = 0;

6835
	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6836

6837
	intel_dp_aux_init(intel_dp);
6838

6839
	intel_connector_attach_encoder(intel_connector, intel_encoder);
6840

6841
	if (HAS_DDI(dev_priv))
6842 6843 6844 6845
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

6846
	/* init MST on ports that can support it */
6847
	if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6848 6849
	    (port == PORT_B || port == PORT_C ||
	     port == PORT_D || port == PORT_F))
6850 6851
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
6852

6853
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6854 6855 6856
		intel_dp_aux_fini(intel_dp);
		intel_dp_mst_encoder_cleanup(intel_dig_port);
		goto fail;
6857
	}
6858

6859
	intel_dp_add_properties(intel_dp, connector);
6860

6861
	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6862 6863 6864 6865
		int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
		if (ret)
			DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
	}
6866

6867 6868 6869 6870
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
6871
	if (IS_G45(dev_priv)) {
6872 6873 6874
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
6875 6876

	return true;
6877 6878 6879 6880 6881

fail:
	drm_connector_cleanup(connector);

	return false;
6882
}
6883

6884
bool intel_dp_init(struct drm_i915_private *dev_priv,
6885 6886
		   i915_reg_t output_reg,
		   enum port port)
6887 6888 6889 6890 6891 6892
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

6893
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6894
	if (!intel_dig_port)
6895
		return false;
6896

6897
	intel_connector = intel_connector_alloc();
Sudip Mukherjee's avatar
Sudip Mukherjee committed
6898 6899
	if (!intel_connector)
		goto err_connector_alloc;
6900 6901 6902 6903

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

6904 6905 6906
	if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
			     &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
			     "DP %c", port_name(port)))
6907
		goto err_encoder_init;
6908

6909
	intel_encoder->hotplug = intel_dp_hotplug;
6910
	intel_encoder->compute_config = intel_dp_compute_config;
6911
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
6912
	intel_encoder->get_config = intel_dp_get_config;
6913
	intel_encoder->suspend = intel_dp_encoder_suspend;
6914
	if (IS_CHERRYVIEW(dev_priv)) {
6915
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6916 6917
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6918
		intel_encoder->disable = vlv_disable_dp;
6919
		intel_encoder->post_disable = chv_post_disable_dp;
6920
		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6921
	} else if (IS_VALLEYVIEW(dev_priv)) {
6922
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6923 6924
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6925
		intel_encoder->disable = vlv_disable_dp;
6926
		intel_encoder->post_disable = vlv_post_disable_dp;
6927
	} else {
6928 6929
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
6930
		intel_encoder->disable = g4x_disable_dp;
6931
		intel_encoder->post_disable = g4x_post_disable_dp;
6932
	}
6933 6934

	intel_dig_port->dp.output_reg = output_reg;
6935
	intel_dig_port->max_lanes = 4;
6936

6937
	intel_encoder->type = INTEL_OUTPUT_DP;
6938
	intel_encoder->power_domain = intel_port_to_power_domain(port);
6939
	if (IS_CHERRYVIEW(dev_priv)) {
6940 6941 6942 6943 6944 6945 6946
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
6947
	intel_encoder->cloneable = 0;
6948
	intel_encoder->port = port;
6949

6950 6951
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;

6952 6953 6954
	if (port != PORT_A)
		intel_infoframe_init(intel_dig_port);

6955
	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
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Sudip Mukherjee committed
6956 6957 6958
	if (!intel_dp_init_connector(intel_dig_port, intel_connector))
		goto err_init_connector;

6959
	return true;
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Sudip Mukherjee committed
6960 6961 6962

err_init_connector:
	drm_encoder_cleanup(encoder);
6963
err_encoder_init:
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Sudip Mukherjee committed
6964 6965 6966
	kfree(intel_connector);
err_connector_alloc:
	kfree(intel_dig_port);
6967
	return false;
6968
}
6969

6970
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6971
{
6972 6973 6974 6975
	struct intel_encoder *encoder;

	for_each_intel_encoder(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp;
6976

6977 6978
		if (encoder->type != INTEL_OUTPUT_DDI)
			continue;
6979

6980
		intel_dp = enc_to_intel_dp(&encoder->base);
6981

6982
		if (!intel_dp->can_mst)
6983 6984
			continue;

6985 6986
		if (intel_dp->is_mst)
			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6987 6988 6989
	}
}

6990
void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6991
{
6992
	struct intel_encoder *encoder;
6993

6994 6995
	for_each_intel_encoder(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp;
6996
		int ret;
6997

6998 6999 7000 7001 7002 7003
		if (encoder->type != INTEL_OUTPUT_DDI)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);

		if (!intel_dp->can_mst)
7004
			continue;
7005

7006
		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7007
		if (ret)
7008
			intel_dp_check_mst_status(intel_dp);
7009 7010
	}
}